JP7179508B2 - Display device - Google Patents

Description

The present disclosure relates to display devices.

Since OLED (Organic Light-Emitting Diode) elements are current-driven self-luminous elements, they do not require a backlight, and have advantages such as low power consumption, a wide viewing angle, and a high contrast ratio. Expected in the development of flat panel displays.

2. Description of the Related Art In an active matrix type OLED display device, pixels are arranged vertically and horizontally in a matrix in a display area. This pixel comprises one or more sub-pixels. When a pixel comprises multiple sub-pixels, the multiple sub-pixels emit light of different colors, for example. A sub-pixel includes a transistor that selects the sub-pixel, and a pixel circuit composed of a driving TFT or the like that supplies a current to an OLED element that controls display of the sub-pixel. Transistors in OLED displays are thin film transistors (TFTs), and generally low temperature poly-silicon (LTPS) TFTs are used.
In a monochromatic OLED display device, only monochromatic pixels are arranged, but in a full-color OLED display device, red (R), green (G), and blue (B) sub-pixels of the three primary colors are arranged in combination. Alternatively, white (W) sub-pixels are arranged and R, G, and B color filters are arranged in combination to realize a full-color display.

The low-temperature polysilicon process crystallizes (polycrystallizes) an amorphous silicon (a-Si) film by an excimer laser annealing (ELA) apparatus to produce polysilicon (Poly-Si), which contains the active layers of TFTs. . An ELA device is a pulsed laser device with an elongated illumination area. The ELA device crystallizes a silicon film across the substrate in its elongated illuminated area. Therefore, the substrate is scanned in one direction while the irradiation position is shifted little by little so that the continuously irradiated pulsed laser beams partially overlap each other. Therefore, the polysilicon film has periodic characteristic fluctuations corresponding to the scan pitch determined by the pulse frequency and scan speed.

Since the sub-pixels are arranged at regular intervals in the display area, the sub-pixel pitch is usually determined based on the screen size and resolution. On the other hand, the ELA scan pitch is determined from a process point of view based on the basic characteristics of the TFT. Therefore, the positional relationship between the TFT (channel) position and the repeated irradiation position of the pulse laser light differs between the sub-pixels physically arranged at different positions in the scanning direction. Therefore, TFTs may have different characteristics between different pixel circuits.

For example, when the long axis of the ELA pulsed laser beam, which is elongated with respect to the display screen, is aligned with the horizontal direction of the display area, and the display area is scanned with the pulsed laser beam in the vertical direction, the displayed image has a certain period. Horizontal streaks may appear due to shading with Such horizontal streaks are also called display unevenness. In other words, due to the non-uniformity of the TFT characteristics, periodic striped unevenness may appear in the displayed image. Display unevenness due to non-uniformity of TFT characteristics may also appear in liquid crystal display devices, as disclosed in US Pat. No. 5,981,974, for example.

U.S. Pat. No. 5,981,974

Therefore, when the channel of a thin film transistor is annealed by irradiating a pulsed laser beam, there is a demand for a technique capable of reducing the difference in characteristics of the thin film transistor caused by the irradiation of the pulsed laser beam. This characteristic difference is the difference between the characteristic of the thin film transistor included in the first pixel circuit and the characteristic of the thin film transistor included in the second pixel circuit different from the first pixel circuit.

One embodiment of the present disclosure is a display device that includes a substrate, a plurality of light emitting elements over the substrate, and a plurality of pixel circuits that control the plurality of light emitting elements over the substrate. Each of the plurality of pixel circuits includes a thin film transistor. Each of the thin film transistors includes a channel. The channel comprises a first directional extension extending along a first direction and a second directional extension extending along a second direction. The absolute value of the angle between the first direction and the scanning direction of the pulsed laser beam for annealing the channel has a predetermined angle. The second direction is perpendicular to the scanning direction. The first direction extending portion and the second direction extending portion are alternately connected. At least one of both ends of each of the second direction extending portions is connected to the side along the first direction of the end portion of the first direction extending portion in the first direction. A linear first imaginary line extending from end to end in the second direction is defined in each of the second direction extending portions. At the position of the first imaginary line in the first direction, the product of the number of the first direction extending portions in the second direction and the channel width and the sum of the length of the first imaginary line are the same value. be. The number and channels of the linear second phantom line extending in the second direction overlapping the second phantom line at a position in the first direction where the second phantom line does not overlap the second direction extending portion The product of width is the same value. The dimension of the channel along the scanning direction is an integral multiple of the scanning pitch of the pulsed laser light.

According to one embodiment of the present disclosure, a difference in characteristics between thin film transistors can be reduced.

4 schematically shows how laser annealing is performed using a pulsed laser beam from an ELA apparatus. 4 is a graph showing the energy distribution in the minor axis direction of a linear pulse beam; It is the 1st figure which expands and shows typically the scanning direction front end of a pulsed laser beam. It is the 2nd figure which expands and shows the scanning direction front end of a pulsed laser beam typically. An example of the positional relationship between a polysilicon film having characteristics that vary according to the irradiation period of pulsed laser light and the channel of a TFT is schematically shown. 1 schematically shows a configuration example of an OLED display device. 4 shows a configuration example of a pixel circuit. 3 shows another configuration example of a pixel circuit. 1 schematically shows a cross-sectional structure of a portion including a driving TFT of an OLED display device; 3 shows another configuration example of a pixel circuit. 6 is a plan view of an element layout example of a pixel circuit having the circuit configuration shown in FIG. 5; FIG. The positional relationship among the pixels arranged in the scanning direction of the pulsed laser light, the channels of the drive TFTs in the pixels, and the successive irradiation positions of the pulsed laser light is schematically shown. An example of a set of N, n and P _ELA satisfying the relationship N×P _ELA =n×P _PIX is shown. A layout is shown in which the pixel pitch P- _PIX is 103.5 μm, the scan pitch P- _ELA is 18 μm, the pixel number n of the pixel unit is 4, and the ELA period number N is 23. Figure 10 shows numerical values that define the layout shown in Figure 9; FIG. 10 shows the positions of the channels in the pixel circuit in the layout shown in FIG. 9; FIG. The layout is shown with a pixel pitch P- _PIX of 103.5 μm, a scan pitch P- _ELA of 23 μm, the pixel number n of the pixel unit being 2, and the ELA period number N being 9. Figure 13 shows numerical values that define the layout shown in Figure 12; FIG. 13 shows the positions of the channels in the pixel circuit in the layout shown in FIG. 12; The layout is shown with a pixel pitch P- _PIX of 103.5 μm, a scan pitch P- _ELA of 21 μm, the pixel number n of the pixel unit being 14, and the ELA period number N being 69. Figure 15 shows numerical values that define the layout shown in Figure 15; FIG. 16 shows the positions of the channels in the pixel circuit in the layout shown in FIG. 15; An example of a positional relationship between a channel having a curved shape and an irradiation position of pulsed laser light is schematically shown. 4 shows a channel with a curved shape and the distribution of the channel's footprint with respect to the position in the scan direction; Figure 3 shows channels with other curved shapes and the distribution of their occupied area versus position in the scan direction; 21 is a diagram for explaining the details of the shape of the channel shown in FIG. 20; FIG. Examples of other channel shapes are shown. Fig. 3 shows the relationship between channels with R corners and channels with square corners; Examples of other channel shapes are shown. An example of a channel shape when the angle between the first direction and the scanning direction is 3 degrees is shown. An example of a channel shape when the angle between the first direction and the scanning direction is 10 degrees is shown. An example of a channel shape when the angle between the first direction and the scanning direction is 20 degrees is shown.

Embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present invention and does not limit the technical scope of the present invention.

[Overview]
In the OLED (Organic Light-Emitting Diode) display device disclosed below, the pixel circuit of the sub-pixel includes a thin film transistor (TFT: Thin Film Transistor) that selects the sub-pixel, and a driving TFT that supplies current to the sub-pixel. including. The TFTs in the pixel circuit are polysilicon TFTs, including polysilicon (Poly-Si) channels.

The polysilicon of the TFT is composed of so-called low temperature polysilicon (LTPS). The active layer of a TFT made of polysilicon is crystallized (polycrystallized) by scanning an amorphous silicon (a-Si) film with an elongated linear pulsed laser beam, and further undergoes processing such as photolithography and etching. It is formed by doing.

A pulsed laser device for crystallization is generally an excimer laser device, also called an excimer laser annealing (ELA) device. FIG. 1A schematically shows laser annealing by a pulsed laser beam 50 from an ELA apparatus. The pulsed laser beam 50 has an elongated linear shape, and when the longitudinal direction is the major axis and the short or lateral direction is the minor axis, the minor axis direction is parallel to the scanning direction, and the major axis direction is perpendicular to the scanning direction. . The short axis width 53 in FIG. 1A is the dimension of the irradiation area of the pulsed laser beam 50 in the short axis direction, and the long axis length 55 is the dimension of the irradiation area of the pulsed laser beam 50 in the long axis direction.

The ELA apparatus repeatedly irradiates the amorphous silicon film 47 with pulsed laser light while shifting the irradiation position little by little so that continuous pulsed laser light partially overlaps. The ELA apparatus generally changes the irradiation position by sliding the substrate 49 . The amorphous silicon film 47 is instantaneously melted by the pulsed laser light and then solidified to be crystallized. The entire amorphous silicon film 47 can be crystallized by scanning the elongated pulsed laser beam 50, but when viewed microscopically, traces of irradiation of the short-axis direction end portion of the pulsed laser beam 50 are crystallized. remains on the polysilicon film 40 . Therefore, the polysilicon film 40 has periodic characteristic fluctuations corresponding to the scan pitch (irradiation pitch) of the pulsed laser light.

Further, the crystallization process will be described with reference to FIGS. 1B to 1E. FIG. 1B is a graph showing the energy distribution in the minor axis direction of linear pulsed laser light. In FIG. 1B, the horizontal axis indicates coordinates in the minor axis direction, and the vertical axis indicates energy density. The energy distribution in the short axis direction of linear pulsed laser light is schematically represented by an ideal rectangle (dashed line 501 in the figure) as shown in FIG. (solid line 502 in the figure).

The process of crystallization of the polysilicon film 40 by the pulsed laser beam 50 will be explained with reference to FIGS. 1C and 1D. In FIGS. 1C and 1D, the substrate 49 is fixed and the irradiation position of the pulsed laser beam 50 is shown to move leftward (in the direction of the arrow in the drawing). First, FIG. 1C shows a state in which an arbitrary s-th shot is irradiated. Descriptions of traces before the s−1 shot are omitted. The silicon film on the front in the scanning direction (on the left side of the figure) is in an amorphous state (see reference numeral 47r), and the range Crs_S irradiated with the s-th shot of the pulsed laser beam 50 is crystallized. Uniform crystallization is performed in the region Crs41 irradiated with the first region of the pulsed laser beam 50 . The first region of the pulsed laser beam 50 corresponds to the center region of the pulsed laser beam where the energy density is flat (that is, the region with the highest energy density) in FIG. 1B.

On the other hand, the region Crs42 irradiated with the second region of the pulsed laser beam 50 is in a crystallized state different from that of the region Crs41. The second region of the pulsed laser beam 50 corresponds to the region where the energy density at the front end of the pulsed laser beam decreases with a slope in FIG. 1B. Also, in the region Crs43 irradiated with the third region of the pulsed laser beam 50, the polysilicon film 40 is not sufficiently crystallized. The third region of the pulsed laser beam 50 corresponds to the frontmost region in FIG. 1B where the energy drops below the crystallization threshold. The polysilicon film 40 remains in an amorphous state (see reference numeral 47r) in the further front (left side of the figure). In this manner, traces of irradiation of the pulsed laser beam are left on the polysilicon film 40 at the front edge of the s-th shot.

Next, the state of the s+1th shot at the same position will be described with reference to FIG. 1D. The ELA irradiates the pulsed laser light 50 while partially overlapping and shifting. That is, in FIG. 1D, the range Crs_S+1 irradiated with the s+1-th shot of the pulsed laser beam 50 is crystallized. A phenomenon similar to that of the s-th shot occurs at the leading edge in the scanning direction. The end portion of the irradiation mark formed by the s-th shot is irradiated with the first region of the pulsed laser beam 50 of the s+1-th shot. However, the process using laser beam light is a phenomenon that occurs when light energy is absorbed by the workpiece and becomes heat. Even if the irradiation energy is uniform, different optical properties on the workpiece side will result in different thermal energies.

In the case of FIG. 1D, the optical characteristics are different depending on the crystalline state of the polysilicon film 40 . In general, the absorptivity of the wavelength of the pulsed laser light used in ELA is higher in the amorphous state than in the polycrystalline state (polysilicon). Therefore, the trace formed at the leading edge in the scanning direction in the s-th shot, ie, the region with a different crystallization state, is not completely homogenized and remains in the s+1-th shot. Similarly, after the s+2nd shot, the difference in crystallinity cannot be completely homogenized, and as a result, regions with different crystallinity are periodically formed in the polysilicon film 40 . When a TFT is formed on such a polysilicon film 40, the transistor characteristics may vary depending on the region in which the TFT is formed and the difference in the crystallization state of the polysilicon film 40. FIG.

The irradiation positions of the pulsed laser light exist periodically at equal intervals determined by the pulse frequency and the scanning speed. If the irradiation position is defined as, for example, the short axis end in the scanning direction of the pulsed laser beam, the TFT characteristics of the TFTs in the pixel circuit may vary depending on the position relative to the irradiation position. can make a difference.

FIG. 1E schematically shows an example of the positional relationship between the polysilicon film 40 having characteristics that vary according to the irradiation cycle (spatial cycle) of the pulsed laser light and the channel 45 of the TFT. In the example of FIG. 1E, the TFTs are arranged so that the scanning direction 51 of the irradiation pulse laser light and the direction of the channel length L of the channel 45 of the TFTs are parallel. The short axis direction of the linear pulsed laser beam is parallel to the scanning direction 51 and the long axis direction is perpendicular to the scanning direction 51 .

For example, the dimension in the scanning direction 51 of the irradiation region of the pulsed laser light (minor axis width 53 of the linear pulsed laser light) is several hundred μm, and the scan pitch 52 is several tens of μm. A scan pitch 52 indicates a moving distance (irradiation interval) of one step of the pulsed laser light that is repeatedly irradiated. The long axis dimension (long axis length 55) of the linear pulsed laser beam is generally larger than the dimension of the display area in the direction parallel to the long axis.

In the example of FIG. 1E, the region of the polysilicon film 40 corresponding to one period of characteristic variation is divided into three regions 41, 42 and 43 for convenience of explanation. A region 41 is a region where only the region where the energy of the pulsed laser light is flat is irradiated in the above description of the crystallization process. Regions 42 and 43 are the vicinity of the irradiation of the leading edge in the scanning direction of the pulsed laser beam. . However, in reality, the characteristics of the polysilicon film 40 change continuously in the regions 41 to 42 and 43, rather than being distinguished by a clear boundary line as shown in the figure.

The regions 41 , 42 , and 43 are periodically arranged in this order in the scanning direction 51 in synchronization with the irradiation positions of the pulsed laser light (positions determined by the scanning pitch 52 ). A total dimension in the scanning direction 51 of the three continuous regions 41 , 42 and 43 matches the scanning pitch 52 .

It is considered that the characteristics of the channel 45 of the TFT substantially match the characteristics obtained by extracting the characteristics of the range corresponding to the channel length L from the polysilicon film 40 and averaging them. In the example of FIG. 1E, the channel 45 having the same area ratio of the three regions 41, 42, 43 forming the channel 45 is considered to have substantially the same characteristics.

An OLED element emits light by itself, and is largely different from a liquid crystal element in that it is current-driven. In a liquid crystal display device, a pixel is charged with a predetermined voltage by a pixel selection TFT that operates as a switch, and then the switch (selection TFT) is turned off to hold the voltage. That is, the display is determined by the charged voltage applied from the outside of the pixel.

On the other hand, in an OLED display device, like a liquid crystal display device, a voltage applied from the outside of a pixel is held, but the voltage is used to operate a pixel driving TFT to control a current flowing through an OLED element. Even if the TFTs are operated at the same voltage, if the transistor characteristics of the TFTs are different, the flowing current will be different. That is, among the pixel circuits, the transistor characteristics of the drive TFT have the greatest influence on the light emission of the OLED element.

Therefore, a pixel circuit of an OLED display device is generally designed to operate the driving TFT in the saturation region for luminance control. Also, in order to avoid the kink effect present in polysilicon TFTs and stabilize the saturation characteristics, the drive TFT is designed to have a long channel length. By arranging the long channel parallel to the scanning direction of the pulsed laser light, the periodic characteristic fluctuation of the polysilicon film is averaged. This averaging makes the driving TFT less susceptible to periodic characteristic variations of the polysilicon film 40 .

Therefore, it is important to reduce the characteristic difference of the channel of the driving TFT between the pixel circuits. In particular, it is important to reduce the characteristic difference of the channel of the driving TFT between the pixel circuits of the sub-pixels of the same color.

In one aspect of the present disclosure, the channels of the driving TFTs included in the plurality of pixel circuits of the same color or all colors are substantially the same in the pulse laser light irradiation cycle (spatial cycle) in the scanning direction of the pulse laser light. is placed at the phase position of To explain this state in terms of real space coordinates, a periodic characteristic distribution is formed in the polysilicon film by the pulsed laser beam as described above. If the irradiation position of the pulsed laser beam is defined by the leading edge in the minor axis direction (same as the scanning direction), patterns with the same characteristic distribution are formed at regular intervals (scan pitch) with respect to each irradiation position. Become.

On the other hand, the position of the channel of the TFT is tentatively defined by the front channel edge in the scanning direction of the pulsed laser beam. "Arranging the channels at the positions of the same phase in the irradiation period of the pulsed laser light" means that the distance between the position of the channel and the irradiation position of the nearest pulsed laser light is the same in all the channels of the drive TFTs. That's what it means. Since the channels of these drive TFTs have the same shape and the same orientation, the characteristic patterns of the polysilicon forming the channels match. Therefore, the characteristics of the drive TFTs of the pixels of the same color can be matched.

As described above, in the pixel circuit, the driving TFTs are arranged at the same position with respect to the irradiation position of the pulsed laser light, in other words, a position equivalent to the scan pitch of the pulsed laser light (position of the same phase). A driving TFT is arranged in the . As a result, it is possible to effectively reduce display unevenness that may occur due to laser annealing for crystallizing the silicon film.

Arranging the channels of the drive TFTs at the same phase positions in the irradiation cycle is particularly effective when the channels have a curved shape. If the channel is straight in the scan direction and its length (dimension in the scan direction) is an integer multiple of the scan pitch, the average properties of the polysilicon forming the channel are substantially the same. In the example of FIG. 1E, if the length L of the channel is an integral multiple of the scan pitch 52, the area ratios of the three regions 41, 42, and 43 that make up the channel are the same even if the channel is positioned at different phases. .

However, when the channel is curved, the channels arranged at different phase positions in the irradiation cycle of the pulsed laser light can have different area ratios of the three regions 41 , 42 , 43 . Channels with different area ratios of the three regions 41, 42, 43 have different properties, as described above. As described above, by arranging the channels of the driving TFTs at the positions of the same phase in the irradiation cycle of the pulsed laser light in the scanning direction of the pulsed laser light, channels of arbitrary channel shapes can have the same characteristic pattern. be able to.

In another aspect of the present disclosure, channels of driving TFTs included in a plurality of pixel circuits of the same color or all colors have specific shapes in order to reduce differences in channel characteristics due to differences in channel arrangement positions. More specifically, the channel has a specific curved shape, and its dimension along the scanning direction of the pulsed laser light is an integral multiple of the scanning pitch of the pulsed laser light. The channel has a specific bent shape so as to reduce the difference in the ratio of regions with different phases in the irradiation cycle of the pulsed laser light. Details of the specific bend shape will be described later.

Having the specific bend shape and dimensions of the channel can reduce the difference in channel properties between channels positioned at different locations. The channels do not need to be arranged at the same phase position in the irradiation cycle of the pulsed laser light.

The channels may be arranged at positions of the same phase in the irradiation cycle of the pulsed laser light. This makes it possible to further reduce the difference in characteristics between channels arranged at different positions. Alternatively, channels having the above-mentioned specific curved shape and having a dimension in the scanning direction of the pulsed laser beam different from an integer multiple of the scan pitch of the pulsed laser beam are arranged at positions of the same phase in the irradiation cycle of the pulsed laser beam. You may This makes it possible to reduce the difference in channel characteristics due to fluctuations in the channel position.

Embodiments will be specifically described below with reference to the drawings. The same reference numerals are given to the common components in each figure. In order to make the description easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated.

<Embodiment 1>
[overall structure]
FIG. 2 schematically shows a configuration example of the OLED display device 10. As shown in FIG. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements are formed, a sealing substrate 200 that seals the organic light emitting elements, and a bonding portion ( glass frit seal portion) 300. Dry air, for example, is enclosed between the TFT substrate 100 and the sealing substrate 200 and sealed by the joint portion 300 .

A scanning driver 131 , an emission driver 132 , a protection circuit 133 , a driver IC 134 and a demultiplexer 136 are arranged around the cathode electrode formation area 114 outside the display area 125 of the TFT substrate 100 . The driver IC 134 is connected to external equipment via an FPC (Flexible Printed Circuit) 135 .

A scanning driver 131 drives the scanning lines of the TFT substrate 100 . Emission driver 132 drives the emission control line to control the light emission period of each pixel. The driver IC 134 is mounted using, for example, an anisotropic conductive film (ACF).

The driver IC 134 supplies power and timing signals (control signals) to the scanning driver 131 and the emission driver 132 . In addition, driver IC 134 provides power and data signals to demultiplexer 136 .

The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 136 drives d times as many data lines as the number of output pins of the driver IC 134 by switching the output destination data line of the data signal from the driver IC 134 d times within the scanning period.

[Circuit configuration]
A plurality of pixel circuits are formed on the substrate 100 for controlling the currents supplied to the anode electrodes of the plurality of sub-pixels. FIG. 3A shows a configuration example of a pixel circuit. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls light emission of the OLED element E1. The transistors are TFTs.

A selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is a p-channel TFT, and its gate terminal is connected to the scanning line 106. FIG. A source terminal is connected to the data line 105 . The drain terminal is connected to the gate terminal of the drive transistor T1.

The drive transistor T1 is a transistor (drive TFT) for driving the OLED element E1. The drive transistor T1 is a p-channel TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. A source terminal of the driving transistor T1 is connected to the power supply line 108 (Vdd). The drain terminal is connected to the source terminal of the emission transistor T3. A holding capacitor C1 is formed between the gate terminal and the source terminal of the driving transistor T1.

The emission transistor T3 is a switch that controls supply and stop of the driving current to the OLED element E1. The emission transistor T3 is a p-channel TFT and has a gate terminal connected to the emission control line 107. FIG. The source terminal of the emission transistor T3 is connected to the drain terminal of the drive transistor T1. A drain terminal of the emission transistor T3 is connected to the OLED element E1.

Next, the operation of the pixel circuit will be described. The scanning driver 131 outputs a selection pulse to the scanning line 106 to turn on the selection transistor T2. A data voltage supplied from the driver IC 134 via the data line 105 is stored in the holding capacitor C1. The holding capacitor C1 holds the stored voltage throughout one frame period. The hold voltage causes the conductance of the driving transistor T1 to change in an analog manner, and the driving transistor T1 supplies a forward bias current corresponding to the emission gradation to the OLED element E1.

The emission transistor T3 is located on the drive current supply path. The emission driver 132 outputs a control signal to the emission control line 107 to control on/off of the emission transistor T3. When the emission transistor T3 is on, a drive current is supplied to the OLED element E1. This supply is stopped when the emission transistor T3 is in the off state. By controlling the on/off of the emission transistor T3, the lighting period (duty ratio) within one field period can be controlled.

FIG. 3B shows another configuration example of the pixel circuit. The pixel circuit has a reset transistor T4 instead of the emission transistor T3 of FIG. 3A. The reset transistor T4 controls electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from the reset control line 109 to the gate of the reset transistor T4.

The reset transistor T4 can be used for various purposes. The reset transistor T4 may be used for the purpose of temporarily resetting the anode electrode of the OLED element E1 to a sufficiently low voltage below the black signal level, for example, in order to suppress crosstalk due to leakage current between the OLED elements E1. .

Alternatively, the reset transistor T4 may be used for the purpose of measuring the characteristics of the drive transistor T1. For example, if the bias conditions are selected so that the drive transistor T1 operates in the saturation region and the reset transistor T4 operates in the linear region, and the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref) is measured, the drive The voltage-to-current conversion characteristic of transistor T1 can be accurately measured. If an external circuit generates a data signal that compensates for the difference in voltage-current conversion characteristics of the driving transistor T1 between sub-pixels, a highly uniform display image can be realized.

On the other hand, if the drive transistor T1 is turned off, the reset transistor T4 is operated in the linear region, and the voltage for causing the OLED element E1 to emit light is applied from the reference voltage supply line 110, the voltage-current characteristics of the OLED element E1 can be accurately measured. can do. For example, even if the OLED element E1 deteriorates due to long-term use, it is possible to extend the life by generating a data signal that compensates for the amount of deterioration in an external circuit.

The pixel circuits of FIGS. 3A and 3B are examples, and the pixel circuits may have other circuit configurations. Although the pixel circuits of FIGS. 3A and 3B use p-channel TFTs, the pixel circuits may also use n-channel TFTs. The pixel circuit described above is provided, for example, to compensate for variations in the threshold value of the driving transistor and suppress image quality deterioration. The display unevenness that has not been sufficiently suppressed by the pixel circuit can be suppressed by the technical means for suppressing the characteristic difference of the transistors described in this specification.

[Pixel structure]
Next, the outline of the structure of the pixel circuit and the light emitting element will be described. FIG. 4 schematically shows a cross-sectional structure of a portion including the driving TFT of the OLED display device 10. As shown in FIG. The OLED display device 10 includes a TFT substrate 100 and a sealing substrate 200 facing the TFT substrate 100 . Moreover, in the following description, up and down indicate up and down in the drawings.

The OLED display device 10 includes an insulating substrate 151 and a sealing structure facing the insulating substrate 151 . One example of a sealing structure is a flexible or inflexible sealing substrate 200 . The encapsulation structure may be, for example, a thin film encapsulation (TFE) structure.

The OLED display device 10 includes a lower electrode (eg, anode electrode 162), an upper electrode (eg, cathode electrode 166), and a plurality of organic light-emitting films 165 disposed between an insulating substrate 151 and a sealing structure. including.

An organic light emitting film 165 is arranged between the cathode electrode 166 and the anode electrode 162 . A plurality of anode electrodes 162 are arranged on the same plane (for example, on the planarizing film 161), and one organic light-emitting film 165 is arranged on one anode electrode 162. As shown in FIG. In the example of FIG. 4, the cathode electrode 166 of one sub-pixel is part of a continuous conductor film.

The OLED display device 10 has a plurality of post spacers (PS) 164 upstanding toward the encapsulation structure and a plurality of pixel circuits each including a plurality of switches. Each of the plurality of pixel circuits is formed between the insulating substrate 151 and the anode electrode 162 and controls current supplied to each of the plurality of anode electrodes 162 .

FIG. 4 is an example of a top emission type (OLED element) pixel structure. In the top emission type pixel structure, a cathode electrode 166 common to a plurality of pixels is arranged on the light emitting side (upper side in the drawing). The cathode electrode 166 has a shape that completely covers the entire surface of the display area 125 . A feature of the top-emission pixel structure is that the anode electrode 162 reflects light and the cathode electrode 166 is light transmissive. As a result, the light from the organic light-emitting film 165 is emitted toward the sealing structure.
In the top emission type, unlike the bottom emission type, in which light is extracted to the insulating substrate 151 side, it is not necessary to provide a transmissive region for extracting light within the pixel region. There is a high degree of freedom in the layout of the pixel circuit, such as being able to

As will be described later, the top-emission pixel structure allows (the channel of) the driving TFT to be easily arranged at a desired position according to the irradiation position of the pulsed laser beam for laser annealing of silicon. Note that the bottom emission type pixel structure has a transparent anode electrode and a reflective cathode electrode, and emits light to the outside through the insulating substrate 151 . The TFT layout of the present disclosure can also be applied to bottom emission pixel structures.

A sub-pixel typically displays either red, green, or blue in a full-color OLED display. One main pixel is composed of red, green, and blue sub-pixels. A pixel circuit containing a plurality of thin film transistors controls light emission of the corresponding OLED element. An OLED device is composed of an anode electrode that is a lower electrode, an organic light-emitting layer, and a cathode electrode that is an upper electrode.

The insulating substrate 151 is made of glass or resin, for example, and is an inflexible or flexible substrate. A polysilicon layer exists on the insulating substrate with a first insulating film 152 interposed therebetween, and the polysilicon layer has a channel 155 that provides the transistor characteristics of the TFT at a position where a gate electrode 157 will be formed later. . At both ends thereof, source/drain regions 168 and 169 doped with high-concentration impurities are present for electrical connection with upper wiring layers.

Between the channel 155 and the source/drain regions 168 and 169, an LDD (Lightly Doped Drain) doped with an impurity at a low concentration may be formed. It should be noted that LDD is omitted from the drawing for the sake of complication. A gate electrode 157 is formed on the polysilicon layer with a gate insulating film 156 interposed therebetween. An interlayer insulating film 158 is formed on the layer of gate electrode 157 .

A source electrode 159 and a drain electrode 160 are formed on the interlayer insulating film 158 in the display region 125 . The source electrode 159 and drain electrode 160 are made of, for example, a refractory metal or its alloy. Source electrode 159 and drain electrode 160 are connected to source/drain regions 168 and 169 of the polysilicon layer through contact holes 170 and 171 formed in interlayer insulating film 158 and gate insulating film 156, respectively.

An insulating planarization film 161 is formed on the source electrode 159 and the drain electrode 160 . An anode electrode 162 is formed on an insulating planarization film 161 . The anode electrode 162 is connected to the drain electrode 160 through a contact portion formed in a contact hole in the planarizing film 161 . A pixel circuit TFT is formed below the anode electrode 162 .

An insulating pixel defining layer (PDL) 163 separating the OLED elements is formed on the anode electrode 162 . OLED elements are formed in openings 167 in pixel defining layer 163 . An insulating spacer 164 is formed on the surface of the pixel defining layer 163 between the two anode electrodes 162 to maintain the spacing between the OLED elements and the encapsulation substrate 200 .

An organic light emitting film 165 is formed on the anode electrode 162 . The organic light emitting film 165 adheres to the pixel defining layer 163 in and around the opening 167 of the pixel defining layer 163 . A cathode electrode 166 is formed on the organic light emitting film 165 . The cathode electrode 166 is an electrode having optical transparency. The cathode electrode 166 transmits part of the visible light from the organic light-emitting film 165 . A laminated film of an anode electrode 162, an organic light-emitting film 165 and a cathode electrode 166 formed in an opening 167 of the pixel defining layer 163 constitutes an OLED element. A cap layer (not shown) may be formed on the cathode electrode 166 .

[Production method]
Next, an example of a method for manufacturing the OLED display device 10 will be described. In manufacturing the OLED display device 10 , first, silicon nitride, for example, is deposited on an insulating substrate 151 by CVD (Chemical Vapor Deposition) or the like to form a first insulating film 152 . Next, a layer containing the channel 155 (polysilicon layer) is formed using known low temperature polysilicon TFT manufacturing techniques. Specifically, for example, amorphous silicon is deposited by the CVD method and crystallized by the ELA described with reference to FIG. 1A to form a polysilicon film. The polysilicon film is processed into an island shape, and the source/drain regions 168 and 169 for connecting with the source electrode 159 and the drain electrode 160 are heavily doped with impurities to reduce the resistance. Similarly, the low-resistance polysilicon layer can also be used for connections between elements within the display area 125 .

Next, a gate insulating film 156 is formed on the polysilicon layer including the channel 155 by depositing, for example, a silicon oxide film by the CVD method or the like. Further, a metal material is deposited by a sputtering method or the like and patterned to form a metal layer including the gate electrode 157 .

In addition to the gate electrode 157, the metal layer includes, for example, storage capacitor electrodes, scanning lines 106, and emission control lines. As the metal layer, for example, one material selected from the group consisting of Mo, W, Nb, MoW, MoNb, Al, Nd, Ti, Cu, Cu alloys, Al alloys, Ag, Ag alloys to form a single layer, Alternatively, in order to reduce wiring resistance, a two-layer structure or a multi-layer structure of one or more materials selected from low-resistance materials such as Mo, Cu, Al, and Ag may be formed.

Next, an offset region is provided between the source/drain regions 168 and 169 doped with a high concentration impurity before forming the gate electrode 157 and the gate electrode 157 . This polysilicon film is doped with additional impurities using the gate electrode 157 as a mask to form a low-concentration impurity layer between the source/drain regions 168 and 169 and the channel 155 immediately below the gate electrode. As a result, the TFT has an LDD (Lightly Doped Drain) structure. Next, an interlayer insulating film 158 is formed by depositing, for example, a silicon oxide film or the like by the CVD method or the like.

Anisotropic etching is performed on the interlayer insulating film 158 and the gate insulating film 156 to open contact holes. Contact holes 170 and 171 connecting the source electrode 159 and the drain electrode 160 to the source/drain regions 168 and 169 are formed in the interlayer insulating film 158 and the gate insulating film 156 .

Next, a conductive film such as Ti/Al/Ti is deposited by sputtering or the like and patterned to form a metal layer. The metal layer includes source electrode 159 , drain electrode 160 and the inside of contact holes 170 and 171 . In addition, data lines 105, power supply lines 108, etc. are also formed on the same layer.

Next, a photosensitive organic material is deposited to form a planarization film 161 . Contact holes for connecting to the source electrode 159 and the drain electrode 160 of the TFT are opened by exposure and development. An anode electrode 162 is formed on the planarization film 161 in which the contact hole 172 is formed. The anode electrode 162 is made of a transparent film such as ITO, IZO, ZnO, In ₂ O ₃ , a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or an alloy containing these metals. It includes three layers, the reflective film and the transparent film described above. The three-layer structure of the anode electrode 162 is an example, and two layers may be used. Anode electrode 162 is connected to drain electrode 160 through contact hole 172 .

Next, for example, a photosensitive organic resin film is deposited by spin coating or the like, and patterning is performed to form the pixel definition layer 163 . An opening 167 is formed in the pixel defining layer 163 by patterning, and the anode electrode 162 of each sub-pixel is exposed at the bottom of the opening 167 formed. The sides of the opening 167 of the pixel defining layer 163 are forward tapered. A pixel defining layer 163 separates the light emitting area of each sub-pixel. Further, a photosensitive organic resin film, for example, is deposited by spin coating or the like and patterned to form spacers 164 on the pixel definition layer 163 .

Next, an organic light-emitting material is attached to the insulating substrate 151 on which the pixel definition layer 163 is formed to form an organic light-emitting film 165 . An organic light-emitting material is deposited for each color of RGB to form an organic light-emitting film 165 on the anode electrode 162 . The organic light-emitting film 165 is formed by depositing an organic light-emitting material on positions corresponding to the pixels using a metal mask. The organic light-emitting film 165 is composed of, for example, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer from the lower layer side. The laminated structure of the organic light-emitting film 165 is determined by design.

Next, a metal material for a cathode electrode 166 is attached to the TFT substrate 100 where the pixel definition layer 163, the spacers 164 and the organic light emitting film 165 (at the opening of the pixel definition layer 163) are exposed. The metal material deposited on the organic luminescent film 165 of one sub-pixel functions as the cathode electrode 166 of this sub-pixel in the open area of the pixel defining layer 163 .

The layer of the cathode electrode 166 is formed by, for example, depositing a metal such as Al, Mg, or an alloy containing these metals. If the resistance of the cathode electrode 166 is high and the uniformity of light emission luminance is impaired, an auxiliary electrode layer is added with a material for forming a transparent electrode such as ITO, IZO, ZnO or In2O3.

[Drive TFT layout]
An example of the layout within the display area of the driving transistors T1 of the plurality of pixel circuits will be described below. In particular, the relationship between the position of the channel of the drive TFT and the irradiation position of the ELA pulsed laser beam for generating polysilicon will be described in detail. For ease of explanation, an example of a pixel having the pixel circuit configuration shown in FIG. 5 will be explained. The pixel circuit of FIG. 5 has a configuration in which the emission transistor T3 and the emission control line are omitted from the pixel circuit shown in FIG. 3A. The following discussion can also be applied to other pixel circuit configurations, such as those shown in FIG. 3A or FIG. 3B.

FIG. 6 is a plan view of an element layout example of a pixel circuit having the circuit configuration shown in FIG. The pixel circuit includes a drive transistor T1, a select transistor T2, and a storage capacitor C1 for the drive transistor T1. The active layer of each TFT is a polysilicon film. A region overlapping with the gate electrode 157 is the channel 155 .

Both ends of the channel 155 (possibly sandwiching a lightly doped LDD region) are source/drain regions 168 and 168 heavily doped with impurities for electrical connection with the source electrode 159 and the drain electrode 160 . 169. The scanning line 106 and the lower electrode of the storage capacitor C1 are formed in the same metal layer (lower metal layer) as the gate electrode 157 . The data line 105, the power supply line 108, and the upper electrode of the storage capacitor C1 are formed on the same metal layer (upper metal layer) as the source electrode 159 and the drain electrode 160 are.

A source electrode 159 of the driving transistor T1 interconnects the power supply line 108 and the source region 168 of the polysilicon layer through a contact hole 170. FIG. Drain electrode 160 interconnects anode electrode 162 (not shown in FIG. 5) and drain region 169 of the polysilicon layer through contact hole 171 .

The channel 155 is a portion of the polysilicon film of the driving transistor T1 overlapping the gate electrode 157 in plan view. In the example of FIG. 6, the channel 155 is linear and extends parallel to the direction in which the data line 105 or the power line 108 extends (vertical direction in FIG. 6).

In the example shown in FIG. 6, the drive transistor T1 has a channel length of 40 μm and a channel width of 4 μm. The pixel pitch _PPIX in the direction in which the data lines 105 or the power lines 108 extend (vertical direction in FIG. 6) is 103.5 μm. As will be described later, the scanning direction of the pulsed laser light of the ELA apparatus is parallel to the direction of the pixel pitch. It should be noted that the layout and numerical values of the pixel elements shown in FIG. 6 are merely examples, and the features of this disclosure can be applied to pixels of other configurations and sizes.

In the following description, the channels 155 of the drive transistors T1 of all sub-pixels have the same shape (including size), the same orientation, and the same channel length and width by design. In other examples, the channels 155 of the drive transistors T1 of different color pixels may have different shapes. Due to manufacturing variations, the shape, orientation, length, and width of the channel 155 of each sub-pixel may vary slightly.

FIG. 7 schematically shows the positional relationship among the pixels 140 arranged in the scanning direction 51 of the pulsed laser beam 50, the channels 155 of the drive transistors T1 in the pixels, and the successive irradiation positions 56 of the pulsed laser beam 50. showing. Rectangles of 1, 2, . . . n indicated by the pixel 140 schematically indicate the areas occupied by individual pixels arranged at the pixel pitch _PPIX . For example, a rectangle that defines a boundary between adjacent light emitting regions corresponds. In FIGS. 7 to 17, sub-pixels are abbreviated as pixels unless otherwise specified.

The irradiation position 56 is a specific position in the short-axis direction of the irradiation area of each pulsed laser beam, for example, the short-axis end in the scanning direction of the pulsed laser beam. The irradiation position 56 may be any position that can define the scan pitch P _ELA of the pulsed laser beam 50 .

The channels 155 of the driving transistors T1 included in the pixel circuits of the pixels 140 are arranged at positions of the same phase in the irradiation cycle (positional cycle) of the pulse laser light in the scanning direction 51 of the pulse laser light. In the example of FIG. 7, the upper edge of each channel 155 in the figure coincides with the illumination position 56 . The channel-to-channel distance between adjacent pixels is an integral multiple of the scan pitch _PELA .

By arranging the channels 155 at different positions in the scanning direction 51 at the positions of the same phase in the irradiation period, the variation patterns of the characteristics of the polysilicon forming the channels 155 are matched, and the characteristics of the driving transistor T1 are matched. can be done.

As described above, the channel 155 is arranged at the same position with respect to the irradiation position of the pulsed laser beam, in other words, the channel 155 is arranged at a position equivalent to the scanning pitch of the pulsed laser beam. As a result, it is possible to effectively reduce display unevenness that may occur due to laser annealing for polysilicon film formation.

Usually the scan pitch is smaller than the pixel pitch. When the driving TFTs of different pixel circuits are arranged at the same position relative to the occupied area of the pixels, the positions of the driving TFTs of adjacent pixels in the scanning direction are the remainder obtained by dividing the pixel pitch by the scanning pitch. It is in a position shifted by a minute. The position of the channel 155 is determined according to the periodic irradiation position 56 of the pulsed laser light. This placement decision needs to satisfy the conditions for the entire display area, but if some pixel units are defined and the conditions are satisfied within that range, it can be easily expanded to the entire display area. It becomes possible.

In FIG. 7 , n consecutive pixels 140 are arranged in a row in the scanning direction 51 of the pulsed laser beam 50 . n is a natural number. The n pixels 140 constitute one pixel unit, and the size of the pixel unit in the scanning direction 51 is P _UNIT . A relationship of P _UNIT =n×P _PIX =N×P _ELA is established. N is a natural number and indicates the number of pulsed laser light irradiations (ELA cycle number) in the P _UNIT . In the example of FIG. 7, the scan pitch P _ELA is smaller than the pixel pitch P _PIX and N is larger than n.

A plurality of pixel units are arranged in a matrix to form a display area 125 . Therefore, the pattern of channel positions of the drive transistor T1 in the pixel unit is repeated in the scanning direction. Also, since the relationship P _UNIT =n×P _PIX =N×P _ELA is established, the relationship between the pixels 140 forming the pixel unit and the irradiation position 56 is repeated in the scanning direction 51 . By determining the pixel circuit layout of the pixel unit in this way, the pixel circuit layout of the entire display area 125 can be efficiently designed.

The scan pitch P _ELA should be a value that can be set in the ELA device. A typical ELA device can be set to an integer value in units of μm. In addition, even in an ELA apparatus capable of setting a scan pitch P _ELA including numbers below the decimal point, by setting the scan pitch P _ELA to an integer value or a simple value that does not carelessly increase the number of digits after the decimal point, The probability of malfunction due to hardware accuracy can be reduced.

In designing and manufacturing the OLED display device 10, for example, for a given pixel pitch P _PIX , N, n and P _ELA are determined that satisfy the relationship N×P _ELA =n×P _PIX . Once these are determined, in each pixel 140 in the pixel unit, the position of (the channel 155 of) the driving transistor T1 is determined so as to be in the same phase in the irradiation cycle.

In this example, the pixel pitch P _PIX is 103.5 μm. FIG. 8 shows an example set of N, n and P _ELA satisfying the relationship N×P _ELA =n×P _PIX . For example, by calculating n×P _PIX =P _UNIT at different n and factoring each value, for example so-called prime factorization, the desired integer P _ELA can be efficiently found.

For example, P _UNIT =n×P _PIX is 207 when the number of pixels in the pixel unit is n=2. Prime factorization of this value is expressed as 3 ² ×23. Therefore, the configurable _PELAs are 3, 9, 23, 69, and 207. For example, if a value near 20 μm is preferred for P _ELA , 23 μm is selected for P _ELA . The ELA cycle number N at this time is nine. Similarly, when the pixel number n=4, the _PELA value near 20 μm is 18 μm, and when the pixel number n=14, the _PELA value near 20 μm is 21 μm. The ELA cycle numbers N are 23 and 69, respectively.

In the following, three layout examples according to the above numerical values are described. FIG. 9 shows a layout with a pixel pitch P _PIX of 103.5 μm, a scan pitch P _ELA of 18 μm, a pixel unit number n of 4, and an ELA period number N of 23. FIG. FIG. 10 shows numerical values that define the layout.

A pixel unit consists of four pixels 140A-140D. The distance (inter-TFT distance) between the channels 155 of the driving transistors T1 of the pixels 140A and 140B is six times the scan pitch P _ELA (6×P _ELA ). The distance between the channel 155 of the drive transistor T1 of pixel 140B and pixel 140C is six times the scan pitch _PELA . The distance between the channel 155 of the driving transistor T1 of pixel 140C and pixel 140D is six times the scan pitch _PELA . The distance between the channel 155 of the drive transistor T1 of the pixel 140D and the pixel of the next pixel unit is five times the scan pitch P _ELA (5×P _ELA ).

The cumulative distance in FIG. 10 indicates the sum of pixel pitches _PPIX from the pixel 140A to the corresponding pixel. Also, the relative positions in FIG. 10 indicate relative positions within the pixel circuit of the channels 155 (drive transistors T1) in the pixels 140A to 140D. As shown in FIG. 11, the pixel circuit position of channel 155 in pixel 140A is defined as a reference position. Also, the ELA cycle number and the distance between TFTs of a certain pixel are the values from this pixel to another pixel adjacent in the scanning direction. It should be noted that FIG. 11 does not show the pixel array actually arranged horizontally, but shows a state in which a plurality of pixels included in the vertically arranged pixel array shown in FIG. 9 are individually arranged horizontally.

The relative position of channel 155 of pixel 140B is shifted by 4.5 μm in scanning direction 51 from the reference position. The relative positions of channels 155 of pixels 140C and 140D are offset from the reference position by 9.0 μm and 13.5 μm, respectively, in scan direction 51 .

FIG. 12 shows a layout with a pixel pitch P _PIX of 103.5 μm, a scan pitch P _ELA of 23 μm, a pixel number n of a pixel unit of 2, and an ELA cycle number N of nine. FIG. 13 shows numerical values that define the layout.

A pixel unit consists of two pixels 240A and 240B. The distance between the channels 155 of the driving transistors T1 of the pixels 240A and 240B (inter-TFT distance) is five times the scan pitch _PELA . The distance between the channel 155 of the drive transistor T1 of the pixel 240B and the pixel of the next pixel unit is four times the scan pitch _PELA . The channel-to-channel distance between adjacent pixels is an integer multiple of the scan pitch _PELA , and the maximum value of the difference is 1 times the scan pitch PELA.

The cumulative distance in FIG. 13 indicates the sum of the pixel pitches _PPIX from the pixel 240A to the corresponding pixel. Also, the relative positions in FIG. 13 indicate relative positions within the pixel circuit of the channels 155 (drive transistors T1) in the pixels 240A and 240B. As shown in FIG. 14, the pixel circuit position of channel 155 in pixel 240A is defined as a reference position. Also, the ELA cycle number and the inter-TFT distance of a certain pixel are values from this pixel to other pixels adjacent in the scanning direction. The relative position of channel 155 of pixel 240B is shifted by 11.5 μm in scanning direction 51 from the reference position. It should be noted that FIG. 14 does not actually show a pixel array arranged horizontally, but shows a state in which a plurality of pixels included in the vertically arranged pixel array shown in FIG. 12 are individually arranged horizontally.

FIG. 15 shows a layout with a pixel pitch P _PIX of 103.5 μm, a scan pitch P _ELA of 21 μm, a pixel unit number n of 14, and an ELA cycle number N of 69. FIG. FIG. 16 shows numerical values that define the layout.

The pixel unit consists of 14 pixels 340A-340N. The distance between the channels 155 of the driving transistors T1 of adjacent pixels (inter-TFT distance) is four times the scan pitch PELA only between the pixel _340N and the pixel of the next pixel unit, and the scan pitch P between the other adjacent pixels. 5 times that of _ELA .

The cumulative distance in FIG. 16 indicates the total sum of pixel pitches _PPIX from pixel 340A to the corresponding pixel. Also, the relative positions in FIG. 16 indicate relative positions within the pixel circuit of the channels 155 (drive transistors T1) in the pixels 340A to 340N. As shown in FIG. 17, the pixel circuit position of channel 155 in pixel 340A is defined as a reference position. The relative positions of channels 155 for pixels 340B-340N are as shown in FIG. FIG. 17 selects pixel 340A and pixel 340N from pixels 340A-340N to show the relative positions of channels 155 thereof. Also, the ELA cycle number and the distance between TFTs of a certain pixel are the values from this pixel to another pixel adjacent in the scanning direction.

As described above, by determining the position of the driving transistor T1 in the pixel circuit, the phase of the position of the channel 155 in different pixel circuits can be made the same with respect to the irradiation position. Also, the inter-channel distance between adjacent pixels is an integral multiple of the scan pitch _PELA , and in the above description, the maximum value of the difference is one scan pitch _PELA . Reducing the difference in channel-to-channel distance makes it easier to design the pixel circuit structure.
However, the action and effect of the present invention can be obtained if the channel-to-channel distance between adjacent pixels is an integral multiple of the scan pitch _PELA . Even if the maximum difference exceeds 1 times the scan pitch _PELA , the same effect can be obtained if the pixel circuit structure can be designed.
10, 13, and 16, the pixels are arranged in such order that the values of the relative positions are 0 and positive numbers. Even if the pixel arrangement is the same, if the reference pixel is changed, a negative numerical value appears in the relative position value, but these are all the same pixel arrangement.

If the channel positions are in the same phase in the ELA irradiation cycle, the channel characteristics can be the same regardless of the channel shape. However, in actual manufacturing, the channel position may deviate slightly from the designed position. If the channel has a linear shape and the dimension in the scanning direction is an integral multiple of the scanning pitch, even if the channel position slightly deviates from the design position, the change in characteristics between channels can be reduced.

In the above example, the pixel circuit is arranged in the section of the sub-pixel driven by the pixel circuit in plan view. However, the section occupied by the pixel circuit does not have to overlap the section occupied by the light emitting region of the corresponding sub-pixel in a plan view. In particular, the top emission type has a high degree of freedom in arranging the pixel circuit and the light emitting region of the sub-pixel, and the pixel circuit section and the pixel light emitting region section may be arranged so as to straddle between adjacent sub-pixels. . A pixel circuit of a sub-pixel different from this sub-pixel may be arranged in the section occupied by the light-emitting region of the sub-pixel. Sub-pixels with different display colors may have pixel circuits with different element layouts, and sub-pixels with the same display color may have pixel circuits with different element layouts. For example, there may be pixel circuits with structures that are symmetrical about a virtual axis.

In the display area 125, the channel positions of the drive TFTs of all pixels need not be in phase with the ELA irradiation period. For example, if the driving TFTs of the pixels of the same color are in phase with respect to the ELA irradiation period at the channel position, the driving TFTs of the pixels of different colors may be out of phase with respect to the ELA irradiation period at the channel position.

The above layout of the channels of the drive TFT may be applied to transistors different from the drive TFT, and may be applied to transistors of different types of display devices than OLED display devices. In addition, the above layout may be applied to transistors of a device in which TFTs are arranged in a matrix, such as an image sensor. Also, the present invention may be applied to a transistor that is a different type of transistor from the polysilicon transistor and that is annealed by pulsed laser light. For example, it may be applied to an oxide semiconductor transistor that is annealed with pulsed laser light.

<Embodiment 2>
[Flexible channel]
In the following, a drive TFT including a channel with a bent shape is described. Differences from the first embodiment will be mainly described below. Descriptions other than the channel shape and channel position described in the first embodiment can be applied to the second embodiment.

As the definition of a display device becomes higher, a curved channel is used in order to dispose a driving TFT having a long channel length L in a small area. FIG. 18 schematically shows an example of the positional relationship between a channel 551 having a curved shape and an irradiation position 56 of pulsed laser light. For ease of indication, the dashed rectangle surrounding the channel is indicated at 551 in FIG. This method of channel designation is also used in other figures below.

The curved channel 551 is configured by alternately connecting first portions extending in the scanning direction 51 and second portions extending in a direction perpendicular to the scanning direction 51 . Channel 551 has a channel length L and a channel width W. FIG.

As will be described later, when the channel has a curved shape, even if the channel size LB in the scanning direction 51 is an integral multiple of the scanning pitch _PELA , if the phases of the channel positions with respect to the irradiation period are different, The proportions of regions of different properties within the channel may differ. Therefore, individual driving TFTs can exhibit different characteristics.

In the following some examples of curved channel shapes are described. FIG. 19 shows a channel 551A having a curved shape and a distribution 559A of the area occupied by the channel 551A versus position in the scan direction 51. FIG. Channel 551A has channel length L, channel width W, and channel size LB1 in scan direction 51 .

Distribution 559 A shows the sum of the lengths of (the occupied area of) channel 551 A in the direction perpendicular to scan direction 51 at each position in scan direction 51 . In other words, an imaginary line extending perpendicular to the scanning direction 51 at each position in the scanning direction 51 indicates the sum of the lengths of portions overlapping the channel 551A.

As can be seen from the shape of distribution 559A, channel 551A in FIG. 19 varies greatly in sum of lengths (or area) depending on the position in scanning direction 51 . In FIG. 19, the distribution 559A has two peaks 560 at positions including the line indicating the irradiation position 56. In FIG. The position of this peak 560 also changes for channels out of phase with respect to the ELA illumination period. In other words, the ratio of regions having different characteristics in each sub-pixel channel is significantly different. If the channel positions of different channels are in phase with respect to the ELA illumination period, they can exhibit identical channel characteristics, as described above. However, when out of phase, their channel characteristics can show significant differences.

FIG. 20 shows a channel 551B with another curved shape and a distribution 559B of the area occupied by channel 551B with respect to position in scan direction 51. FIG. Channel 551B has channel length L, channel width W, and channel size LB2 in scan direction 51 .

As distribution 559B shows, channel 551B has a constant sum of lengths (or area) with respect to position in scan direction 51 . That is, the length sum of all positions in the scanning direction 51 is the same value. Therefore, if the channel size LB is an integral multiple of the scan pitch _PELA , the difference in the proportion of regions with different characteristics within the channel in different TFTs will be small, or substantially eliminated.
In FIG. 20, the characteristics of a transistor having a curved channel are described as a synthesis of individual characteristics corresponding to the phases of channel elements regardless of the direction of current flow. The reason why such a description is possible will be explained at the end of the second embodiment.

FIG. 21 is a diagram for explaining the details of the shape of channel 551B shown in FIG. The channel 551B has a shape in which a plurality of rectangles are combined, and has a constant channel width W in the straight portion along the current path. A channel length L (see FIG. 20) is defined between channel ends 556 and 557 along the centerline of the current path. The channel 551B is composed of first direction extending portions 553A, 553B and 553C extending in a first direction along the scanning direction 51 and second direction extending portions 554A and 554B extending in a second direction perpendicular to the scanning direction 51. It is configured.

In FIG. 21, the scan direction 51 is from top to bottom of the drawing. 21 to 24, the first direction is denoted by the same reference numeral 51 as the scanning direction. The second direction is from right to left or left to right in the drawing. In the following, the second direction will be referred to as direction 54 from left to right in the drawing.

In the channel 551B, the first direction extending portions and the second direction extending portions are alternately connected. Specifically, the first direction extending portion 553A, the second direction extending portion 554A, the first direction extending portion 553B, the second direction extending portion 554B, and the first direction extending portion 553C are arranged in this order. are concatenated.

At least one of both ends of each of the second direction extending portions is connected to the first direction end of the first direction extending portion along the first direction. Specifically, the second direction extending portion 554A is connected to the first direction extending portions 553A and 553B at both ends thereof.

The left end and right end of the second direction extending portion 554A are connected to the lower end portions of the first direction extending portions 553A and 553B in FIG. 21, respectively. Further, the second direction extending portion 554A extends along the first direction 51 of the first direction extending portions 553A and 553B, that is, the right side and the first direction extending portion of the first direction extending portion 553A in FIG. It is connected to the left side of the existing portion 553B.

The second direction extending portion 554B is connected to the first direction extending portions 553B and 553C at both ends thereof. The left end and right end of the second direction extending portion 554B are connected to the upper end portions of the first direction extending portions 553B and 553C, respectively. Further, the second direction extension portion 554B is connected to the right side of the first direction extension portion 553B and the left side of the first direction extension portion 553C.

In each of the second direction extensions 554A and 554B, a straight imaginary line can be defined extending through the center in the second direction 54 from end to end. A position P1 in the first direction 51 is the position of the virtual line VLA of the second direction extending portion 554A. A virtual line VLA of the second direction extending portion 554A has a length LHA. A position P2 in the first direction 51 is the position of the virtual line VLB of the second direction extending portion 554B. A virtual line VLB of the second direction extending portion 554B has a length LHB.

At the position of the phantom line of the second direction extending portion in the first direction, the sum TL of the product of the number of the first direction extending portion in the second direction and its channel width W and the length LH* of the phantom line is It is the same value at the position of the virtual line. Note that the asterisk * in LH* is a so-called wild card and indicates nothing or one or more character strings.

At the position of the phantom line of the second-direction-extending portions in the first direction, the product of the number of the first-direction-extending portions in the second direction and the channel width is the sum of the channel widths of the first-direction-extending portions. means. The channel width means the dimension of the channel portion along the second direction, and is the same as the so-called channel width (width in the direction perpendicular to the first direction) as the current path of the TFT. In addition, it is preferable that the so-called channel width as a current path of the TFT is constant between the portion extending in the first direction and the portion extending in the second direction. Specifically, there are two first-direction extending portions 553A and 553B at the position P1 of the virtual line VLA of the second-direction extending portion 554A. Also, the length of the virtual line VLA is LHA. Therefore, the length sum TL is 2W+LHA.

Further, two first-direction extending portions 553B and 553C are present at the position P2 of the virtual line VLB of the second-direction extending portion 554B. Also, the length of the virtual line VLB is LHB. Therefore, the length sum TL is 2W+LHB. Here, length LHA and length LHB are equal. That is, the length sum TL is the same value at the positions P1 and P2.

At an arbitrary position in the first direction where the straight imaginary line extending in the second direction does not overlap the second direction extending portion, the product of the number of first direction extending portions where the imaginary line overlaps with the channel width W is become constant. For example, at a position P3 in the first direction 51, there is no second direction extension. First direction extending portions 553A, 553B, and 553C are present at this position P3. Therefore, the product of the number of first-direction extending portions and the channel width W is 3W. In the example of FIG. 21, the values of LHA, LHB and W are identical. That is, the sum TL of the lengths is the same value of 3W at any of the positions P1, P2, and P3.

Channel ends 556 and 557 defining channel length L are located inside upper and lower ends of channel 551B defining channel size LB2 in the first direction. More specifically, the position of the channel end 556 in the first direction 51 matches the position of the lower end of the second direction extending portion 554B. Also, the position of the channel end 557 in the first direction 51 coincides with the position of the upper end of the second direction extending portion 554A. The first direction extending portions 553A and 553C have the same length in the first direction. The length of the first direction extending portion 553B is longer than the length of the first direction extending portions 553A and 553C by the width W of the channel.

FIG. 22 shows examples of other channel shapes. Channel 551C has a constant channel width W in the straight portion along the current path. A channel length L is defined between channel ends 566 and 567 along the central portion of the current path. Note that the central portion of the current path also includes the center of the current path and a constant width from the center. The channel 551C has first direction extending portions 563A, 563B and 563C extending in a first direction 51 along the scanning direction 51 and second direction extending portions 564A and 564B extending in a second direction 54 perpendicular to the scanning direction 51. It consists of

All corners of channel 561B described with reference to FIG. 21 are right angles. On the other hand, the channel 561C has curved portions (R) at the corners in plan view. Specifically, the corners having the radius R are the lower left corner of the first direction extension portion 563A, the lower right and upper left corners of the first direction extension portion 563B, and the upper right corner of the first direction extension portion 563C. outside R, respectively. Also, the upper left and upper right of the second direction extending portion 564A and the lower left and lower right of the second direction extending portion 564B are the inner R, respectively.

Therefore, channel 551C does not have a perfectly constant sum of length (or area) with respect to position in scan direction 51 . However, similar to the channel 551B, by having the following configuration, the difference in the ratio of regions with different characteristics in the channel is reduced, and the sum of the lengths (or the area) with respect to the position in the scanning direction 51 is substantially can be regarded as fixed.

In channel 551C, in the order of first direction extension 563A, second direction extension 564A, first direction extension 563B, second direction extension 564B, and first direction extension 563C, these are Concatenated.

The second direction extending portion 564A is connected to the first direction extending portions 563A and 563B at both ends thereof. The left end and right end of the second direction extension portion 564A are connected to the lower end portions of the first direction extension portions 563A and 563B, respectively. Further, the second direction extending portion 564A is located on the side of the first direction extending portions 563A and 563B along the first direction 51, that is, the right side of the first direction extending portion 563A and the first direction extending portion 563B. connected to the left side of the

The second direction extending portion 564B is connected to the first direction extending portions 563B and 563C at both ends thereof. The left end and right end of the second direction extending portion 564B are connected to the upper end portions of the first direction extending portions 563B and 563C, respectively. Further, the second direction extension portion 564B is connected to the right side of the first direction extension portion 563B and the left side of the first direction extension portion 563C.

In each of the second direction extensions 564A and 564B, a straight imaginary line can be defined that extends in the second direction 54 from end to end. A position P1 in the first direction 51 is the position of the virtual line VLA of the second direction extending portion 564A. A virtual line VLA of the second direction extending portion 564A has a length LHA. A position P2 in the first direction 51 is the position of the virtual line VLB of the second direction extending portion 564B. A virtual line VLB of the second direction extending portion 564B has a length LHB.

At the position P1 of the virtual line VLA of the second direction extending portion 564A, there are two first direction extending portions 563A and 563B. Also, the length of the virtual line VLA is LHA. Therefore, the length sum TL is 2W+LHA. Also, two first-direction extending portions 563B and 563C are present at the position P2 of the virtual line VLB of the second-direction extending portion 564B. Also, the length of the virtual line VLB is LHB. Therefore, the length sum TL is 2W+LHB. Here, length LHA and length LHB are equal. That is, the length sum TL is the same value at the positions P1 and P2.

At a position P3 in the first direction 51, there is no second direction extension. First direction extending portions 563A, 563B, and 563C are present at this position P3. Therefore, the product of the number of first-direction extending portions and the channel width thereof is 3W. The values of LHA, LHB and W are identical. That is, the sum TL of the lengths is the same value of 3W at any of the positions P1, P2, and P3. Even at other positions in the first direction where the straight imaginary lines extending in the second direction do not overlap the second direction extending portions, the product of the number of the first direction extending portions where the imaginary lines overlap and the channel width is 3W.

Channel ends 566 and 567 defining channel length L are located inside upper and lower ends of channel 551C defining channel size LB3 in the first direction. More specifically, the position of the channel end 566 in the first direction 51 matches the position of the lower end of the straight portion of the second direction extending portion 564B. The position of the lower end of the straight portion of the second directionally extending portion 564B defines the channel width W of the second directionally extending portion 564B.

Also, the position of the channel end 567 in the first direction 51 coincides with the position of the upper end of the straight portion of the second direction extending portion 564A. The position of the upper end of the straight portion of the second directionally extending portion 564A defines the channel width W of the second directionally extending portion 564A. The first direction extending portions 563A and 563C have the same length in the first direction. The length of the first directionally extending portion 563B is longer than the first directionally extending portions 563A and 563C by the channel width W. As shown in FIG.

FIG. 23 shows the relationship between a channel 551C having curved corners (R) in plan view and a channel 551B having all corners at right angles. FIG. 23 shows channel 551C in solid lines and channel 551B in dashed lines and shows them superimposed. In FIG. 23, channel width W and channel length L are common.

As can be understood from FIG. 23, the shape obtained by assuming a virtual end surface obtained by linearly extending the end surface (edge) defining the channel width W of the channel 551C matches the shape of the channel 551B. Specifically, the end surfaces 571 and 572 extending along the first direction 51 extend downward. The end faces 573, 574 and 577, 578 extending along the second direction 54 extend to both left and right sides. The end surfaces 575 and 576 extending along the first direction 51 are extended to both upper and lower sides. End faces 579 and 580 extending along the first direction 51 are extended upward.

The shape surrounded by the virtual end surfaces formed in this way matches the channel shape of the channel 551B. That is, the virtual shape has a completely constant sum of lengths (or area) with respect to the position in the scanning direction (first direction) 51 . That is, in the virtual shape, the areas of the portions divided in the scanning direction (first direction) 51 are completely uniform. A channel 551C having such a shape can effectively reduce the difference in the percentage of regions with different properties within the channel.

FIG. 24 shows examples of other channel shapes. Channel 551D includes more first and second direction extensions than channels 551B and 551C described above. Like the channel 551B, the channel 551D has right-angled corners and a completely constant sum of lengths (or area) with respect to the position in the scanning direction (first direction) 51 .

Channel 551D has a constant channel width W. FIG. A channel length L is defined between channel ends 586 and 587 . The channel 551D is composed of first direction extending portions 583A to 583D extending in a first direction 51 along the scanning direction 51 and second direction extending portions 584A to 584E extending in a second direction 54 perpendicular to the scanning direction 51. It is configured.

In channel 551D, second direction extension 584A, first direction extension 583A, second direction extension 584B, first direction extension 583B, second direction extension 584C, first direction extension 583C, second direction extending portion 584D, first direction extending portion 583D, and second direction extending portion 584E are connected in this order.

The second direction extending portion 584A is connected to the first direction extending portion only at one end. Specifically, the right end of the second direction extension portion 584A is connected to the lower end portion of the first direction extension portion 583A. Further, the second direction extending portion 584A is connected to the side of the first direction extending portion 583A along the first direction 51, that is, the left side of the first direction extending portion 583A.

The second direction extending portion 584B is connected to the first direction extending portions 583A and 583B at both ends thereof. The left end and right end of the second direction extending portion 584B are connected to the upper end portions of the first direction extending portions 583A and 583B, respectively. Further, the second direction extension portion 584B is connected to the right side of the first direction extension portion 583A and the left side of the first direction extension portion 583B.

The second direction extending portion 584C is connected to the first direction extending portions 583B and 583C at both ends thereof. The left end and right end of the second direction extending portion 584C are connected to the lower end portions of the first direction extending portions 583B and 583C, respectively. Further, the second direction extension portion 584C is connected to the right side of the first direction extension portion 583B and the left side of the first direction extension portion 583C.

The second direction extending portion 584D is connected to the first direction extending portions 583C and 583D at both ends thereof. The left end and right end of the second direction extending portion 584D are connected to the upper end portions of the first direction extending portions 583C and 583D, respectively. Further, the second direction extension portion 584D is connected to the right side of the first direction extension portion 583C and the left side of the first direction extension portion 583D.

The second direction extending portion 584E is connected to the first direction extending portion only at one end. Specifically, the left end of the second direction extension portion 584E is connected to the lower end portion of the first direction extension portion 583D. Further, the second direction extending portion 584E is connected to the side of the first direction extending portion 583D along the first direction 51, that is, the right side of the first direction extending portion 583D.

A straight imaginary line extending from end to end in the second direction 54 can be defined in each of the second direction extending portions 584A to 584E. A position P1 in the first direction 51 is the position of the virtual line VLA of the second direction extending portion 584A. A virtual line VLA of the second direction extending portion 584A has a length LHA.

A position P2 in the first direction 51 is the position of the virtual line VLB of the second direction extending portion 584B. A virtual line VLB of the second direction extending portion 584B has a length LHB. A position P3 in the first direction 51 is the position of the virtual line VLC of the second direction extending portion 584C. A virtual line VLC of the second direction extending portion 584C has a length LHC. A position P4 in the first direction 51 is the position of the virtual line VLD of the second direction extending portion 584D. A virtual line VLD of the second direction extending portion 584D has a length LHD. The position of the virtual line VLE of the second direction extending portion 584E is the same as the position P3 of the virtual line VLC. A virtual line VLE of the second direction extending portion 584E has a length LHE.

Four first-direction extending portions 583A to 583D are present at the position P1 of the virtual line VLA of the second-direction extending portion 584A. Also, the length of the virtual line VLA is LHA. Therefore, the length sum TL is 4W+LHA. Four first-direction extending portions 583A to 583D are present at the position P2 of the virtual line VLB of the second-direction extending portion 584B. Also, the length of the virtual line VLB is LHB. Therefore, the length sum TL is 4W+LHB.

At position P3, there are two second direction extensions 584C and 584E and three first direction extensions 583B, 583C and 583D. The lengths of virtual lines VLC and VLE of the second direction extending portions 584C and 584E are LHC and LHE, respectively. Therefore, the length sum TL is 3W+LHC+LHE. There are two first direction extensions 583C and 583D at the position P4 of the virtual line VLD of the second direction extension 584D. Also, the length of the virtual line VLD is LHD. Therefore, the sum of lengths TL is 2W+LHD.

In channel 551D of FIG. 24, lengths LHA, LHB, LHC and LHE are equal to channel width W; Also, the length LHD is three times the channel width W. FIG. Therefore, the sum of lengths TL at all positions P1 to P4 is 5W, which is the same. Note that the virtual line extending in the second direction 54 overlaps the second direction extending portion of the channel 551</b>D at any position in the first direction 51 . That is, when the channel 551D is viewed in the second direction 54, the second direction extending portion exists at any position in the first direction 51. FIG.

Referring to FIG. 20, channel size LB2 in scanning direction 51 of channel 551B is an integer multiple of scanning pitch P _ELA of pulsed laser beam 50 . With this configuration, even if the channel 551B exists at any phase position in the scanning direction 51, the same channel characteristics can be exhibited.

As described above, channel 551B has a constant length sum TL with respect to position in scan direction 51 . Therefore, if channel size LB2 in scan direction 51 of channel _551B is an integer multiple of scan pitch PELA, the area of all phases that channel 551B contains is the same. Therefore, the ratio of regions with different characteristics is the same among all the channels 551B. Therefore, if the channel size LB2 is an integral multiple of the scan pitch PELA, the channel characteristics can be kept constant regardless of the position of the channel _551B .

A similar discussion can be applied to channel 551D having a curved shape as described with reference to FIG. Since the channel 551C described with reference to FIG. 22 has curved portions (R) at the corners in plan view, the sum of the lengths (area) at the positions in the scanning direction 51 is perfect as described above. is not equal to However, if the channel size LB4 in the scanning direction 51 is an integer multiple of the scanning pitch PELA, the channel _551D having the above configuration can exhibit similar channel characteristics regardless of the arrangement position.

In another configuration example, the channel 551B, 551C, or 551D having the curved shape has a channel size LB that is an integral multiple of the scan pitch P _ELA , and is arranged so that the phase of the channel position with respect to the ELA irradiation period matches. do. This makes it possible to make the characteristics between channels more uniform.

In another configuration example, the channel 551B, 551C, or 551D having the curved shape has a channel size LB that is different from an integer multiple of the scan pitch PELA, and the phase of the channel position with respect to the irradiation period of _ELA matches. Deploy.

In Embodiment 2, the channel positions of the driving TFTs of the pixels of the same color are in the same phase in the ELA irradiation cycle. Therefore, the channel characteristics of channels with arbitrary curved shapes can be kept constant regardless of the placement position. However, actual channel positions may have fluctuations (deviations) with respect to design positions. As described above, if the channels have a curved shape with a small difference in the proportion of regions having different properties, even if the channel positions are slightly shifted from the design position, the change in properties between the channels can be small. Such curved channels may have channel sizes that differ from integer multiples of the scan pitch _PELA .

Here, as explained with reference to FIG. 20, the reason why the characteristics of a transistor having a curved channel can be described as a synthesis of individual characteristics corresponding to the phase of the channel element regardless of the direction of the current is as follows. explain.

An experiment was conducted by densely arranging test transistors each having a channel width and a channel length of W. FIG. This W corresponds to W described in FIG. There are two types of test transistors: parallel type test transistors (hereinafter abbreviated as parallel type) and vertical type test transistors (hereinafter abbreviated as vertical type). The parallel type is a transistor in which the direction of the channel length of the transistor, that is, the direction of current flow, is arranged parallel to the scanning direction. On the other hand, the vertical type is a transistor in which the direction of the channel length of the transistor, that is, the direction of current flow, is arranged perpendicular to the scanning direction.

A parallel type and a vertical type are set as one set, for example, and a plurality of sets are arranged on the substrate. In one set, the parallel mold and the vertical mold are arranged in close proximity. In each of the plurality of sets, the parallel type and the vertical type are arranged at slightly different positions, and are arranged at different phases in the irradiation cycle of the pulsed laser light.

The characteristics of the test transistors arranged in this way were measured, and the characteristics measured corresponding to the phases in which the transistors were arranged were arranged, and the parallel type and the vertical type were compared. From this comparison, it was confirmed that the characteristics themselves were equivalent and that the behavior of the characteristics changing with respect to the phase was also equivalent. That is, in a transistor having a channel width equivalent to that of a transistor forming a pixel circuit, each channel segment (in other words, channel segment) obtained by dividing the channel length by the channel width has its current direction in the scanning direction of the ELA. It can be said that they have similar (in other words, substantially equivalent) characteristics whether they are parallel to or perpendicular to them.

Therefore, as described with reference to FIG. 20, the characteristics of a transistor having a curved channel can be described as a synthesis of individual characteristics corresponding to the phase of the channel element, regardless of the direction of the current. of.

21 to 24, the example in which the angle between the first direction of the first direction extending portion and the scanning direction is 0 degrees, that is, the first direction and the scanning direction are parallel has been described. However, the absolute value of the angle between the first direction and the scanning direction may exceed 0 degrees. 25A to 25C show examples of channel shapes when the angles between the first direction and the scanning direction are 3 degrees, 10 degrees, and 20 degrees, respectively.

In FIG. 25A, the absolute value of the angle between the first direction d11 of each first direction extension (593A, 593B, 593C) of the channel 591B and the scan direction 51 is 3 degrees. A two-dot chain line 51 a is a line parallel to the scanning direction 51 . The first direction d11 is indicated by a dotted line in FIG. 25A and extends along the long side of each first direction extending portion.

In the channel 591B, the first direction extending portion and the second direction extending portion are alternately connected. Specifically, the first direction extension portion 593A, the second direction extension portion 594A, the first direction extension portion 593B, the second direction extension portion 594B, and the first direction extension portion 593C are connected in this order. ing. Since this connection relationship has been explained in FIG. 21, the explanation of this connection relationship is omitted.

In FIG. 25B, the absolute value of the angle between the first direction d111 of each first direction extension (603A, 603B, 603C) of the channel 601B and the scanning direction 51 is 10 degrees. The first direction d111 is indicated by a dotted line in FIG. 25B and extends along the long side of each first direction extending portion. In the channel 601B, the first-direction-extending portions and the second-direction-extending portions are alternately connected. Specifically, the first direction extending portion 603A, the second direction extending portion 604A, the first direction extending portion 603B, the second direction extending portion 604B, and the first direction extending portion 603C are connected in this order. ing. Since this connection relationship has been explained in FIG. 21, the explanation of this connection relationship is omitted.

In FIG. 25C, the absolute value of the angle between the first direction d1111 of each first direction extension (613A, 613B, 613C) of the channel 611B and the scan direction 51 is 20 degrees. The first direction d1111 is indicated by a dotted line in FIG. 25B and extends along the long side of each first direction extending portion. In the channel 611B, the first-direction-extending portions and the second-direction-extending portions are alternately connected. Specifically, the first direction extending portion 613A, the second direction extending portion 614A, the first direction extending portion 613B, the second direction extending portion 614B, and the first direction extending portion 613C are connected in this order. ing. Since this connection relationship has been explained in FIG. 21, the explanation of this connection relationship is omitted.

Summarizing the angle between the first direction and the scanning direction, the absolute value of the angle between the first direction and the scanning direction is a predetermined angle. The predetermined angle is preferably 0 degrees. The predetermined angle may exceed 0 degrees, and may be set to 20 degrees or less, for example, as long as the effects described in the embodiments of the present disclosure can be achieved.

The dimension (size) of the channel along the first direction and the dimension of the channel along the scanning direction satisfy the following formula.
D2=D1×COS θ

where D2 is the dimension of the channel along the scanning direction, D1 is the dimension of the channel along the first direction, and θ is the predetermined angle. The dimension of the channel along the scanning direction is an integral multiple of the scanning pitch of the pulsed laser beam.

Note that even if the absolute value of the angle exceeds 0 degrees, the number of first-direction-extending portions in the second direction at the position of the virtual line of the second-direction-extending portions in the first direction and the channel width means the sum of the channel widths of the respective first-direction extending portions. The channel width of the first direction extending portion is the same as the dimension of the channel portion along the second direction, but the so-called channel width (the width in the direction perpendicular to the first direction) of the TFT current path is is not necessarily the same as

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above-described embodiments within the scope of the present disclosure. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

10 OLED display device, 40 polysilicon film, 41-43 region, 45 channel, 47 amorphous silicon film, 49 substrate, 50 pulse laser light, 51 scan direction, 52 scan pitch, 53 minor axis width, 56 irradiation position, 100 TFT Substrate 105 Data line 106 Scanning line 107 Emission control line 108 Power supply line 109 Reset control line 110 Reference voltage supply line 114 Cathode electrode formation area 125 Display area 131 Scan driver 132 Emission driver 133 Protection circuit, 136 demultiplexer, 140, 140A-140D, 240A, 240B, 340A-340N pixel, 151 insulating substrate, 152 first insulating film, 155 channel, 156 gate insulating film, 157 gate electrode, 158 interlayer insulating film, 159 source Electrode 160 Drain electrode 161 Planarizing film 162 Anode electrode 163 Pixel defining layer 164 Spacer 165 Organic light-emitting film 166 Cathode electrode 167 Opening 168, 169 Source/drain region 170, 171 Contact hole 200 sealing substrate, 300 junction, T1 drive TFT, T2 selection transistor, T3 emission transistor, T4 reset transistor, P _ELA scan pitch, P _PIX pixel pitch

Claims (7)

a substrate;
a plurality of light emitting elements on the substrate;
a plurality of pixel circuits each controlling the plurality of light emitting elements on the substrate;
including
each of the plurality of pixel circuits includes a thin film transistor;
each of the thin film transistors includes a channel;
The channel has a characteristic variation pattern arranged at a constant pitch in the vertical direction,
The channel comprises a first direction extension portion extending along a first direction and a second direction extension portion extending along a second direction, wherein the absolute angle between the first direction and the longitudinal direction is defined by the channel. the value has a predetermined angle, the second direction is perpendicular to the longitudinal direction, the first direction extensions and the second direction extensions are alternately connected;
At least one of both ends of each of the second direction extending portions is connected to a side along the first direction of the end of the first direction extending portion in the first direction,
A linear first imaginary line extending from end to end in the second direction is defined in each of the second direction extending portions,
At the position of the first imaginary line in the first direction, the product of the number of the first direction extending portions in the second direction and the channel width and the sum of the length of the first imaginary line are the same value. can be,
The number and channels of the linear second phantom line extending in the second direction overlapping the second phantom line at a position in the first direction where the second phantom line does not overlap the second direction extending portion the product of the width is the same value, and
the dimension of the channel along the longitudinal direction is an integral multiple of the pitch of the characteristic variation pattern ,
display device. The display device according to claim 1,
The channel is
a first first-direction extending portion;
a first second-direction extending portion connected to the first first-direction extending portion;
a second first-direction extending portion connected to the first second-direction extending portion;
a second second-direction extending portion connected to the second first-direction extending portion;
a third first direction extending portion connected to the second second direction extending portion;
display device. The display device according to claim 1,
The sum of the lengths of the portions where the third imaginary line extending in the second direction overlaps the channel is the same value in the first direction,
display device. The display device according to claim 1,
A portion of the first direction extending portion connected to the second direction extending portion includes a curved portion,
display device. The display device according to claim 4,
The position of the third virtual line extending in the second direction is a position other than the curved portion,
The sum of the lengths of the portions where the third imaginary line extending in the second direction overlaps the channel is the same value in the first direction,
display device. The display device according to claim 1,
The plurality of pixel circuits are arranged at different positions in the vertical direction,
At least channels of the same color among the channels are arranged at positions of the same phase in the characteristic variation pattern in the vertical direction,
display device. The display device according to claim 1,
the dimension of the channel along the first direction and the dimension of the channel along the longitudinal direction satisfy
D2=D1×COS θ
D2 is the dimension of the channel along the longitudinal direction, D1 is the dimension of the channel along the first direction, and θ is the predetermined angle,
display device.

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