JP2011119525A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which an insulating member of high quality can be formed at a periphery of a semiconductor element by using a coating method and a depositing method. <P>SOLUTION: The method of manufacturing the semiconductor device 100 includes the processes of: additionally forming an insulating film 10 made of an Si-based insulating material on a semiconductor substrate 2; forming a catalyst metal film 11 on the insulating film 10; subjecting the insulating film 10 to oxidation processing using the catalyst metal film 11 as a catalyst; forming a gate insulating film 4 by processing the insulating film 10 having been subjected to the oxidation processing; and forming an MOSFET 1 including the gate insulating film 4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a coating method and a deposition method are known as methods for forming a silicon oxide film. Compared with the thermal oxidation method in which the silicon oxide film is formed by oxidizing the surface of the silicon member, the coating method and the deposition method do not require the underlying material to be silicon, and the silicon oxide film thickness can be freely set. It has the advantage that it can be set.

  On the other hand, a silicon oxide film formed by a coating method or a deposition method is more likely to generate fixed charges due to impurities (nitrogen, carbon, etc.) contained in the raw material than those formed by a thermal oxidation method. Problems such as a high interface state at the interface between the substrate and the base member, damage when plasma nitriding is performed, and damage when a metal film is formed on the silicon oxide film by plasma sputtering. There is. In order to solve such problems and obtain a high-quality silicon oxide film, a method of performing an oxidation treatment under high temperature conditions after forming a silicon oxide film by a coating method or a deposition method has been conventionally used. However, when the oxidation treatment is performed under a high temperature condition, there is a possibility that impurities in the silicon oxide film diffuse to the outside and deteriorate the device characteristics.

  As a conventional technique, a technique is known in which an insulating film and a metal film are stacked on a semiconductor film, and then a part of the semiconductor film is oxidized by heat treatment to form an insulating oxide film by low-temperature heat treatment ( For example, see Patent Document 1).

Japanese Patent No. 3786569

  An object of the present invention is to provide a semiconductor device manufacturing method capable of forming a high-quality insulating member by using a coating method or a deposition method.

  One aspect of the present invention includes a step of additionally forming an insulating film made of a Si-based insulating material on a base member, a step of forming a catalytic metal film on the insulating film, and using the catalytic metal film as a catalyst. Using the step of oxidizing the insulating film, forming the insulating member by processing the insulating film subjected to the oxidizing treatment, and a semiconductor element including the insulating member or adjacent to the insulating member And a process for forming the semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can form a high quality insulating member using the apply | coating method and the deposition method can be provided.

1 is a vertical sectional view of a semiconductor device according to a first embodiment of the present invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (E)-(g) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure showing the relationship between a gate applied voltage and NBTI lifetime. The vertical sectional view of the semiconductor device concerning a 2nd embodiment of the present invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a vertical sectional view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 has a MOSFET 1 separated from other elements by an element isolation insulating film 3 on a semiconductor substrate 2.

  MOSFET 1 includes a gate electrode 5 formed on a semiconductor substrate 2 via a gate insulating film 4, an offset spacer 6 formed on a side surface of the gate electrode 5, and a sidewall formed on a side surface of the offset spacer 6. It has a spacer 7 and source / drain regions 8 formed on both sides of the gate electrode 5 in the semiconductor substrate 2. Although not shown, a well may be formed in a region under the MOSFET 1 in the semiconductor substrate 2.

  The semiconductor substrate 2 is made of a Si-based crystal such as a Si crystal.

The element isolation insulating film 3 is made of an insulating material such as SiO ₂ and has an STI (Shallow Trench Isolation) structure.

The gate insulating film 4 is made of an insulating material containing Si and O (oxygen) such as SiO ₂ and SiON.

  The gate electrode 5 is made of, for example, a Si-based polycrystal such as polycrystalline Si containing a conductive impurity, or a metal material. Further, a metal silicide layer may be formed on or over the gate electrode 5.

The offset spacer 6 and the sidewall spacer 7 are made of an insulating material such as SiO ₂ or SiN. Further, the sidewall spacer 7 may have a two-layer structure made of a plurality of kinds of insulating materials such as SiN, SiO ₂ , TEOS (Tetraethoxysilane), or a structure having three or more layers.

The source / drain regions 8 are formed by injecting conductive impurities into the semiconductor substrate 2. When the n-type source / drain region 8 is formed, n-type impurities such as As and P are used. Further, when the p-type source / drain region 8 is formed, an n-type impurity such as B or BF ₂ is used. A metal silicide layer may be formed on the source / drain region 8.

  Below, an example of the manufacturing method of the semiconductor device 100 which concerns on this Embodiment is shown.

(Manufacture of semiconductor devices)
2A (a) to 2 (d) and FIGS. 2B (e) to (g) are cross-sectional views showing manufacturing steps of the semiconductor device 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 2A (a), an element isolation insulating film 3 is formed on a semiconductor substrate 2 to partition an element region for forming the MOSFET 1. Although not shown, a channel region is formed in the semiconductor substrate 2 after the element isolation insulating film 3 is formed.

Next, as shown in FIG. 2A (b), an insulating film 10 made of a Si-based insulating material such as SiO ₂ , SiN, or SiON is formed on the semiconductor substrate 2. The insulating film 10 is additionally formed on the semiconductor substrate 2 by a deposition method such as a CVD (Chemical Vapor Deposition) method or a coating method. Since the insulating film 10 is a film additionally formed on the semiconductor substrate 2, it is not a film formed by a method of oxidizing the surface of the Si substrate using a thermal oxidation method.

Further, after forming the SiO ₂ film by a deposition method or a coating method, the insulating film 10 made of SiON may be formed by nitriding the SiO ₂ film.

  Next, as shown in FIG. 2A (c), a catalytic metal film 11 is formed on the insulating film 10 by a PVD (Physical Vapor Deposition) method or the like. The catalytic metal film 11 is made of a metal such as Hf, Pd, Pt, or Mn having a catalytic function that promotes the oxidation reaction of the material in contact.

The thickness of the catalytic metal film 11 is preferably 0.03 nm or more and 3 nm or less, and more preferably 0.5 nm or less. The surface density of the catalytic metal film 11 is preferably 3 × 10 ¹⁴ atoms / cm ² or less. Further, instead of the catalyst metal film 11, the above-described catalyst metal formed in an island shape on the insulating film 10 may be used.

  If the thickness or surface density of the catalytic metal film 11 is too large, oxygen may not be sufficiently transmitted when the insulating film 10 is oxidized in a later step, and the insulating film 10 may not be sufficiently oxidized. There is. Moreover, when the thickness or surface density of the medium metal film 11 is too small, the effect as a catalyst may be insufficient.

More specifically, for example, when the thickness of the catalytic metal film 11 is about 0.05 nm or more and 0.5 nm or less, the surface density is 3 × 10 ¹³ atoms / cm ² or more and 3 × 10 ¹⁵ atoms / cm ^2. It is preferable that it is cm ² or less.

  Next, as shown in FIG. 2A (d), the insulating film 10 is oxidized (post-oxidized) by an RTO (Rapid Thermal Oxidation) method or the like. At this time, since the oxidation reaction of the insulating film 10 is promoted by the catalytic metal film 11, the insulating film 10 can be oxidized at a lower temperature (for example, 500 ° C. or lower) than when the catalytic metal film 11 is not used.

  Next, as shown in FIG. 2B (e), after removing the catalytic metal film 11 by wet etching or the like, a gate material film 12 made of polycrystalline Si or the like is formed on the insulating film 10 by a CVD method or the like.

  Next, as shown in FIG. 2B (f), the gate material film 12 and the insulating film 10 are patterned by a combination of photolithography and RIE (Reactive Ion Etching), etc. Form.

  Next, as shown in FIG. 2B (g), offset spacers 6, sidewall spacers 7, and source / drain regions 8 are formed. An example of a specific method for forming these members will be described below.

First, a SiO ₂ film or a SiON film is formed on the entire surface of the semiconductor substrate 2 by the CVD method, and this is processed by the RIE method to form the offset spacer 6 on the side surface of the gate electrode 5. Next, a SiO ₂ film or a SiON film is formed on the entire surface of the semiconductor substrate 2 by the CVD method, and this is processed by the RIE method to form side wall spacers (not shown) on the side surfaces of the offset spacers 6.

  Next, by using the gate electrode 5, the offset spacer 6 and the side wall spacer as a mask, conductive impurities are implanted into the semiconductor substrate 2, and the implanted conductive impurities are activated by heat treatment, whereby the source / drain regions 8 are formed. A deep region is formed.

  Next, after removing the side wall spacer, a conductive impurity is implanted into the semiconductor substrate 2 using the gate electrode 5 and the offset spacer 6 as a mask. An extension region of the drain region 8 is formed.

Next, a SiO ₂ film or a SiON film is formed on the entire surface of the semiconductor substrate 2 by the CVD method, and this is processed by the RIE method to form the sidewall spacer 7 on the side surface of the offset spacer 6.

  Thereafter, a silicide layer may be formed on the gate electrode 5 and the source / drain regions 8 in a self-aligning manner.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the insulating film 10 containing Si and O formed by a deposition method, a coating method, or the like is subjected to an oxidation treatment, so that the gate insulating film is formed by impurities contained in the insulating film 10. 4 can solve problems such as a problem that a fixed charge is generated in 4 and the threshold voltage fluctuates, and a problem that the interface state at the interface between the gate insulating film 4 and the semiconductor substrate 2 becomes high.

  FIG. 3 is a diagram showing the relationship between the gate applied voltage and the NBTI (Negative Bias Temperature Instability) life. FIG. 3 shows that by performing post-oxidation treatment on the insulating film 10, the interface state is lowered, the quality of the gate insulating film 4 is improved, and the NBTI lifetime with respect to the gate applied voltage is increased. It also shows that when the catalytic metal film 11 is on the insulating film 10, the oxidation is promoted by the catalytic metal, the quality of the gate insulating film 4 is further improved, and the NBTI life is increased.

  In addition, when the insulating film 10 is oxidized, the insulating metal film 11 can be sufficiently oxidized under a low temperature condition by using the catalytic metal film 11 as a catalyst for the oxidation reaction. By oxidizing the insulating film 10 at a low temperature, it is possible to solve the problem that the impurities in the insulating film 10 are diffused to the substrate interface and the characteristics of the semiconductor device 100 are deteriorated.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment in that an element isolation insulating film is formed by an insulating film subjected to oxidation treatment. Note that the description of the same points as in the first embodiment will be omitted or simplified.

(Configuration of semiconductor device)
FIG. 4 is a vertical sectional view of a semiconductor device 200 according to the second embodiment of the present invention. MOSFET 1 included in semiconductor device 200 is the same as that included in the first embodiment.

The element isolation insulating film 20 is made of an insulating material containing Si and O (oxygen) such as SiO ₂ and SiON, and has an STI structure.

  Below, an example of the manufacturing method of the semiconductor device 200 concerning this Embodiment is shown.

(Manufacture of semiconductor devices)
FIGS. 5A to 5D are cross-sectional views illustrating the manufacturing steps of the semiconductor device 200 according to the second embodiment of the present invention.

  First, as shown in FIG. 5A, a groove 21 is formed in the semiconductor substrate 2 by a combination of photolithography and RIE.

  Next, as shown in FIG. 5B, an insulating film 22 is additionally formed in the groove 21 by a deposition method such as a CVD method or a coating method, and a catalytic metal film 23 is formed thereon by a PVD method or the like. Form.

Here, the insulating film 22 is made of a Si-based insulating material such as SiO ₂ , SiN, or SiON. The catalytic metal film 23 is made of the same material as the catalytic metal film 11 in the first embodiment.

  Next, as shown in FIG. 5C, the insulating film 22 is oxidized by an RTO method or the like. At this time, since the oxidation reaction of the insulating film 22 is promoted by the catalytic metal film 23, the insulating film 22 is oxidized at a lower temperature (for example, 500 ° C. or lower) than when the catalytic metal film 23 is not used, thereby improving the film quality. be able to.

  Next, as shown in FIG. 2B (e), the catalytic metal film 23 and the insulating film 22 outside the groove 21 are removed by wet etching or the like to form an element isolation insulating film 20.

  Thereafter, the well, the gate insulating film 4, the gate electrode 5, the offset spacer 6, the sidewall spacer 7, and the source / drain region 8 are formed by the same process as in the first embodiment, and the semiconductor device 200 is obtained.

(Effect of the second embodiment)
According to the first embodiment of the present invention, when the insulating film 22 is oxidized, the insulating metal film 23 is sufficiently oxidized under a low temperature condition by using the catalytic metal film 23 as a catalyst for the oxidation reaction. be able to.

  Further, by oxidizing the insulating film 22 at a low temperature, it is possible to solve the problem that impurities in the insulating film 22 diffuse to the substrate interface and the characteristics of the semiconductor device 200 are deteriorated.

[Other Embodiments]
The present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the spirit of the invention. For example, another insulating member (included in or adjacent to the semiconductor element) around the semiconductor element such as a transistor can be formed using a method similar to that of the gate insulating film 4 or the element isolation insulating film 20.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

  100, 200 Semiconductor device, 1 MOSFET, 2 Semiconductor substrate, 4 Gate insulating film, 20 Element isolation insulating film, 10, 22 Insulating film, 11, 23 Catalytic metal film

Claims (5)

A step of additionally forming an insulating film made of a Si-based insulating material on the base member;
Forming a catalytic metal film on the insulating film;
Performing an oxidation treatment on the insulating film using the catalytic metal film as a catalyst;
Processing the insulating film subjected to the oxidation treatment to form an insulating member;
Forming a semiconductor element including or adjacent to the insulating member;
A method of manufacturing a semiconductor device including: The insulating film is formed by a coating method or a deposition method.
A method for manufacturing a semiconductor device according to claim 1. The oxidation treatment is performed under a temperature condition of 500 ° C. or lower.
A method for manufacturing a semiconductor device according to claim 1. The surface density of the catalytic metal film is 3 × 10 ¹³ atoms / cm ² or more and 3 × 10 ¹⁵ atoms / cm ² or less.
The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The semiconductor element is a transistor;
The insulating member is a gate insulating film of the transistor or an element isolation insulating film that separates the transistor from other elements.
The manufacturing method of the semiconductor device as described in any one of Claims 1-4.

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