JP2009004492A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of improving performance or the like of the semiconductor device by inhibiting a variation in thickness of a sidewall film of a gate electrode provided in the semiconductor device and improving flatness of a surface of the sidewall film. <P>SOLUTION: First heat treatment takes place on at least one gate structure 13 comprising an inter-electrode insulation film 4 between a floating gate electrode 3 containing impurities and a control gate electrode 10 and provided on a semiconductor substrate 1 via a tunnel insulation film 2. After impurities are implanted toward a front layer of the semiconductor substrate 1 having the gate structure 13 on which the first heat treatment takes place, a non-monocrystal silicon film 18 without impurities added is provided to cover the gate structure 13. After an insulation film 19 is further provided to cover the silicon film 18, second heat treatment takes place on the silicon film 18 and the gate structure 13 covered with the insulation film 19. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to form a sidewall film of a gate electrode that can improve the performance of the semiconductor memory device by suppressing variations in the thickness of the sidewall film of the gate electrode included in the semiconductor memory device. Regarding the method.

  A method for manufacturing a flash memory, which is a kind of semiconductor memory device as a semiconductor device, will be described below. In particular, a general method for forming a floating gate transistor included in a flash memory will be described (for example, see Patent Document 1).

  First, a tunnel oxide film is formed on the surface of the semiconductor silicon substrate. Subsequently, a first polycrystalline silicon film to which phosphorus (P) as an impurity is added is deposited on the tunnel oxide film. The first P-added polycrystalline silicon film becomes a floating gate electrode. Subsequently, an interelectrode insulating film is formed on the first P-added polycrystalline silicon film. Specifically, first, a first silicon nitride film to be a lowermost nitride film is deposited on the first P-added polycrystalline silicon film. Subsequently, a bottom oxide film serving as a lower oxide film is deposited on the first silicon nitride film. Subsequently, a second silicon nitride film to be an intermediate nitride film is deposited on the bottom oxide film. Subsequently, a top oxide film to be an upper oxide film is deposited on the second silicon nitride film. Subsequently, a third silicon nitride film which is the uppermost nitride film is deposited on the top oxide film. As a result, an interelectrode insulating film having a structure in which silicon nitride films and silicon oxide films are alternately stacked in five layers is formed on the first P-added polycrystalline silicon film. Each silicon nitride film and each silicon oxide film are formed by, for example, a CVD method.

  Next, second polycrystalline silicon in which phosphorus (P) as an impurity is added onto the third silicon nitride film, which is the uppermost layer of the interelectrode insulating film, in the same manner as the first P-added polycrystalline silicon film. Deposit film. This second P-added polycrystalline silicon film serves as a control gate electrode. Subsequently, a processing hard mask material made of a silicon nitride film is deposited on the second P-added polycrystalline silicon film. Subsequently, a laminated film from the processing hard mask material to the first P-added polycrystalline silicon film (floating gate polycrystalline silicon film) is processed by a normal photolithography process and a dry etching process to obtain a predetermined gate structure. To mold. Subsequently, in order to recover the damage given to the laminated film from the second P-added polycrystalline silicon film to the first P-added polycrystalline silicon film by this processing step, Heat treatment is performed under an atmosphere. As a result, a gate structure in which the interelectrode insulating film is sandwiched between the floating gate electrode and the control gate electrode is formed on the surface of the semiconductor silicon substrate via the tunnel oxide film.

  Next, a source / drain diffusion layer having an LDD (Lightly Doped Drain) structure is formed. Specifically, first, first ion implantation is performed with low energy toward the surface layer portion of the semiconductor silicon substrate on which the gate structure is formed. As a result, an extension region serving as a shallow junction in the source / drain diffusion layer is formed in the surface layer portion of the semiconductor silicon substrate with the gate structure sandwiched from both outer sides thereof. Subsequently, an oxide film is deposited on the side wall of the gate structure by a CVD method so as to cover a portion of the extension region adjacent to the gate structure. This sidewall oxide film serves as a spacer for forming an offset region for electrically isolating a contact region of a source / drain diffusion layer described later from the channel region. Subsequently, the sidewall oxide film is heat-treated in an oxidizing atmosphere to be densified.

  Thereafter, second ion implantation is performed with higher energy than the first ion implantation toward the surface layer portion of the semiconductor silicon substrate on which the gate structure having the densified sidewall oxide film is formed. As a result, a contact region serving as a deep junction in the source / drain diffusion layer is formed on the surface layer of the semiconductor silicon substrate with the gate electrode provided with the sidewall oxide film sandwiched from both outsides. The contact region is formed so as to be further shifted toward the both outer sides of the gate electrode by the thickness of the sidewall oxide film with respect to the extension region and reach a position deeper than the extension region. Therefore, the thickness of the sidewall oxide film becomes the size (width, length) of the offset region of the contact region with respect to the channel region. Through the steps so far, a flash memory storage transistor having a floating gate electrode is formed on the surface layer portion of the semiconductor silicon substrate.

When the source / drain diffusion layer having the LDD structure is formed by the process described above, the position of the contact region is determined according to the thickness of the sidewall oxide film of the gate structure. That is, in order to control the position of the source / drain diffusion layer having the LDD structure in the source / drain direction with high accuracy, the controllability of the thickness of the sidewall oxide film is an important point. However, in recent years, the demand for miniaturization of semiconductor devices has further increased, and it is very difficult to control the thickness of the sidewall oxide film to a desired thickness when forming the sidewall oxide film.
JP 2003-298050 A

  In the present invention, a method of manufacturing a semiconductor device capable of improving the performance of the semiconductor device by suppressing variations in the thickness of the sidewall film of the gate electrode provided in the semiconductor device and improving the flatness of the surface of the sidewall film. I will provide a.

  A method for manufacturing a semiconductor device according to one embodiment of the present invention includes an interelectrode insulating film sandwiched between a floating gate electrode containing an impurity and a control gate electrode, and is provided over a semiconductor substrate via a tunnel insulating film. The first heat treatment is performed on at least one gate structure, and impurities are implanted into the surface layer portion of the semiconductor substrate having the gate structure subjected to the first heat treatment, and then the gate is formed. An impurity-free non-single-crystal silicon film is provided to cover the structure, an insulating film is further provided to cover the non-single-crystal silicon film, and then the non-single-crystal silicon film and the gate structure covered with the insulating film The second heat treatment is performed on the substrate.

  In addition, a method of manufacturing a semiconductor device according to another aspect of the present invention includes an interelectrode insulating film sandwiched between a floating gate electrode containing an impurity and a control gate electrode, and is formed on a semiconductor substrate via a tunnel insulating film. A first insulating film is provided on a side surface of the floating gate electrode and the control gate electrode in at least one gate structure provided on the gate structure, and an impurity is formed on the side surface of the gate structure so as to cover the first insulating film. After adding an additive-free non-single-crystal silicon film and implanting impurities toward the surface layer portion of the semiconductor substrate having the gate structure provided with the non-single-crystal silicon film, the non-single-crystal silicon film and the gate A second insulating film is provided so as to cover the structure, and the non-single-crystal silicon film provided with the second insulating film and the gate structure are subjected to heat treatment.

  According to the method for manufacturing a semiconductor device according to the present invention, it is possible to suppress variations in the thickness of the sidewall film of the gate electrode provided in the semiconductor device and improve the flatness of the surface of the sidewall film. The performance of the apparatus can be improved.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

(First embodiment)
First, prior to describing the first embodiment according to the present invention, a brief description will be given of problems in the case where a floating gate type transistor is formed by the conventional formation method investigated by the present inventors. . According to the results of investigations by the present inventors, it has been found that when a floating gate type transistor is formed by a general forming method, the following two problems are likely to occur.

  The first problem relates to the controllability of the formation position of the source / drain diffusion layer. The P concentration in the P-added polycrystalline silicon film serving as the floating gate electrode and the control gate electrode varies depending on the ion implantation process. The sidewall oxide film provided on the side surface of the P-added polycrystalline silicon film has a film thickness that increases as the P concentration in the polycrystalline silicon film increases due to accelerated oxidation by P in the polycrystalline silicon film. It has P concentration dependency of increasing thickness. That is, the impurity concentration in the polycrystalline silicon film serving as the underlying layer of the sidewall oxide film affects the film thickness of the sidewall oxide film. Therefore, if the impurity concentration in the polycrystalline silicon film varies, the thickness of the sidewall oxide film also varies. As a result, when the impurity concentration varies in the polycrystalline silicon film, the controllability of the formation position of the source / drain diffusion layer is deteriorated. When the controllability of the formation position of the source / drain diffusion layer is deteriorated, the electrical characteristics and performance of the floating gate transistor are deteriorated. Eventually, the electrical characteristics and performance of the entire flash memory including such a floating gate type transistor are deteriorated.

  The second problem relates to threshold interference between transistors when a plurality of transistors are formed close to each other. In the heat treatment under the oxidizing atmosphere described above, an oxide film is easily formed on the P-doped polycrystalline silicon film serving as the floating gate electrode and the control gate electrode in the gate structure. It is difficult to form an oxide film on the interelectrode insulating film. For this reason, a step is likely to occur in the sidewall oxide film formed on the side surface of the gate structure. When a step is generated in the sidewall oxide film, voids are generated between the plurality of transistors when an oxide film serving as an interlayer insulating film is deposited on the semiconductor silicon substrate by the CVD method prior to the wiring formation step. Then, a depression starting from the void is generated in a subsequent process, and a processing stopper film such as a SiN film enters the inside of the depression. Then, the dielectric constant of the insulating film between the transistors increases, and the parasitic capacitance between the transistors increases. As a result, there arises a problem that threshold interference between the transistors becomes large. When the threshold interference between the transistors increases, the electrical characteristics and performance of the floating gate type transistor and the entire flash memory including the same deteriorate as in the case where the controllability of the formation position of the source / drain diffusion layer is deteriorated. To do.

  The present embodiment has been made to solve the problems described above. Hereinafter, a first embodiment according to the present invention will be described with reference to FIGS. In the present embodiment, a method for manufacturing a flash memory which is a kind of semiconductor memory device as a semiconductor device will be described. In particular, a method for forming a floating gate type transistor and a sidewall film of the flash memory will be mainly described.

First, as shown in FIG. 1A, a tunnel insulating film 2 made of, for example, a silicon oxide film (SiO ₂ film) is formed so as to cover the surface of a silicon substrate 1 as a semiconductor substrate. This tunnel insulating film 2 is also referred to as a tunnel oxide film. Subsequently, a first polycrystalline silicon film 3 is deposited on the tunnel oxide film 2, and phosphorus (P) as an impurity is added to the first polycrystalline silicon film 3 by an ion implantation method. The first P-added polycrystalline silicon film 3 is processed into a predetermined shape in a subsequent process to become a floating gate electrode (floating gate electrode).

Subsequently, an interelectrode insulating film 4 is formed on the first P-added polycrystalline silicon film 3. Here, the interelectrode insulating film 4 is formed using a laminated insulating film formed by laminating a plurality of insulating films having different film types. Specifically, first, a first silicon nitride film (SiN film) 5 serving as a first-layer (lowermost layer) interelectrode insulating film is deposited on the first P-added polycrystalline silicon film 3. Subsequently, a first silicon oxide film (SiO ₂ film) 6 serving as a second-layer interelectrode insulating film is deposited on the first silicon nitride film 5. Since the first silicon oxide film 6 becomes an oxide film on the lower layer side with respect to a second silicon oxide film 8 to be described later, it is also referred to as a bottom oxide film. Subsequently, a second silicon nitride film (SiN film) 7 serving as a third-layer interelectrode insulating film is deposited on the first silicon oxide film 6. Subsequently, a second silicon oxide film (SiO ₂ film) 6 serving as a fourth-layer interelectrode insulating film is deposited on the second silicon nitride film. Since the second silicon oxide film 6 is an upper oxide film with respect to the first silicon oxide film 6 described above, it is also referred to as a top oxide film. Subsequently, on the second silicon oxide film 8, a third silicon nitride film (SiN film) 9 serving as a fifth layer (uppermost layer) interelectrode insulating film is deposited. The interelectrode insulating film 4 having a structure in which the silicon nitride films 5, 7, 9 and the silicon oxide films 6, 8 are alternately stacked in the five layers by the above steps is formed into the first P-added polycrystalline silicon film 3. Formed on. The first, second, and third silicon nitride films 5, 7, 9, and the first and second silicon oxide films 6, 8 may be formed by, for example, a CVD method.

  Subsequently, a second polycrystalline silicon film 10 is deposited on the third silicon nitride film 9 which is the uppermost insulating film of the interelectrode insulating film 4. Then, like the first P-added polycrystalline silicon film 3, phosphorus (P) as an impurity is added to the second polycrystalline silicon film 10 by an ion implantation method. The second P-added polycrystalline silicon film 10 is processed into a predetermined shape in a subsequent process to become a control gate electrode (control gate electrode).

  Subsequently, a processing hard mask material 11 made of, for example, a silicon nitride film (SiN film) is deposited on the second P-added polycrystalline silicon film 10, and the processing hard mask material 11 is formed into a predetermined shape. Pattern. Thereafter, using the patterned processing hard mask material 11 as a mask, the laminated film from the second P-added polycrystalline silicon film 10 to the first P-added polycrystalline silicon film 3 is subjected to a normal photolithography process and dry etching. It is processed by the process and molded into a predetermined gate structure. Through the steps so far, a gate structure 13 having the interelectrode insulating film 4 sandwiched between the floating gate electrode 3 and the control gate electrode 10 is formed on the surface of the silicon substrate 1 via the tunnel oxide film 2.

Next, as shown in FIG. 1B, the first heating is performed in an oxidizing atmosphere on the stacked film from the second P-added polycrystalline silicon film 10 to the first P-added polycrystalline silicon film 3. Apply processing. Thereby, the damage received by the stacked film from the second P-added polycrystalline silicon film 10 to the first P-added polycrystalline silicon film 3 by the gate processing step described above is recovered. At this time, an extremely thin silicon oxide film (SiO ₂ film) 12 is formed on the exposed side surfaces of the second P-added polycrystalline silicon film 10 and the first P-added polycrystalline silicon film 3. . The thickness of the silicon oxide film 12 is about 4 nm at most.

  Next, a source / drain diffusion layer 14 having an LDD (Lightly Doped Drain) structure is formed on the surface layer portion of the silicon substrate 1 on which the gate structure 13 is formed. Specifically, first, as indicated by a solid arrow in FIG. 2A, an impurity is implanted into the surface layer portion of the silicon substrate 1 with low energy by an ion implantation method. This is the first ion implantation step. By this first ion implantation process, the extension region 15, which is a shallow junction of the source / drain diffusion layer 14, is sandwiched from the outer sides of the gate structure 13 to which the silicon oxide film 12 is attached, and the surface layer of the silicon substrate 1. Formed in the part. The extension region 15 serves as an electrical junction between the source diffusion layer 14a and the drain diffusion layer 14b and the channel region 17 between the diffusion layers 14a and 14b.

  Next, as shown in FIG. 2B, an impurity-free non-single-crystal silicon film 18 is provided so as to cover the gate structure 13 to which the silicon oxide film 12 is attached and the processing hard mask material 11. The non-single crystal silicon film 18 is formed in a thin shape by, for example, a CVD method. As the non-single crystal silicon film 18, either a polycrystalline silicon film (polysilicon film) or an amorphous silicon film (amorphous silicon film) may be used. However, it is preferable to use an amorphous silicon film as the non-single-crystal silicon film 18 because the amorphous silicon film has better controllability such as surface uniformity and film thickness than the polysilicon film. Therefore, here, an impurity-free amorphous silicon film (α-Si film) is formed as the non-single-crystal silicon film 18 without impurities.

Next, as shown in FIG. 3A, an insulating film 19 is further provided so as to cover the amorphous silicon film 18 to which no impurities are added. This insulating film 19 functions as a sidewall protective film of the gate structure 13 when a further processing process is performed as a post process. Here, a silicon oxide film (SiO ₂ film) is deposited as the insulating film 19 on the surface of the amorphous silicon film 18 by the CVD method.

Next, as shown in FIG. 3B, the amorphous silicon film 18 and the gate structure 13 covered with the silicon oxide film 19 are subjected to a second heat treatment in an oxidizing atmosphere. Thereby, the silicon oxide film 19 is baked and hardened to be densified. At this time, the amorphous silicon film 18 is integrated with the silicon oxide film 19 and becomes a part of a thicker silicon oxide film (SiO ₂ film) 20. A portion of the silicon oxide film 20 on the side surface of the gate structure 13 becomes a gate sidewall film (sidewall oxide film) 21 together with the silicon oxide film 12.

  In the present embodiment, unlike the conventional gate structure forming method described in the background art, the silicon oxide film 19 that becomes a part of the gate sidewall film 21 is not provided directly on the side surface of the gate structure 13. In the present embodiment, as described above, prior to the formation of the silicon oxide film 19 on the side surface of the gate structure 13, the amorphous silicon film 18 without addition of impurities is provided to cover the side surface of the gate structure 13. As a result, the silicon oxide film 19 does not directly contact the side surfaces of the floating gate electrode 3 and the control gate electrode 10 made of a polysilicon film to which phosphorus (P) as an impurity is added. Further, the amorphous silicon film 18 which is the base layer of the silicon oxide film 19 is free of impurities. Further, an extremely thin silicon oxide film 12 is interposed between the amorphous silicon film 18 and the floating gate electrode 3 and the control gate electrode 10. The silicon oxide film 12 functions as a diffusion preventing film for preventing phosphorus inside the floating gate electrode 3 and the control gate electrode 10 from diffusing outside the electrodes 3 and 10.

  According to such a structure, there is almost no possibility that phosphorus inside the floating gate electrode 3 and the control gate electrode 10 will reach the silicon oxide film 19. For this reason, even if there is a variation in the concentration of phosphorus in each of the gate electrodes 3 and 10, the speed increase due to phosphorus in the gate electrodes 3 and 10 is performed when the second heat treatment is performed. There is almost no risk of oxidation occurring in the silicon oxide film 19. As a result, there is almost no possibility that the silicon oxide film 19 has a variation in film thickness due to the phosphorus concentration dependency that the film thickness increases as the phosphorus concentration in the underlayer increases. As a result, there is almost no possibility that the silicon oxide film 20 will vary in film thickness.

  Further, as described above, the thickness of the silicon oxide film 12 is at most about 4 nm, and is extremely thinner than the amorphous silicon film 18, the silicon oxide film 19, or the silicon oxide film 20. For this reason, the silicon oxide film 12 partially formed on the side surface of the gate structure 13 affects the height and in-plane uniformity (flatness) of the surface of the silicon oxide film 20 on the side surface of the gate structure 13. There is virtually no fear. That is, substantially no step or unevenness is generated on the surface of the silicon oxide film 20 on the side surface of the gate structure 13. At the same time, the thickness of the silicon oxide film 20 on the side surface of the gate structure 13 can be substantially regarded as the thickness of the gate sidewall film 21. Therefore, the film thickness of the gate sidewall film 21 composed of the silicon oxide film 12 and the silicon oxide film 20 on the side surface of the gate structure 13 is substantially uniform. There is virtually no variation or the like.

  Next, as indicated by the solid line arrow in FIG. 4, impurities are formed by ion implantation in the same manner as in the first ion implantation step toward the surface layer portion of the silicon substrate 1 having the gate structure 13 covered with the silicon oxide film 20. Inject. This is the second ion implantation step. This second ion implantation step is performed with higher energy than the first ion implantation step. By this second ion implantation step, a contact region 16 which is a deep junction in the source / drain diffusion layer 14 is formed so as to reach a position deeper than the extension region 15 in the surface layer portion of the silicon substrate 1. The impurity concentration in the contact region 16 is higher than the impurity concentration in the extension region 15.

  The contact region 16 is formed by sandwiching the gate structure 13 covered with the silicon oxide film 20 from both outsides. That is, the contact region 16 is formed so as to be further shifted toward both outer sides of the gate structure 13 by the thickness of the silicon oxide film 20 with respect to the extension region 15. As shown in FIG. 4, the region where the contact region 16 is displaced from the extension region 15 becomes an offset region 22 for electrically separating the contact region 16 from the channel region 17. Through the steps so far, the floating gate type transistor 23 including the tunnel oxide film 2, the gate structure 13, the source / drain diffusion layers 14 a and 14 b, and the gate sidewall film 21 is provided in the surface layer portion of the silicon substrate 1.

  As described in the background art, when forming a source / drain diffusion layer having an LDD structure, the gate sidewall film usually functions as a spacer for forming an offset region. For this reason, the size (width) of the offset region and the formation position of the contact region are defined according to the film thickness of the gate sidewall film. As a result, the formation position and shape of the source / drain diffusion layer are determined according to the film thickness of the gate sidewall film. Therefore, how to improve the controllability of the film thickness of the gate sidewall film is a point as to whether or not the source / drain diffusion layer can be formed with precise control of the position in the source / drain direction.

  In the present embodiment, as described above, both ends of the gate structure 13 are equal to the thickness of the silicon oxide film 12 in the gate sidewall film 21 formed of the silicon oxide film 20 on the side surfaces of the silicon oxide film 12 and the gate structure 13. The extension region 15 is formed by being shifted in advance from the portion toward both outer sides of the gate structure 13. Therefore, in the present embodiment, the silicon oxide film 20 on the side surface of the gate structure 13 in the gate sidewall film 21 serves as a spacer for forming the offset region 22. The size of the offset region 22 and the position where the contact region 16 is formed are defined according to the thickness of the silicon oxide film 20 on the side surface of the gate structure 13.

  As described above, in the present embodiment, the silicon oxide film 20 on the side surface of the gate structure 13 constituting most of the gate sidewall film 21 has a step or unevenness on its surface, or there is a variation in film thickness. It can form, suppressing generating. That is, the silicon oxide film 20 can be formed while controlling the surface uniformity (flatness) and film thickness with high accuracy. As a result, according to the present embodiment, variations and errors in the formation positions of the contact region 16 and the offset region 22 can be suppressed and kept within the allowable range in the second ion implantation step. That is, the formation positions of the contact region 16 and the offset region 22 can be controlled with high accuracy, and the respective regions 16 and 22 can be formed at desired positions.

  In FIGS. 1A, 1B, 2A, 2B, 3A, 3B, and 4, the floating gate type transistor 23 according to the present embodiment is formed. Only one transistor 23 is shown for easy understanding of the process. However, in a flash memory that is actually a product, a plurality of transistors 23 are provided close to each other on the surface layer portion of the silicon substrate 1. For example, FIG. 5 shows only two adjacent transistors 23 among the plurality of transistors 23 provided in the surface layer portion of the silicon substrate 1. The amorphous silicon film 18 and the silicon oxide film 19 shown in FIGS. 2B and 3A referred to above are actually plural on the surface of the silicon substrate 1, as shown in FIG. These gate structures 13 are collectively covered. However, the steps of providing the amorphous silicon film 18 and the silicon oxide film 19 and the steps after providing the respective films 18 and 19 are the same as those shown in FIGS. 2 (b), 3 (a), 3 (b), and FIG. Since the steps are the same as those described with reference to FIG. 6A and 6B referred to in the following description, only the two adjacent transistors 23 among the plurality of transistors 23 are shown in the same manner as FIG. 5 and FIGS. 6A and 6B, the source / drain diffusion layers 14a and 14b and the channel region 17 between the transistors 23 are not shown in order to make the drawings easy to see.

  Next, as shown in FIG. 6A, the processing hard mask material 11 and the silicon oxide film 20 provided on each gate structure 13 are removed by polishing, for example, by a CMP method. Subsequently, although not shown, the silicon oxide film 20 that covers each gate structure 13 and is provided on the surface of the silicon substrate 1 is selectively removed by, for example, RIE. Thereby, the surface of the silicon substrate 1 is once exposed.

Next, as shown in FIG. 6B, prior to providing a wiring such as a bit line (not shown) above each transistor 23, the interlayer insulating film 24 covers the surface of each gate structure 13 and the silicon substrate 1. Is provided. Here, as the interlayer insulating film 24, for example, a silicon oxide film (SiO ₂ film) is deposited on the surface of the silicon substrate 1 by the CVD method. Subsequently, although not shown, the silicon oxide film 24 provided on each gate structure 13 is removed by polishing, for example, by CMP. Subsequently, a processing stopper film 25 is provided on the control gate electrode 10 of each gate structure 13. The processing stopper film 25 functions as a protective film for preventing each control gate electrode 10 from being damaged in the process of processing the silicon oxide film 24 to form a wiring. Here, as the processing stopper film 25, for example, a silicon nitride film (SiN film) is formed.

  As described above, in this embodiment, there is almost no possibility that a step or unevenness is generated on the surface of the silicon oxide film 19 on the side surface of the gate structure 13 or that the silicon oxide film 19 has a variation in film thickness. No. Further, the thickness of the silicon oxide film 12 is at most about 4 nm, and is extremely thinner than the silicon oxide film 24 formed thicker than the silicon oxide film 19. For this reason, there is almost no possibility that a step or unevenness is generated on the surface of the silicon oxide film 24 formed by the same process as the silicon oxide film 19 or that the film thickness of the silicon oxide film 24 is not uniform. That is, the surface of the silicon oxide film 24 on the side surface of the gate structure 13 is substantially flat and the film thickness is substantially uniform, like the silicon oxide film 19 and the silicon oxide film 20. Therefore, there is almost no possibility that voids are generated inside the silicon oxide film 24 provided by filling a minute gap between the gate structures 13 provided close to each other. As a result, there is almost no possibility that a recess starting from a void is generated inside the silicon oxide film 24 between the gate structures 13. As a result, there is almost no possibility that the silicon nitride film 25 penetrates into the silicon oxide film 24 between the gate structures 13.

  Thereafter, although not shown in the figure, a bit line and a contact plug for connecting the bit line and the source / drain diffusion layers 14a and 14b are provided on the silicon substrate 1. As a result, as shown in FIG. 6B, a flash memory according to this embodiment having a structure in which a plurality of floating gate transistors 23 are provided close to each other on the surface layer portion of the silicon substrate 1 is obtained. Can do.

  As described above, according to the first embodiment, variation in the film thickness of the side wall film (side wall oxide film) 21 of the gate structure 13 including the floating gate electrode 3 and the control gate electrode 10 is suppressed and the side wall is suppressed. The flatness of the surface of the film 21 can be improved. Thereby, the controllability of the positions and shapes of the source / drain diffusion layers 14a, 14b can be improved, and the source / drain diffusion layers 14a, 14b can be formed at desired positions with high accuracy. In addition, the generation of voids in the silicon oxide film 24 provided by burying minute gaps between the gate structures 13 (transistors 23) adjacent to each other and the generation of depressions starting from the voids can be reduced. The silicon nitride film 25 can be made difficult to enter between the structures 13. As a result, it is possible to suppress an increase in the dielectric constant between the adjacent transistors 23 and an increase in parasitic capacitance, and to reduce threshold interference between the transistors 23. As a result, the electrical characteristics, performance or quality of the floating gate transistor 23 can be improved. As a result, the electrical characteristics, performance, quality, etc. of the entire flash memory including a large number of such floating gate type transistors 23 can be improved.

  As described above, according to the first embodiment of the present invention, the variation in the thickness of the sidewall film 21 of the floating gate electrode 3 and the control gate electrode 10 included in the flash memory as the semiconductor device is suppressed and the sidewall film 21 By improving the flatness of the surface, the electrical characteristics, performance, quality, etc. of the flash memory can be improved.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment mentioned above, and those detailed description is abbreviate | omitted. The present embodiment is substantially the same as the first embodiment except that the method for forming the gate sidewall film is different from the first embodiment. Hereinafter, it demonstrates concretely and in detail.

  First, as shown in FIG. 7A, a tunnel insulating film 2, a first P-added polycrystalline silicon film 3, a first silicon nitride film 5, and a first silicon oxide film 6 are formed on the surface of the silicon substrate 1. The second silicon nitride film 7, the second silicon oxide film 8, the third silicon nitride film 9, the second P-added polycrystalline silicon film 10, and the processing hard mask material 11 are sequentially stacked and deposited. . Subsequently, the laminated film from the processing hard mask material 11 to the first P-added polycrystalline silicon film 3 is processed and formed into a predetermined gate structure. The steps so far are the same as those described with reference to FIG. 1A in the first embodiment. Through the steps so far, a gate structure 13 having the interelectrode insulating film 4 sandwiched between the floating gate electrode 3 and the control gate electrode 10 is formed on the surface of the silicon substrate 1 via the tunnel oxide film 2.

Next, as shown in FIG. 7B, a first insulating film 31 is provided on the side surfaces of the floating gate electrode 3 and the control gate electrode 10. Here, a silicon oxide film (SiO ₂ film) having a very thin film thickness is provided as the first insulating film 31. The silicon oxide film 31 is formed, for example, by subjecting the side walls of the floating gate electrode 3 and the control gate electrode 10 to wet treatment using ozone water (O ₃ ) or hydrogen peroxide water (H ₂ O ₂ ). . Here, the silicon oxide film 31 is formed with a film thickness of about 0.5 to 1 nm. Therefore, the silicon oxide film 31 is formed on the side surfaces of the first and second P-added polycrystalline silicon films 3 and 10 in the same manner as the silicon oxide film 31. 12, and the silicon oxide film 31 is thinner than the silicon oxide film 12. Similarly to the silicon oxide film 12 of the first embodiment, the silicon oxide film 31 is also a diffusion preventing film that prevents phosphorus inside the floating gate electrode 3 and the control gate electrode 10 from diffusing outside the electrodes 3 and 10. Function as.

Next, as shown in FIG. 8A, a non-single crystal silicon film 32 with no impurities is formed covering the gate structure 13 in which the side surfaces of the floating gate electrode 3 and the control gate electrode 10 are covered with the silicon oxide film 31. Provide. Here, as the non-single-crystal silicon film 32 without addition of impurities, for example, a silicon oxide film without addition of impurities (SiO ₂ film) is deposited on the gate structure 13 and the silicon oxide film 31 by the CVD method. Subsequently, a first heat treatment is performed on the gate structure 13 covered with the silicon oxide film 32 in an oxidizing atmosphere. Thereby, the damage received by the laminated film from the second P-added polycrystalline silicon film 10 to the first P-added polycrystalline silicon film 3 by the gate processing step is recovered.

  Next, as shown by a solid line arrow in FIG. 8B, a first ion implantation step is performed on the surface layer portion of the silicon substrate 1 on which the gate structure 13 is formed by the same method as in the first embodiment. . As a result, the extension region 15 is formed in the surface layer portion of the silicon substrate 1 with the gate structure 13 covered with the silicon oxide film 32 sandwiched from both outer sides thereof.

Next, as shown in FIG. 9A, a second insulating film 33 is provided to further cover the silicon oxide film 32 provided so as to cover the gate structure 13. The second insulating film 33, together with the silicon oxide film 31 and the silicon oxide film 32, becomes a part of the side wall protective film of the gate structure 13 in a wiring processing process as a subsequent process. Here, as the second insulating film 33, a silicon oxide film (SiO ₂ film) is deposited on the silicon oxide film 32 by a CVD method, for example, like the silicon oxide film 32.

Next, as shown in FIG. 9B, the gate structure 13 covered with the silicon oxide film 32 and the silicon oxide film 33 is subjected to a second heat treatment in an oxidizing atmosphere. Thus, the silicon oxide films 32 and 33 are baked and densified, and the silicon oxide films 32 and 33 are integrated to form a thicker silicon oxide film (SiO ₂ film) 34. To do. A portion of the silicon oxide film 34 on the side surface of the gate structure 13 becomes a gate side wall film 35 as a side wall protective film together with the silicon oxide film 31.

  Next, as shown by the solid line arrow in FIG. 10, the second ion implantation is performed on the surface layer portion of the silicon substrate 1 having the gate structure 13 covered with the silicon oxide film 34 by the same method as in the first embodiment. Apply the process. As a result, the contact region 16 is formed on the surface layer portion of the silicon substrate 1 with the gate structure 13 covered with the silicon oxide film 34 sandwiched from both outer sides thereof. The contact region 16 is formed by being further shifted from the extension region 15 toward both outer sides of the gate structure 13 by the thickness of the silicon oxide film 33. Therefore, the thickness of the silicon oxide film 33 becomes the size (width) of the offset region 22. Through the steps so far, the floating gate type transistor 36 including the tunnel oxide film 2, the gate structure 13, the source / drain diffusion layers 14 a and 14 b, and the gate sidewall film 35 is provided on the surface layer portion of the silicon substrate 1.

  As in the first embodiment, FIGS. 7A, 7B, 8A, 8B, 9A, 9B, and 10 show the present embodiment. In order to easily explain the process of forming the floating gate type transistor 36, only one transistor 36 is shown. On the other hand, FIG. 11 shows only two adjacent transistors 36 among the plurality of transistors 36 provided on the surface layer portion of the silicon substrate 1. Further, the silicon oxide films 32 and 33 shown in FIGS. 8A, 8B and 9A referred to above are actually on the surface of the silicon substrate 1 as shown in FIG. A plurality of gate structures 13 are collectively covered. However, the process of providing the silicon oxide films 32 and 33 and the process after providing the silicon oxide films 32 and 33 are described with reference to FIGS. 8A, 8B and 9A. Since it is the same as the process described, the description thereof is omitted. Also, FIGS. 12A and 12B referred to in the following description show only two adjacent transistors 36 among the plurality of transistors 36 as in FIG. Further, in FIG. 11 and FIGS. 12A and 12B, illustration of the source / drain diffusion layers 14a and 14b and the channel region 17 between the transistors 36 is omitted for easy understanding of the drawings.

  Next, as shown in FIG. 12A, the processing hard mask material 11 and the silicon oxide film 34 provided on each gate structure 13 are removed by the same process as in the first embodiment. Subsequently, although not shown, the silicon oxide film 34 provided on the surface of the silicon substrate 1 covering each gate structure 13 is removed to once expose the surface of the silicon substrate 1.

Next, as shown in FIG. 12B, a silicon oxide film (SiO ₂ film) 24 as an interlayer insulating film is formed so as to cover the surface of each gate structure 13 and the silicon substrate 1 by the same process as in the first embodiment. Is provided. Subsequently, although not shown, the silicon oxide film 24 provided on each gate structure 13 is removed by polishing, for example, by CMP. Subsequently, a silicon nitride film (SiN film) 25 as a processing stopper film is provided on the control gate electrode 10 of each gate structure 13.

  Thereafter, although not shown in the figure, a bit line and a contact plug for connecting the bit line and the source / drain diffusion layers 14a and 14b are provided on the silicon substrate 1. As a result, as shown in FIG. 12B, the flash memory according to this embodiment having a structure in which a plurality of floating gate transistors 36 are provided close to each other on the surface layer portion of the silicon substrate 1 is obtained. Can do.

  As described above, in the second embodiment, the heat treatment (annealing treatment) for removing the damage received by the gate electrodes 3 and 10 in the process of forming the floating gate electrode 3 and the control gate electrode 10. Is applied to each of the gate electrodes 3 and 10 in an oxidizing atmosphere, and a silicon oxide film 31 as an anti-diffusion film and an impurity-free silicon oxide film 32 are continuously covered to cover the side surfaces of the gate electrodes 3 and 10. Provide. Therefore, like the silicon oxide film 19 of the first embodiment, the silicon oxide film 33 is directly formed on the side surfaces of the floating gate electrode 3 and the control gate electrode 10 made of a polysilicon film to which phosphorus (P) as an impurity is added. There is no contact. At the same time, there is almost no possibility that phosphorus inside the floating gate electrode 3 and the control gate electrode 10 will reach the silicon oxide film 33. Further, as described above, the silicon oxide film 31 is formed thinner than the silicon oxide film 12 of the first embodiment.

  According to such a structure, the gate sidewall film 35 made of the silicon oxide film 31 and the silicon oxide film 34 on the side surface of the gate structure 13 has a film thickness greater than that of the gate sidewall film 21 of the first embodiment. In addition to being uniformed, steps and irregularities on the surface are also reduced. That is, according to the present embodiment, it is possible to further suppress the variation in the film thickness of the gate sidewall film 35 and further improve the flatness of the surface of the sidewall film 21 as compared with the gate sidewall film 21 of the first embodiment. it can. Thereby, the controllability of the position and shape of the source / drain diffusion layers 14a, 14b is further improved as compared with the first embodiment, and the source / drain diffusion layers 14a, 14b are formed at a desired position with higher accuracy. Can do.

  In addition, there is a possibility that a step or unevenness may occur on the surface of the silicon oxide film 24 formed by the same process as the silicon oxide film 33, or the film thickness of the silicon oxide film 24 may vary. This is reduced as compared with the silicon oxide film 24. That is, the silicon oxide film 24 of this embodiment has a flatter surface and a more uniform film thickness than the silicon oxide film 24 of the first embodiment. For this reason, there is a risk that voids or depressions originating from voids may be generated inside the silicon oxide film 24 provided by filling minute gaps between the gate structures 13 provided close to each other. Compared to As a result, the possibility that the silicon nitride film 25 penetrates into the silicon oxide film 24 between the gate structures 13 is further reduced as compared with the first embodiment. Thereby, it is possible to further suppress an increase in dielectric constant and an increase in parasitic capacitance between the adjacent transistors 23, and to further reduce the threshold interference between the transistors 23 as compared with the first embodiment.

  Therefore, according to the second embodiment, the electrical characteristics, performance, quality, etc. of the floating gate transistor 36 are compared with the electrical characteristics, performance, quality, etc. of the floating gate transistor 23 of the first embodiment. Can be further improved. As a result, the electrical characteristics, performance, quality, etc. of the entire flash memory including a large number of such floating gate transistors 36 can be further improved as compared with the flash memory of the first embodiment.

  Note that the method for manufacturing a semiconductor device according to the present invention is not limited to the first and second embodiments described above. Without departing from the spirit of the present invention, a part of the configuration or manufacturing process can be changed to various settings, or various settings can be appropriately combined and used. .

  For example, the first insulating film 31 formed on the side surfaces of the floating gate electrode 3 and the control gate electrode 10 in the second embodiment is not limited to the silicon oxide film described above. The first insulating film 31 only needs to prevent the phosphorus inside the floating gate electrode 3 and the control gate electrode 10 from diffusing outside the electrodes 3 and 10. At the same time, the method for forming the first insulating film 31 is not limited to the wet treatment described above. For example, as the first insulating film 31, a silicon nitride film or a silicon oxynitride film may be formed on the side surfaces of the floating gate electrode 3 and the control gate electrode 10 by radical nitriding (thermal nitriding).

  Further, the interelectrode insulating film 4 is not limited to the laminated insulating film 4 described above. As the interelectrode insulating film 4, various insulating films can be used by using a single-layer insulating film or by appropriately changing the number and order of stacking of silicon nitride films and silicon oxide films as appropriate. it can. For example, instead of the laminated insulating film 4, a so-called single-layer high dielectric film may be formed as the interelectrode insulating film 4.

Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Tunnel oxide film (tunnel insulating film), 3 ... Floating gate electrode (1st P addition polycrystalline silicon film 3, floating gate electrode), 4 ... Interelectrode insulating film, 5 ... First silicon nitride film (SiN film, first-layer interelectrode insulating film), 6... First silicon oxide film (SiO ₂ film, second-layer interelectrode insulating film), 7. Silicon nitride film (SiN film, third layer inter-electrode insulating film), 8... Second silicon oxide film (SiO ₂ film, fourth layer inter-electrode insulating film), 9. Film (SiN film, fifth interelectrode insulating film), 10... Control gate electrode (second P-doped polycrystalline silicon film 3, control gate electrode), 13... Gate structure, 18. Silicon film (non-single crystal silicon film without impurities), 19. Recon oxide film (SiO ₂ film, insulating film), 31... Silicon oxide film (SiO ₂ film, first insulating film), 32... No impurity added silicon oxide film (no impurity added SiO ₂ film, no impurity added) Non-single crystal silicon film), 33... Silicon oxide film (SiO ₂ film, second insulating film)

Claims (5)

A first heating is performed on at least one gate structure provided on the semiconductor substrate with the inter-electrode insulating film interposed between the floating gate electrode containing the impurity and the control gate electrode and the tunnel insulating film interposed therebetween. Processing,
After implanting impurities toward the surface layer portion of the semiconductor substrate having the gate structure subjected to the first heat treatment, an impurity-free non-single crystal silicon film is provided to cover the gate structure,
An insulating film is further provided so as to cover the non-single crystal silicon film, and then the second heat treatment is performed on the non-single crystal silicon film and the gate structure covered with the insulating film.
A method for manufacturing a semiconductor device. An inter-electrode insulating film is sandwiched between a floating gate electrode containing impurities and a control gate electrode, and the floating gate electrode of at least one gate structure provided on a semiconductor substrate via a tunnel insulating film and Providing a first insulating film on a side surface of the control gate electrode;
An impurity-free non-single-crystal silicon film is provided on the side surface of the gate structure so as to cover the first insulating film,
After implanting impurities into the surface layer portion of the semiconductor substrate having the gate structure provided with the non-single crystal silicon film, a second insulating film is provided to cover the non-single crystal silicon film and the gate structure. ,
Heat-treating the non-single crystal silicon film provided with the second insulating film and the gate structure;
A method for manufacturing a semiconductor device.   3. The semiconductor device according to claim 2, wherein an oxide film as a first insulating film is provided on side surfaces of the floating gate electrode and the control gate electrode by performing a wet process on the gate structure. Method.   The method of manufacturing a semiconductor device according to claim 3, wherein the wet treatment is performed using ozone water or hydrogen peroxide water.   3. The semiconductor device according to claim 2, wherein a nitride film as a first insulating film is provided on side surfaces of the floating gate electrode and the control gate electrode by performing radical nitriding treatment on the gate structure. Production method.

Images