JP2011114470A - Digital delay circuit, and method of controlling digital delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital delay circuit capable of reducing jitters of a clock signal. <P>SOLUTION: A master DLL circuit 11 generates first stage number data Ds1 showing the number of stages of a delay element to be used to delay a reference clock signal CLKr to a predetermined phase. A slave DLL circuit 12 generates second stage number data Ds2 showing the number of stages of a delay element to be used on the basis of the first stage number data Ds1, delays a first clock signal CLK1 at a delay element of the number of stages corresponding to the second stage number data Ds2 and generates a second clock signal CLK2. A phase adjustment circuit 31 of the slave DLL circuit 12 performs correction corresponding to a change in the first stage number data Ds1 to generate second stage number data Ds2 when the first stage number data Ds1 transits between two values. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a digital delay circuit and a method for controlling the digital delay circuit.

Conventionally, a semiconductor device is provided with a DLL (Delay Locked Loop) circuit that generates a second clock signal having a desired phase difference with respect to the first clock signal.
In this type of DLL circuit, a master DLL circuit that detects a delay amount that delays the phase of the reference clock signal by one cycle, and a first clock signal that has a desired phase based on the delay amount that delays the reference clock signal by one cycle. There is known a master / slave DLL type DLL circuit having a slave DLL circuit that generates a second clock signal with a delay of up to (for example, see Patent Document 1).

FIG. 4 is a basic circuit diagram of a master / slave DLL type DLL circuit 60.
The master DLL circuit 61 includes a first delay circuit 62, a phase comparison circuit 63, and a delay control circuit 64.

  The first delay circuit 62 has a plurality of delay elements (buffer circuits) connected in series, delays the reference clock signal CLKr, and outputs it as a comparison clock signal CLKc. The first delay circuit 62 is connected in series according to the first stage number data Ds1 for designating the number of stages of delay elements connected in series in the first delay circuit 62 from the delay control circuit 64. Change the number of delay elements.

  The phase comparison circuit 63 receives the reference clock signal CLKr, and receives the comparison clock signal CLKc obtained by delaying the reference clock signal CLKr via the first delay circuit 62. The phase comparison circuit 63 compares the phase of the reference clock signal CLKr with the phase of the comparison clock signal CLKc, and outputs the comparison result as the phase comparison signal Sc.

  The delay control circuit 64 changes the phase of the comparison clock signal CLKc with respect to the phase of the reference clock signal CLKr in accordance with the phase comparison signal Sc from the phase comparison circuit 63, and the first delay circuit 62 1 The first stage number data Ds1 for delaying by the period is output.

  Specifically, when the phase of the comparison clock signal CLKc is advanced with respect to the reference clock signal CLKr, the phase comparison circuit 63 causes the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr to be one cycle of the reference clock signal CLKr. Is less than a minute delay. Therefore, when the phase of the comparison clock signal CLKc is smaller than the delay of one cycle of the reference clock signal CLKr with respect to the reference clock signal CLKr, the delay control circuit 64 increases the number of delay elements connected in series. The first stage number data Ds1 is output to increase the number of stages of delay elements connected in series with the first delay circuit, and the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr is increased.

  On the other hand, when the phase of the comparison clock signal CLKc is delayed with respect to the reference clock signal CLKr, the phase comparison circuit 63 causes the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr to be one cycle of the reference clock signal CLKr. It is larger than the delay. Therefore, when the phase of the comparison clock signal CLKc is larger than the delay of one cycle of the reference clock signal CLKr with respect to the reference clock signal CLKr, the delay control circuit 64 reduces the number of delay elements connected in series. The first stage number data Ds1 is output to reduce the number of stages of delay elements connected in series with the first delay circuit 62, thereby reducing the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr.

The slave DLL circuit 65 includes a phase adjustment circuit 66 and a second delay circuit 67.
The phase adjustment circuit 66 receives the first stage number data Ds1 from the delay control circuit 64 of the master DLL circuit 61 and the phase setting data Dp. Then, the phase adjustment circuit 66 delays the first clock signal CLK1 to a phase corresponding to the phase setting data Dp by the second delay circuit 67 based on the first stage number data Ds1 and the phase setting data Dp. The number of stages of the element is calculated, and second stage number data Ds2 of the number of stages is output.

  The second delay circuit 67 has a plurality of delay elements (buffer circuits) connected in series, delays the first clock signal CLK1, and outputs it as the second clock signal CLK2. The second delay circuit 67 changes the number of delay elements connected in series according to the second stage number data Ds2 from the phase adjustment circuit 66.

  Therefore, the second delay circuit 67 can generate the second clock signal CLK2 obtained by delaying the first clock signal CLK1 to the phase corresponding to the phase setting data Dp based on the second stage number data Ds2.

JP 2005-142859 A

  However, the phase of the comparison clock signal CLKc rarely matches the reference clock signal CLKr. This is because the delay time of the comparison clock signal CLKc changes digitally with respect to the reference clock signal CLKr. For example, the output signal of the delay element in the (n−1) stage has a phase smaller than the delay of one cycle of the reference clock signal CLKr, and the output signal of the delay element in the (n) stage is the reference clock signal CLKr. If the delay is greater than one cycle, the first stage number data Ds1 output from the master DLL circuit always fluctuates. For this reason, in the slave DLL circuit 65, the number of stages of the delay elements in the second delay circuit 67 is calculated based on the fluctuating first stage number data Ds1, so the second stage number data Ds2 also fluctuates and the second delay time is increased. Jitter occurs in the second clock signal CLK2 generated by the circuit 67.

  According to an aspect of the present invention, the digital delay circuit includes a stage number data generation circuit that generates first stage number data indicating the number of stages of delay elements used to delay the reference clock signal to a predetermined phase, and Second stage number data indicating the number of stages of delay elements to be used is generated based on the stage number data, and a second clock signal is generated by delaying the first clock signal by the number of stage delay elements corresponding to the second stage number data. When the first stage number data transitions between two values, the signal generation circuit performs correction according to a change in the first stage number data and generates the second stage number data.

  According to one aspect of the present invention, clock signal jitter is reduced.

It is a block diagram of a digital DLL circuit. It is a block diagram of a phase adjustment circuit. It is operation | movement explanatory drawing of a phase adjustment circuit. It is a block diagram of a digital DLL circuit.

Hereinafter, embodiments will be described with reference to FIGS.
FIG. 1 is a schematic configuration diagram of the digital DLL circuit 10. As shown in FIG. 1, the digital DLL circuit 10 includes a master DLL circuit 11 and a slave DLL circuit 12.

(Master DLL circuit)
The master DLL circuit 11 includes a first delay circuit 21, a phase comparison circuit 22, and a delay control circuit 23. The first delay circuit 21 has a plurality of delay elements (not shown) (for example, a buffer circuit made of a CMOS transistor), receives a reference clock signal CLKr from the outside, and is connected in series in the first delay circuit 21 from the delay control circuit 23. First stage number data Ds1 for designating the number of stages of delay elements connected to is input.

  The first stage number data Ds1 is data specifying the number of delay elements (number of stages) connected in series between the input / output terminals in the first delay circuit 21. In the present embodiment, the first stage number data Ds1 is composed of 10-bit data from “0000000000000” to “1111111111” and is data indicating the number of stages from “0” to “1023” in decimal. Yes.

  The first delay circuit 21 increases or decreases the number of delay elements connected in series according to the first stage number data Ds1. The first delay circuit 21 outputs a signal delayed from the reference clock signal CLKr as the comparison clock signal CLKc from the output terminal according to the number of delay elements connected in series.

  The phase comparison circuit 22 receives the reference clock signal CLKr from the outside, and receives the comparison clock signal CLKc from the first delay circuit 21. The phase comparison circuit 22 compares the phase of the comparison clock signal CLKc with the phase of the reference clock signal CLKr, and outputs a phase comparison signal Sc corresponding to the comparison result.

  That is, the phase comparison circuit 22 determines whether the phase of the comparison clock signal CLKc is smaller or larger than the delay of one cycle of the reference clock signal CLKr with respect to the reference clock signal CLKr. When the phase of the comparison clock signal CLKc with respect to the reference clock signal CLKr is smaller than the delay of one period of the reference clock signal CLKr, the phase comparison circuit 22 outputs, for example, an L level phase comparison signal Sc, and the reference clock signal When the phase of the comparison clock signal CLKc with respect to CLKr is larger than the delay of one cycle of the reference clock signal CLKr, for example, an H level phase comparison signal Sc is output.

  The delay control circuit 23 includes a register Re for storing the first stage number data Ds1 at that time, a first counter circuit C1 for counting the H level phase comparison signal Sc from the phase comparison circuit 22, and an L level phase comparison signal Sc. A second counter circuit C2 for counting is provided.

  The register Re stores, as an initial value, first stage number data Ds1 determined in advance at the time of initial setting. The delay control circuit 23 adds to or subtracts from the first stage number data Ds1 based on the count results of the first counter circuit C1 and the second counter circuit C2, and updates the first stage number data Ds1 stored in the register Re. It has become. Then, the delay control circuit 23 outputs the first stage number data Ds1 stored in the register Re.

  When the phase comparison signal Sc is at the H level, the first counter circuit C1 counts up the first count value Vc1 in response to the rising of the reference clock signal CLKr to the H level, and when the phase comparison signal Sc is at the L level. The first count value Vc1 is reset. When the first count value Vc1 reaches the stage number decrease value Vcd (in this embodiment, Vcd = 3), the first counter circuit C1 outputs an H level stage number decrease signal Sdn.

  The delay control circuit 23 subtracts (decrements) “1” from the first stage number data Ds1 of the register Re in response to the H level stage number reduction signal Sdn, and sets the value of the subtraction result as new first stage number data. Stored in the register Re as Ds1. Then, the delay control circuit 23 outputs the first stage number data Ds1 stored in the register Re. Therefore, the first stage number data Ds1 decreases “1”.

  The first delay circuit 21 generates the comparison clock signal CLKc by the number of stages of delay elements corresponding to the first stage number data Ds1. Since the first stage number data Ds1 is decreased by “1”, the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr is shortened, and the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr is decreased.

  Then, the phase comparison circuit 22 outputs an L level phase comparison signal Sc. Then, the second counter circuit C2 resets the first count value Vc1 in response to the L level phase comparison signal Sc, and outputs the L level stage number decrease signal Sdn.

  When the phase comparison signal Sc is at the L level, the second counter circuit C2 counts up the second count value Vc2 in response to the rising of the reference clock signal CLKr to the H level, and when the phase comparison signal Sc is at the H level. The second count value Vc2 is reset. When the second count value Vc2 reaches the stage number increase value Vcu (in this embodiment, Vcu = 3), the second counter circuit C2 outputs an H level stage number increase signal Sup.

  In response to the H-level stage number increase signal Sup, the delay control circuit 23 adds (increments) “1” to the first stage number data Ds1 of the register Re, and sets the value of the addition result as new first stage number data Ds1. Is stored in the register Re. Then, the delay control circuit 23 outputs the first stage number data Ds1 stored in the register Re. Accordingly, the first stage number data Ds1 increases “1”.

  The first delay circuit 21 generates the comparison clock signal CLKc by the number of stages of delay elements corresponding to the first stage number data Ds1. Since the first stage number data Ds1 increases “1”, the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr becomes longer, and the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr becomes longer.

  Then, the phase comparison circuit 22 outputs an H level phase comparison signal Sc. Then, the second counter circuit C2 resets the second count value Vc2 in response to the H level phase comparison signal Sc, and outputs an L level stage number increase signal Sup.

  That is, the delay control circuit 23 obtains “1” from the first stage number data Ds1 when the phase comparison signal Sc is continuously at the H level until the first count value Vc1 becomes the stage number decrease value Vcd. Decrease. The first delay circuit 21 decreases “1” from the number of stages of delay elements connected in series according to the first stage number data Ds1, and reduces the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr.

  Further, the delay control circuit 23 sets “1” to the first stage number data Ds1 when the phase comparison signal Sc is continuously at the L level until the second count value Vc2 reaches the stage number increase value Vcu. increase. The first delay circuit 21 increases “1” to the number of stages of delay elements connected in series according to the first stage number data Ds1, and increases the delay time of the comparison clock signal CLKc with respect to the reference clock signal CLKr.

  The delay control circuit 23 does not change the first stage number data Ds1 when the level of the phase comparison signal Sc is not continuous for a period corresponding to the stage number decrease value Vcd and the stage number increase value Vcu. As a result, the delay control circuit 23 switches between the H level and the L level of the phase comparison signal Sc in a short time, that is, without excessively following the advance / delay of the phase of the comparison clock signal CLKc with respect to the reference clock signal CLKr. Stable first stage number data Ds1 is generated.

(Slave DLL circuit)
The slave DLL circuit 12 includes a phase adjustment circuit 31 and a second delay circuit 32. The second delay circuit 32 includes a plurality of delay elements (for example, buffer circuits made of CMOS transistors) having the same configuration (electrical characteristics) as the first delay circuit 21.

The phase adjustment circuit 31 receives the first stage number data Ds1, the stage number increase signal Sup, and the stage number decrease signal Sdn from the master DLL circuit 11, and receives the phase setting data Dp from the outside.
The phase setting data Dp is data indicating a phase difference between the second clock signal CLK2 generated by the slave DLL circuit 12 and the first clock signal CLK1. The number of bits of the phase setting data Dp corresponds to a unit for setting the phase difference of the second clock signal CLK2 with respect to the first clock signal CLK1. The setting unit is a value obtained by dividing the delay time (phase difference) according to the number of stages of the first stage number data Ds1 calculated based on the reference clock signal CLKr in the master DLL circuit 11 by an integer.

  As described above, the master DLL circuit 11 has the first stage number so as to generate the comparison clock signal CLKc delayed by one cycle of the signal CLKr with respect to the reference clock signal CLKr, that is, the phase difference of 360 degrees. Data Ds1 is generated. For example, when the phase difference of the second clock signal CLK2 with respect to the first clock signal CLK1 is set every 45 degrees (1/8 of 360 degrees), the phase setting data Dp is 3 bits from “000” to “111” It takes a value from “0” to “7” in decimal.

  When the phase of the second clock signal CLK2 is delayed by 45 ° with respect to the first clock signal CLK1, the phase setting data Dp is “001”, and when the phase is delayed by 90 °, the phase setting data Dp is “010”. .

  Based on the first stage number data Ds1 and the phase setting data Dp, the phase adjustment circuit 31 sets the second clock signal CLK2 to the first clock signal CLK1 by the second delay circuit 32 based on the phase setting data Dp. The number of delay elements connected in series between the input and output terminals of the second delay circuit 32 for making a phase difference (the number of phase adjustment stages) is calculated. Further, the phase adjustment circuit 31 suppresses fluctuations in the number of stages based on the stage number increase signal Sup and the stage number decrease signal Sdn. Then, the phase adjustment circuit 31 outputs the calculated phase adjustment stage number as second stage number data Ds2.

  As shown in FIG. 2, the phase adjustment circuit 31 includes an OR circuit 41, first and second buffer circuits 42 and 43, first and second D-FF (flip-flop) circuits 44 and 45, and first and second latches. Circuits 46 and 47, an adder 48, a multiplier 49, and a divider 50 are provided.

  The OR circuit 41 receives the stage number increase signal Sup and the stage number decrease signal Sdn from the master DLL circuit 11. The OR circuit 41 outputs an H level signal when the stage number increase signal Sup or the stage number decrease signal Sdn is at an H level, and outputs an L level signal when both the signals Sup and Sdn are at an L level. This signal is supplied to the clock input terminal CK of the first D-FF circuit 44 through the first and second buffer circuits 42 and 43 as the stage number increase / decrease signal Sud.

  As described above, the master DLL circuit 11 outputs the H level stage number increase signal Sup or the stage number decrease signal Sdn, and changes the first stage number data Ds1. In other words, the stage number increase / decrease signal Sud of H level is input to the clock input terminal CK of the first D-FF circuit 44 when the first stage number data Ds1 fluctuates.

  The first D-FF circuit 44 receives the stage number reduction signal Sdn at its data input terminal D. The first D-FF circuit 44 outputs a correction signal Sr having a level equal to the level of the stage number decrease signal Sdn in response to the H level signal input to the clock input terminal CK, that is, the H level stage number increase / decrease signal Sud. Output from.

  The first D-FF circuit 44 outputs an L level correction signal Sr when “1” is increased to the first stage number data Ds1, and is corrected to H level when “1” is decreased from the first stage number data Ds1. The signal Sr is output.

  The second D-FF circuit 45 receives the reference clock signal CLKr at its clock input terminal CK, and outputs the synchronization correction signal Srs from its output terminal Q to the adder 48. When the reference clock signal CLKr rises to the H level, the second D-FF circuit 45 holds the level of the correction signal Sr and outputs it as a synchronization correction signal Srs having a level equal to the held level.

  The adder 48 receives the first stage number data Ds1 from the master DLL circuit 11 and the synchronization correction signal Srs from the second D-FF circuit 45. The adder 48 adds the correction value corresponding to the synchronization correction signal Srs to the first stage number data Ds1, calculates the corrected first stage number data CDs1, and outputs the corrected first stage number data CDs1.

  Specifically, when the H level synchronization correction signal Srs is input, the adder 48 adds “1” to the first stage number data Ds1, and when the L level synchronization correction signal Srs is input, the adder 48 receives the first stage number data Ds1. "0" is added to. That is, the adder 48 corrects the first stage number data Ds1 by adding “1” to the first stage number data Ds1 when the first stage number data Ds1 decreases “1” in the master DLL circuit 11. When the master DLL circuit 11 increases “1”, “0” is added to the first stage number data Ds1 for correction. When adding “0”, the second stage number data Ds2 having a value equal to the value of the first stage number data Ds1 is output. In other words, it can be said that the first stage number data Ds1 is not corrected when the first stage number data Ds1 increases “1”.

  The first latch circuit 46 is composed of, for example, the same number of D-FF circuits as the number of bits of the phase setting data Dp. The first latch circuit 46 holds the phase setting data Dp in response to the reference clock signal CLKr, and outputs synchronous phase setting data Dps having a level equal to the held data.

  The multiplier 49 receives the corrected first stage number data CDs 1 from the adder 48, and receives the synchronization phase setting data Dps from the first latch circuit 46. The multiplier 49 multiplies the corrected first stage number data CDs1 by the synchronization phase setting data Dps and outputs the multiplication result as multiplication value data Dm.

  The divider 50 receives the multiplication value data Dm from the multiplier 49 and the number of bits of the phase setting data Dp. The divider 50 is a value corresponding to the number of bits of the phase setting data Dp for the multiplication value data Dm, and is the number of numerical values expressed by the number of bits, and 360 degrees that is the phase difference in the master DLL circuit 11 is obtained. Divide by the number to be divided (in this embodiment, the phase setting data Dp is 3 bits, so “8”), and the division result is output as division value data Dd.

Accordingly, the multiplier 49 and the divider 50 calculate the number of stages of delay elements that delay the first clock signal CLK1 to the phase set by the phase setting data Dp.
Note that the multiplier 49 generates the multiplication value data Dm by summing the values obtained by shifting the correction first stage number data CDs1 to the left according to the bit position of “1” included in the binary phase setting data Dp. . The divider 50 generates the division value data Dd by deleting (truncating or shifting to the right) the lower bits of the multiplication value data Dm according to the number of bits of the phase setting data Dp.

  The second latch circuit 47 holds the divided value data Dd in synchronization with the rising of the reference clock signal CLKr to the H level, and outputs the signal of the held value as the second stage number data Ds2.

With such a configuration, the phase adjustment circuit 31 generates the second stage number data Ds2 based on the following equation.
Ds2 = CDs1 × Dp / 2 ^X
“X” is the number of bits of the phase setting data Dp.

  That is, the phase adjustment circuit 31 corrects the ratio of the amount of shifting the phase of the first clock signal CLK1 set by the phase setting data Dp and the amount of shifting the phase of the reference clock signal CLKr (360 °) to the corrected first stage number data CDs1. As a result, the number of stages of delay elements of the second delay circuit 32 that delays the first clock signal CLK1 to the phase set by the phase setting data Dp is calculated.

  As described above, in the corrected first stage number data CDs1, when “1” is added to the first stage number data Ds1, the adder 48 adds “0” to the first stage number data Ds1, and the first stage number data When “1” is subtracted from Ds1, the adder 48 performs correction for adding “1” to the first stage number data Ds1.

  Accordingly, the correction data generation circuit including the OR circuit 41, the first and second buffer circuits 42 and 43, and the first and second D-FF circuits 44 and 45 increases or decreases in reverse with respect to the increase or decrease of the first stage number data Ds1. A synchronization correction signal Srs is generated. The adder 48 adds the synchronization correction signal Srs to the first stage number data Ds1, and outputs the result as corrected first stage number data CDs1. Accordingly, when the first stage number data Ds1 repeats “n−1” and “n” alternately, the change in the first stage number data Ds1 is canceled by the synchronization correction signal Srs, and the stable corrected first stage number data CDs1 is added. Output from the device 48. As a result, the phase adjustment circuit 31 prevents the second stage number data Ds2 from fluctuating even when the value of the first stage number data Ds1 is alternately changing between “n−1” and “n”. Yes.

  Next, the operation of the phase adjustment circuit 31 when the first stage number data Ds1 alternately changes between “599” and “600” will be described with reference to FIG. For the constituent members, refer to FIGS. 1 and 2.

  First, at time t1, when the reference clock signal CLKr rises to the H level while the first stage number data Ds1 is “599”, the second counter circuit C2 changes the reference clock signal CLKr to the H level. The rising edge is counted, and the second count value Vc2 becomes “1”.

  At time t2, that is, when the third reference clock signal CLKr counted up from time t1 rises to H level, the second counter circuit C2 counts rising of the reference clock signal CLKr to H level, 2 The count value Vc2 is “3”. As a result, the second count value Vc2 becomes equal to the stage number increase value Vcu, so that the second counter circuit C2 outputs an H level stage number increase signal Sup. When an H level stage increase signal Sup is input, the OR circuit 41 outputs an H level stage increase / decrease signal Sud. When the H level stage increase / decrease signal Sud is input, the first D-FF circuit 44 outputs an L level correction signal Sr in response to the L level stage number decrease signal Sdn.

  Then, at time t3, when the reference clock signal CLKr rises to the H level next time, the delay control circuit 23 adds “1” to the first stage number data Ds1 to make “600”. The second D-FF circuit 45 outputs a synchronization correction signal Srs having the same level as the L level correction signal Sr. As a result, the adder 48 adds “0” to the first stage number data Ds1, and the corrected first stage number data CDs1 becomes “600”.

  Here, when the phase setting data Dp is “010”, the corrected first stage number data CDs1 is processed by the multiplier 49 and the divider 50, thereby setting the second stage number data Ds2 to “150”. When the first stage number data Ds1 becomes “600”, the second counter circuit C2 outputs an L level stage number increase signal Sup. When the L level stage increase signal Sup is input, the OR circuit 41 outputs an L level stage increase / decrease signal Sud.

  At time t4, when the reference clock signal CLKr rises to the H level next, the first counter circuit C1 counts the rise of the reference clock signal CLKr to the H level, and the first count value Vc1 is “1”. It becomes.

  Then, at time t5, that is, when the third reference clock signal CLKr counted up from time t4 rises to H level, the first counter circuit C1 counts rising of the reference clock signal CLKr to H level, The one count value Vc1 is “3”. As a result, the first count value Vc1 becomes equal to the stage number decrease value Vcd, and therefore the first counter circuit C1 outputs an H level stage number decrease signal Sdn. When an H level stage number decrease signal Sdn is input, the OR circuit 41 outputs an H level stage number increase signal Sud. When the H-level stage number increase / decrease signal Sud is input, the first D-FF circuit 44 outputs the correction signal Sr according to the H-level stage number decrease signal Sdn.

  At time t6, when the reference clock signal CLKr rises to H level, the delay control circuit 23 subtracts “1” from the first stage number data Ds1 to obtain “599”. The second D-FF circuit 45 outputs a synchronization correction signal Srs having the same level as the H level correction signal Sr. As a result, the adder 48 adds “1” to the first stage number data Ds1 of “599” to set the corrected first stage number data CDs1 to “600”. Then, the corrected first stage number data CDs1 is processed by the multiplier 49 and the divider 50, whereby the second stage number data Ds2 is set to “150”. The phase adjustment circuit 31 repeats the above operation.

  Therefore, when the first stage number data Ds1 decreases from “600” to “599”, the phase adjustment circuit 31 adds “1” to the first stage number data Ds1 to obtain the corrected first stage number data CDs1 of “600”. Output. Further, when the first stage number data Ds1 increases from “599” to “600”, the phase adjustment circuit 31 adds “0” to the first stage number data Ds1 to obtain the corrected first stage number data CDs1 of “600”. Output. As a result, the phase adjustment circuit 31 can maintain the second stage number data Ds2 of “150” in a state where the first stage number data Ds1 is alternately changing between “599” and “600”.

  The second delay circuit 32 receives the second stage number data Ds2 from the phase adjustment circuit 31, and receives the first clock signal CLK1 from the outside. The second delay circuit 32 connects the number of stages of the delay elements according to the second stage number data Ds2 in series, so that the first clock signal CLK1 from the outside is phased based on the phase setting data Dp (in this embodiment, The second clock signal CLK2 delayed to 90 ° is generated.

  Therefore, when the first stage number data Ds1 is alternately transitioning between “n−1” and “n”, the second delay circuit 32 inputs the constant second stage number data Ds2, and therefore the second clock signal CLK2 Can be stably generated.

As described above, according to the present embodiment, the following effects can be obtained.
(1) When the first stage number data Ds1 alternately transitions between “n−1” and “n”, the slave DLL circuit 12 performs a correction according to the change in the first stage number data Ds1 and performs a certain first step. Two-stage data Ds2 is generated. Therefore, since the slave DLL circuit 12 generates the second clock signal CLK2 based on the corrected constant second stage number data, the jitter of the second clock signal CLK2 can be reduced.

  (2) The slave DLL circuit 12 generates the synchronization correction signal Srs according to the change in the first stage number data Ds1 when the first stage number data Ds1 is alternately changed between “n−1” and “n”. The synchronization correction signal Srs is added to the first stage number data Ds1 to generate the corrected first stage number data Ds1 of “n”. Therefore, the slave DLL circuit 12 can generate the second stage number data Ds2 based on the corrected “n” corrected first stage number data CDs1, and reduce the jitter of the second clock signal CLK2.

  (3) When changing the first stage number data Ds1, the master DLL circuit 11 generates a stage number increase signal Sup and a stage number decrease signal Sdn according to the change. The slave DLL circuit 12 generates the second stage number data based on the stage number increase signal Sup and the stage number decrease signal Sdn. Therefore, the digital DLL circuit 10 can reduce the jitter of the second clock signal CLK2 with a simple circuit configuration.

  (4) The master DLL circuit 11 outputs an H level stage number increase signal Sup when increasing the first stage number data Ds1, and outputs an H level stage number decrease signal Sdn when decreasing the first stage number data Ds1. . The slave DLL circuit 12 generates an L level synchronization correction signal Srs when an H level stage number increase signal Sup is input, and generates an H level synchronization correction signal Srs when an H level stage number decrease signal Sdn is input. I made it. Therefore, the digital DLL circuit 10 can reduce the jitter of the second clock signal CLK2 with a simple circuit configuration.

  (5) The slave DLL circuit 12 generates the second stage number data Ds2 based on the corrected first stage number data CDs1 and the phase setting data Dp. Therefore, the digital DLL circuit 10 can reduce the jitter of the second clock signal CLK2 while setting the phase of the second clock signal CLK2 based on the phase setting data Dp.

  (6) The first counter circuit C1 of the delay control circuit 23 counts up the pulse of the reference clock signal CLKr when the phase comparison signal Sc is at the H level, and when the first count value Vc1 reaches the stage number decrease value Vcd. , An H level stage number decrease signal Sdn is output. The second counter circuit C2 of the delay control circuit 23 counts up the pulse of the reference clock signal CLKr when the phase comparison signal Sc is at the L level, and when the second count value Vc2 reaches the stage number increase value Vcu, An H level stage number increase signal Sup is output. Accordingly, the delay control circuit 23 is stable without excessively following the switching of the H level and L level of the phase comparison signal Sc in a short time, that is, the advance / delay of the phase of the comparison clock signal CLKc with respect to the reference clock signal CLKr. The first stage number data Ds1 thus generated can be generated.

  (7) The delay element included in the first delay circuit 21 of the master DLL circuit 11 and the delay element included in the second delay circuit 32 of the slave DLL circuit 12 have the same delay characteristics. Therefore, the digital DLL circuit 10 can generate the second clock signal CLK2 having a phase based on the phase setting data Dp with high accuracy.

In addition, you may implement the said embodiment in the following aspects.
In the present embodiment, when the delay control circuit 23 subtracts “1” from the first stage number data Ds1, the phase adjustment circuit 31 adds “1” to the first stage number data Ds1 and corrects the first stage number. Data Ds1 was generated. The phase adjustment circuit 31 is not limited to this. When the delay control circuit 23 adds “1” to the first stage number data Ds1, the phase adjustment circuit 31 subtracts “1” from the first stage number data Ds1 to correct the first stage number data Ds1. Ds1 may be generated.

  Therefore, in the state where the first stage number data Ds1 alternately transits between “n−1” and “n”, the phase adjustment circuit 31 performs the first step based on the corrected first stage number data CDs1 of “n−1”. Two-stage data Ds2 can be generated.

  As a result, in the above state, the second delay circuit 32 always connects the delay elements of the constant second stage number data Ds2 in series, so that the jitter of the second clock signal CLK2 can be reduced compared to the conventional case. it can.

  In the present embodiment, the first delay circuit 21 receives the reference clock signal CLKr, but may receive the first clock signal CLK1. Even if it does in this way, the effect similar to said embodiment can be acquired.

  In the present embodiment, the delay control circuit 23 subtracts “1” from the first stage number data Ds1 when the first count value Vc1 of the first counter circuit C1 is equal to the stage number decrease value Vcd. On the other hand, the delay control circuit 23 adds “1” to the first stage number data Ds1 when the second count value Vc2 of the second counter circuit C2 becomes equal to the stage number increase value Vcu.

  The delay control circuit 23 subtracts “1” from the first stage number data Ds1 when the H level phase comparison signal Sc is input. Further, the delay control circuit 23 outputs a stage number reduction signal Sdn to the slave DLL circuit 12. On the contrary, when the L level phase comparison signal Sc is input, the delay control circuit 23 may add “1” to the first stage number data Ds 1 and output the stage number increase signal Sup to the slave DLL circuit 12. .

  Therefore, in the state in which the first stage number data Ds1 is alternately changed between “n−1” and “n”, the frequency of the first stage number data Ds1 increasing or decreasing is higher than that in the above embodiment, but the digital DLL circuit 10 Since the second stage number data Ds2 having the same value can be maintained, the jitter of the second clock signal CLK2 can be reduced as compared with the conventional case. Accordingly, the digital DLL circuit 10 can delete the first and second counter circuits C1 and C2, and can reduce the circuit scale.

  As long as the delay elements of the second delay circuit 32 have the same configuration as the delay elements of the first delay circuit 21, the number of stages may be different from the number of stages of the delay elements of the first delay circuit 21. Even if it does in this way, the effect similar to said embodiment can be acquired.

  The phase adjustment circuit 31 generates a synchronization correction signal Srs of “0” or “1” for the first stage number data Ds1 according to the change in the data, and uses the synchronization correction signal Srs as the first stage number data Ds1. To the corrected first stage number data CDs1. That is, it is sufficient that the value of the corrected first stage number data CDs1 supplied to the multiplier 49 does not change. Therefore, for example, it includes a selection circuit to which the corrected first stage number data CDs1 obtained by adding “1” to the first stage number data Ds1 and the first stage number data Ds1 are supplied, and the change in the first stage number data Ds1. That is, the synchronization correction signal Srs or the first stage number data Ds1 may be supplied to the multiplier 49 based on the stage number decrease signal Sdn and the stage number increase signal Sup.

The following notes are disclosed regarding the above embodiments.
(Appendix 1)
A stage number data generation circuit for generating first stage number data indicating the number of stages of delay elements used to delay the reference clock signal to a predetermined phase;
Based on the first stage number data, second stage number data indicating the number of stages of delay elements to be used is generated, and the first clock signal is delayed by a delay element having the number of stages corresponding to the second stage number data, thereby generating a second clock signal. When the first stage number data is transitioned between two values, a signal generation circuit that performs correction according to a change in the first stage number data and generates the second stage number data,
A digital delay circuit comprising:
(Appendix 2)
The signal generation circuit includes:
Generating correction data according to a change in the first stage number data, adding the correction data to the first stage number data, and generating the second stage number data according to the addition result;
2. The digital delay circuit according to appendix 1, wherein:
(Appendix 3)
The stage number data generation circuit, when changing the stage number data, outputs a stage number change signal according to the change,
The signal generation circuit generates the correction data in response to the stage number change signal;
The digital delay circuit according to appendix 2, characterized by:
(Appendix 4)
The stage number data generation circuit generates a first stage number change signal when increasing the first stage number data, and generates a second stage number change signal when decreasing the first stage number data;
The signal generation circuit generates correction data of a first value based on the first stage number change signal, and has a second value that is one greater than the first value based on the second stage number change signal. Generating correction data,
The digital delay circuit according to any one of Appendices 1 to 3, characterized by:
(Appendix 5)
The stage number data generation circuit sets the phase difference between the corrected first stage number data generated by adding the correction data to the first stage number data and the phase difference between the first clock signal and the second clock signal. Generating the second stage number data based on:
The digital delay circuit according to any one of appendices 2 to 4, characterized in that:
(Appendix 6)
The stage number data generation circuit includes:
A phase comparison circuit that compares the phase of the reference clock signal with the reference clock signal delayed by the first stage number data and the phase of the reference clock signal, and outputs a phase comparison signal according to the comparison result;
A delay control circuit that changes the first stage number data according to the phase comparison signal;
Including
The delay control circuit includes:
Based on the phase comparison signal, it counts up when the phase of the comparison clock signal is larger than the delay of one cycle of the reference clock signal, and outputs the first stage number change signal according to the count value and the set value A first counter circuit that
Based on the phase comparison signal, it counts up when the phase of the comparison clock signal is smaller than the delay of one cycle of the reference clock signal, and outputs a second stage number change signal according to the count value and the set value A second counter circuit that
Have
Reducing the first stage number data in response to the first stage number change signal and increasing the first stage number data in response to the second stage number change signal;
The digital delay circuit according to any one of appendices 1 to 5, characterized in that:
(Appendix 7)
The delay element included in the stage number data generation circuit and the delay element included in the signal generation circuit have the same delay characteristics.
The digital delay circuit according to any one of appendices 1 to 6, characterized in that:
(Appendix 8)
A first delay circuit for generating a comparison clock signal by delaying a reference clock signal by a delay element having a number of stages based on the first stage number data;
A phase comparison circuit for comparing phases of the reference clock signal and the comparison clock signal;
A delay control circuit that generates the first stage number data so as to match the phases of the reference clock signal and the comparison clock signal based on a comparison result of the phase comparison circuit;
A phase adjustment circuit for generating second stage number data based on the first stage number data;
A second delay circuit for generating a second clock signal delayed from the first clock signal by the number of stages of delay elements based on the second stage number data,
The phase adjustment circuit
When the first stage number data transitions between two values, the digital delay circuit generates the second stage number data by performing correction according to a change in the first stage number data.
(Appendix 9)
First stage number data indicating the number of stages of delay elements used for delaying the reference clock signal to a predetermined phase is generated, and second stage number data indicating the number of stages of delay elements to be used is generated based on the first stage number data. When a first clock signal is delayed by a delay element having a number of stages corresponding to the second stage number data to generate a second clock signal, and the first stage number data is transitioned between two values, Performing the correction according to the change in the first stage number data to generate the second stage number data,
A method for controlling a digital delay circuit.

10 Digital delay circuit (Digital DLL circuit)
11-stage data generation circuit (master DLL circuit)
12 Signal generation circuit (slave DLL circuit)
CLK1 First clock signal CLK2 Second clock signal CLKr Reference clock signal Ds1 First stage number data Ds2 Second stage number data

Claims (6)

A stage number data generation circuit for generating first stage number data indicating the number of stages of delay elements used to delay the reference clock signal to a predetermined phase;
Based on the first stage number data, second stage number data indicating the number of stages of delay elements to be used is generated, and the first clock signal is delayed by a delay element having the number of stages corresponding to the second stage number data, thereby generating a second clock signal. When the first stage number data is transitioned between two values, a signal generation circuit that performs correction according to a change in the first stage number data and generates the second stage number data,
A digital delay circuit comprising: The signal generation circuit includes:
Generating correction data according to a change in the first stage number data, adding the correction data to the first stage number data, and generating the second stage number data according to the addition result;
The digital delay circuit according to claim 1. The stage number data generation circuit, when changing the stage number data, outputs a stage number change signal according to the change,
The signal generation circuit generates the correction data in response to the stage number change signal;
The digital delay circuit according to claim 2. The stage number data generation circuit generates a first stage number change signal when increasing the first stage number data, and generates a second stage number change signal when decreasing the first stage number data;
The signal generation circuit generates correction data of a first value based on the first stage number change signal, and has a second value that is one greater than the first value based on the second stage number change signal. Generating correction data,
The digital delay circuit according to any one of claims 1 to 3. The stage number data generation circuit sets the phase difference between the corrected first stage number data generated by adding the correction data to the first stage number data and the phase difference between the first clock signal and the second clock signal. Generating the second stage number data based on:
The digital delay circuit according to any one of claims 2 to 4, wherein First stage number data indicating the number of stages of delay elements used for delaying the reference clock signal to a predetermined phase is generated, and second stage number data indicating the number of stages of delay elements to be used is generated based on the first stage number data. When a first clock signal is delayed by a delay element having a number of stages corresponding to the second stage number data to generate a second clock signal, and the first stage number data is transitioned between two values, Performing the correction according to the change in the first stage number data to generate the second stage number data,
A method for controlling a digital delay circuit.

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