JP2011109818A - Voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an inrush current to a switched capacitor and an output smoothing capacitor when power is applied to a charge pump circuit. <P>SOLUTION: A DC/DC converter (2) converts a DC voltage from a DC power supply (1) by slow start where a voltage output is increased to a desired voltage level over a predetermined time. The charge pump circuit (3) boosts an output voltage from the DC/DC converter (2) so that the voltage level is doubled. The charge pump circuit (3) consists of MOS transistors (Q1-Q4), a switched capacitor (C1), and an output smoothing capacitor (C2). A drive circuit (4) controls switching of the MOS transistors (Q1-Q4) by a drive signal having a voltage level which increases gradually after starting operation of the charge pump circuit (3). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage generation circuit that generates another DC voltage from a DC voltage, and more particularly to a voltage generation circuit using a charge pump system.

JP 2003-219634 A

  As a conventional voltage generation circuit using a charge pump system, for example, as shown in FIG. 5, a double boost DC / DC converter is known. This DC / DC converter includes a charge pump circuit 101 that doubles the voltage, a drive circuit 102 that drives the charge pump circuit 101, and an output capacitor C5. The charge pump circuit 101 includes MOS transistors Q9 to Q12 and a capacitor C6. The drive circuit 102 controls on / off of the MOS transistors Q9 to Q12 at a timing defined by the output of the oscillation circuit 103.

  The operation of the conventional example shown in FIG. 5 will be described. MOS transistors Q9 and Q10 have parasitic diodes. When the power is turned on, the input DC voltage Vin suddenly charges the uncharged output capacitor C5 by the parasitic diodes of the MOS transistors Q9 and Q10. As a result, a large charging current flows through the output capacitor C5. At this time, since only the MOS transistors Q10 and Q12 are turned on, the input DC voltage Vin charges the capacitor C6 having almost no charge.

  Next, the drive circuit 102 turns on only the MOS transistors Q9 and Q11. As a result, a voltage obtained by adding the charging voltage of the capacitor C6 to the input DC voltage Vin is applied to the capacitor C5, and a larger charging current flows through the capacitor C5.

  Further, the drive circuit 102 turns off the MOS transistors Q9 and Q11 and simultaneously turns on the MOS transistors Q10 and Q12. As a result, the input DC voltage Vin is applied to the capacitor C6, and a relatively large charging current flows through the capacitor C6.

  Next, the drive circuit 102 turns off the MOS transistors Q10 and Q12 and simultaneously turns on the MOS transistors Q9 and Q11. As a result, a voltage obtained by adding the charging voltage of the capacitor C6 to the input DC voltage Vin is applied to the capacitor C5, and a larger charging current flows through the capacitor C5.

  Thereafter, by repeating these operations, the charging current of the capacitor C5 gradually decreases, and accordingly, the voltage between the terminals of the capacitor C5, that is, the output voltage Vout gradually increases, and finally input. The voltage becomes twice the DC voltage Vin.

  Thereafter, the charge pump circuit 102 charges the capacitor C6 to the input DC voltage Vin by turning on only the MOS transistors Q10 and Q12. Further, by turning off the MOS transistors Q10 and Q12 and simultaneously turning on the MOS transistors Q9 and Q11, the capacitor C5 is charged with a voltage obtained by adding the input DC voltage Vin to the charging voltage of the capacitor C6. By repeating this, the output voltage Vout is maintained at twice the input DC voltage Vin.

  As described above, in the conventional DC / DC converter, when the operation of the charge pump circuit is started, a large charging current, that is, an inrush current flows through the capacitor C6 and the output capacitor C5. This has a negative effect on the equipment. A method for reducing such inrush current is described in Patent Document 1. When the DC / DC converter is not operating, a precharge circuit is provided for precharging the capacitor C6 and the output capacitor C5. Specifically, as shown in FIG. 6, MOS transistors Q13 and Q14 are provided that can charge the capacitors C5 and C6, respectively, even when the charge pump circuit is inactive.

  In the DC / DC converter described in Patent Document 1, a precharge circuit for reducing the inrush current becomes a factor in increasing the cost and size of the device.

  An object of this invention is to show the voltage generation circuit which reduced the inrush current by simpler structure.

  A voltage generation circuit according to the present invention is a DC / DC converter that converts a DC voltage supplied from a DC power source into another voltage, a DC / DC converter that performs a slow start from a voltage output start, and the DC / DC A charge pump circuit that boosts the voltage of the input power supply by switching a plurality of switching elements using an output of the converter as an input power supply, a drive circuit that controls the plurality of switching elements of the charge pump circuit, and the drive circuit A start / stop control circuit for controlling the start and stop of the operation, supplying the output of the DC / DC converter to the power supply of the drive circuit, and paralleling the output of the DC / DC converter and the drive circuit To start operation of the charge pump circuit during a slow start period of the DC / DC converter. And wherein the door.

  A voltage generation circuit according to the present invention is a DC / DC converter that converts a DC voltage supplied from a DC power source into another voltage, a DC / DC converter that performs a slow start from a voltage output start, and the DC / DC A charge pump circuit that boosts the voltage of the input power supply by switching a plurality of switching elements using an output of the converter as an input power supply; and a drive circuit that controls the plurality of switching elements of the charge pump circuit, The output of the DC / DC converter is supplied to the power supply of the drive circuit, the output of the DC / DC converter is used as a control signal for controlling the start or stop of the operation of the charge pump circuit, and the slow start period of the DC / DC converter The operation of the charge pump circuit is started.

  In the present invention, since the operation of the charge pump circuit is started during the slow start period of the DC / DC converter, the inrush current at the start of the operation of the charge pump circuit can be made smaller than the conventional one.

It is a schematic block diagram of 1st Example of this invention. It is a timing chart which shows the operation example of 1st Example. It is a schematic block diagram of 2nd Example of this invention. It is a timing chart which shows the operation example of 2nd Example. It is a schematic block diagram of a prior art example. It is a schematic block diagram of another prior art example. It is a gate voltage-on-resistance characteristic of a MOS transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram of a voltage generation circuit according to an embodiment of the present invention. Reference numeral 1 denotes a DC power source such as a battery or an adapter. A DC / DC converter 2 converts a DC voltage supplied from the DC power source 1 into a desired DC voltage. The DC / DC converter 2 performs a slow start in which the voltage output is increased over a predetermined time from the voltage output start to a desired voltage. 3 is a charge pump circuit of double boosting. The charge pump circuit 3 includes a plurality of switching elements (MOS transistors Q1 to Q4), a switched capacitor C1, and an output smoothing capacitor C2. The charge pump circuit 3 receives the output of the DC / DC converter 2 as an input.

  A drive circuit 4 drives the transistors Q1 to Q4 of the charge pump circuit 3. An oscillation circuit 5 oscillates a signal supplied to the drive circuit 4. Reference numeral 6 denotes a start / stop control circuit that controls the start and stop of the operation of the DC / DC converter 2 and the charge pump circuit 3. Reference numerals 7 and 8 denote current limiting resistors.

  In the charge pump circuit 3, MOS transistors Q1 to Q4 are connected in series between the output line of the charge pump circuit 3 and GND, and an output smoothing capacitor C2 is connected in parallel. A predetermined drive signal (ON / OFF control signal) is applied from the drive circuit 4 to each gate of the MOS transistors Q1 to Q4. A switched capacitor C1 is connected between the common connection portion of the MOS transistors Q1 and Q2 and the common connection portion of the MOS transistors Q3 and Q4. The output of the DC / DC converter 2 is connected to a common connection between the MOS transistor Q2 and the MOS transistor Q3, and is connected to the power supply terminal of the drive circuit 4.

  The current limiting resistors 7 and 8 are connected in series between the input of the charge pump circuit 3 and GND. A common connection portion of the current limiting resistor 7 and the current limiting resistor 8 is connected to the control terminal CTL of the drive circuit 4 and is connected to the start / stop control circuit 6. The control signal output of the start / stop control circuit 6 is connected to the control terminal CTL of the DC / DC converter 2.

  FIG. 2 shows a timing chart of the DC / DC converter shown in FIG. S <b> 1 indicates a control signal for controlling the start or stop of the DC / DC converter 2. S2 indicates an output voltage of the DC / DC converter 2, and is also an input power supply voltage of the charge pump circuit 3 and the drive circuit 4. S <b> 3 indicates a control signal for the start / stop control circuit 6 to control the start or stop of the drive circuit 4. S4 indicates a control signal for controlling activation or deactivation of the drive circuit 2. S5 indicates a drive signal for MOS transistors Q2 and Q4. S6 indicates a drive signal for the MOS transistors Q1 and Q3. S7 indicates a voltage between both electrodes of the switched capacitor C1. S8 indicates the on resistance of the MOS transistors Q2 and Q4. S9 indicates the on resistance of the MOS transistors Q1 and Q3. S10 indicates the output voltage of the charge pump circuit 3.

  The operation of this embodiment will be described. When the DC power source 1 is connected and a start operation is performed from the outside, the start / stop control circuit 6 sends a start signal to the DC / DC converter 2 (T1 in FIG. 2). The DC / DC converter 2 performs a slow start in response to the activation signal, and increases the output voltage to a desired voltage value over a predetermined time (T1 to T7 in FIG. 2). At the same time, the input voltages of the charge pump circuit 3 and the drive circuit 4 rise at the same potential as the output voltage of the DC / DC converter 2. A voltage obtained by dividing the output of the DC / DC converter 2 by the current limiting resistors 7 and 8 is input to the drive circuit 4 as a start signal. Here, when a desired operation is not performed from the outside, the start / stop control circuit 6 controls the connection line to the drive circuit 4 for starting the charge pump circuit 3 to be open (T1 to T11 in FIG. 2). .

  When the DC / DC converter 2 outputs a voltage, the output smoothing capacitor C2 is charged by the parasitic diodes of the MOS transistors Q1 and Q2. However, in this embodiment, since the slow start is performed when the DC / DC converter 2 is started, the inrush current to the output smoothing capacitor C2 can be reduced.

  When the output voltage of the DC / DC converter 2 is applied to the power supply terminal VDD of the drive circuit 4 and the drive signal is applied to the control terminal CTL, the drive circuit 4 drives the MOS transistors Q2 and Q4 (on / off control). Signal) (T2 in FIG. 2). FIG. 7 shows the relationship between the gate voltage and the on-resistance of the MOS transistor. In FIG. 7, v1 indicates the minimum drive voltage of the MOS transistor. RDS1 indicates the on-resistance of the MOS transistor when the minimum driving voltage is applied to the gate. In general, when the voltage applied to the gate of the MOS transistor is higher than the minimum drive voltage v1, the on-resistance is reduced (v1 to v2 in FIG. 7). If it is higher than the drive voltage v2, the change in the on-resistance becomes a constant value.

  When the power supply voltage of the drive circuit 4 reaches the drive voltage of the MOS transistors Q2 and Q4 (T4 in FIG. 2), the MOS transistors Q2 and Q4 are turned on. Then, the switched capacitor C1 is charged up to the output voltage of the DC / DC converter 2 which is the input power source of the charge pump circuit 3. At this time, since the MOS transistors Q2 and Q4 are turned on with a low gate voltage, the on-resistances of the MOS transistors Q2 and Q4 are large, and therefore the inrush current to the switched capacitor C1 is small.

  Next, the drive circuit 4 turns off the MOS transistors Q2 and Q4 and simultaneously outputs a drive signal (on / off control signal) for driving the MOS transistors Q1 and Q3 (T3 in FIG. 2). When the power supply voltage of the drive circuit 4 reaches the drive voltage of the MOS transistors Q1 and Q3 (T5 in FIG. 2), the MOS transistors Q1 and Q3 are turned on. As a result, a voltage obtained by adding the charging voltage of the switched capacitor C1 to the output voltage of the DC / DC converter 2 is applied to the output smoothing capacitor C2. That is, the charge pump circuit 3 charges the output smoothing capacitor C2 with a voltage higher than the input voltage. At this time, since the MOS transistors Q1 and Q3 are turned on with a low gate voltage, the on-resistances of the MOS transistors Q1 and Q3 are large, and the inrush current to the output smoothing capacitor C2 is small.

  Subsequently, the drive circuit 4 turns off the MOS transistors Q1 and Q3 and simultaneously turns on the MOS transistors Q2 and Q4. Thereby, the switched capacitor C1 is charged with the output voltage of the DC / DC converter 2 (T6 in FIG. 2). Next, the drive circuit 4 turns off the MOS transistors Q2 and Q4 and simultaneously turns on the MOS transistors Q1 and Q3 (T7 in FIG. 2). As a result, again, a voltage obtained by adding the charging voltage of the switched capacitor C1 to the output voltage of the DC / DC converter 2 is applied to the output smoothing capacitor C2.

  When the MOS transistors Q2 and Q4 are turned on or the MOS transistors Q1 and Q3 are turned on after the second time, an inrush current can flow through the switched capacitor C1 and the output smoothing capacitor C2. However, the inrush current at this time is small because the first charged charge remains in the switched capacitor C1 and the output smoothing capacitor C2.

  Thereafter, by repeating these operations, the voltage of the output smoothing capacitor C2 gradually increases and finally becomes twice the output voltage of the DC / DC converter 2 (T8 in FIG. 2).

  When a stop operation is performed from the outside, the start / stop control circuit 6 sends a stop signal to the DC / DC converter 2 (T9 in FIG. 2). When the stop signal is input, the DC / DC converter 2 reduces the voltage output to the GND level (T9 to T10 in FIG. 2). At the same time, the input power supply voltage of the charge pump circuit 3 decreases with the output voltage of the DC / DC converter 2, and the output voltage of the charge pump circuit 3 also decreases.

  In some cases, the output of the DC / DC converter 2 is not stopped in response to an external stop operation, and only the output voltage of the charge pump circuit 3 is desired to be lowered. In such a case, the start / stop control circuit 6 controls the connection line to the drive circuit 4 for starting the charge pump circuit 3 to the GND level (T11 in FIG. 2). When the connection line to the drive circuit 4 is controlled to the GND level, the drive circuit 4 stops the control of the MOS transistors Q1 to Q4, that is, turns it off. As a result, the output voltage of the charge pump circuit 3 drops to the GND level (T11 to T12 in FIG. 2).

  In this embodiment, the output of the DC / DC converter 2 is connected to the power supply terminal and the control terminal of the drive circuit 4 of the charge pump circuit 3, and the charge pump circuit 3 is started to operate during the slow start period of the DC / DC converter 2. . Thereby, the inrush current to the switched capacitor C1 and the output smoothing capacitor C2 when the charge pump circuit 3 is started can be reduced.

  FIG. 3 shows a schematic block diagram of the second embodiment of the present invention. Reference numeral 11 denotes a DC power source such as a battery or an AC adapter. Reference numeral 12 denotes a two-channel output DC / DC converter that converts a DC voltage supplied from the DC power supply 11 into a desired DC voltage. The DC / DC converter 12 performs a slow start in which the output voltage is increased over a predetermined time from the voltage output start to a desired voltage. Reference numeral 13 denotes a charge pump circuit for double boosting. The charge pump circuit 13 includes MOS transistors Q5 to Q8, a switched capacitor C3, and an output smoothing capacitor C4, and operates using the first channel output of the DC / DC converter 12 as an input power supply.

  A drive circuit 14 drives the transistors Q5 to Q8 of the charge pump circuit 13. An oscillation circuit 15 oscillates a signal supplied to the driving circuit 14. Reference numeral 16 denotes a start / stop control circuit that controls the start and stop of the operation of the DC / DC converter 12 and the charge pump circuit 13. Reference numerals 17 and 18 denote current limiting resistors.

  In the charge pump circuit 13, MOS transistors Q5 to Q8 are connected in series between the output line 5 of the charge pump circuit 13 and GND, and an output smoothing capacitor C4 is connected in parallel. A predetermined drive signal (on / off control signal) is applied from the drive circuit 14 to the gates of the MOS transistors Q5 to Q8.

  A switched capacitor C3 is connected between the common connection portion of the MOS transistors Q5 and Q6 and the common connection portion of the MOS transistors Q7 and Q8. The first channel output 3 of the DC / DC converter 12 is connected to the common connection part of the MOS transistor Q6 and the MOS transistor Q7 and the power supply terminal VDD of the drive circuit.

  The current limiting resistors 17 and 18 are connected in series between the second channel output line 4 of the DC / DC converter 12 and GND. A common connection portion of the current limiting resistor 17 and the current limiting resistor 18 is connected to the control terminal CTL of the drive circuit 14 and the control signal output of the start / stop control circuit 16.

  The start / stop control circuit 16 is connected to the control terminals CTL of the first channel and the second channel of the DC / DC converter 12.

  FIG. 4 shows a timing chart of an operation example of the embodiment shown in FIG. S101 indicates a control signal for controlling the start and stop of the first channel of the DC / DC converter 12. S102 indicates the output voltage of the first channel of the DC / DC converter 12, and is also the input power supply voltage of the charge pump circuit 3. S103 indicates a control signal for controlling the start and stop of the second channel of the DC / DC converter 12. S104 indicates the output voltage of the DC / DC converter 12, and is also the input power supply voltage of the drive circuit 14. S105 indicates a control signal for controlling the start and stop of the drive circuit 14 output from the start / stop control circuit 16. S106 indicates a control signal for controlling the start and stop of the drive circuit 12. S107 indicates a drive signal (ON / OFF control signal) for the MOS transistors Q6 and Q8. S108 indicates a drive signal (ON / OFF control signal) for the MOS transistors Q5 and Q7. S109 indicates a voltage between both electrodes of the switched capacitor C3. S110 indicates the on-resistance of the MOS transistors Q6 and Q8. S111 indicates the on-resistance of the MOS transistors Q5 and Q7. S112 indicates the output voltage of the charge pump circuit 13.

  The operation of this embodiment will be described. It is assumed that the DC power source 11 is connected to the DC / DC converter 12 and an activation operation is performed from the outside. Then, the start / stop control circuit 16 sends a start signal to the first channel of the DC / DC converter 12 (T101 in FIG. 4). When the activation signal is input, the first channel of the DC / DC converter 12 performs a slow start and increases the output voltage to a desired voltage value over a predetermined time (T101 to T102 in FIG. 4). As the output voltage of the first channel of the DC / DC converter 12 increases, the input power supply voltage of the charge pump circuit 13 also increases.

  When the output voltage of the first channel of the DC / DC converter 12 rises to a desired voltage value, the start / stop control circuit 16 sends a start signal to the second channel of the DC / DC converter 12 (T102 in FIG. 4). In response to the input of the start signal, the second channel of the DC / DC converter 12 performs a slow start, and increases the output voltage to a desired voltage value over a certain time (T102 to T107 in FIG. 4).

  As the output voltage of the second channel of the DC / DC converter 12 increases, the input voltage of the power supply terminal VDD of the drive circuit 14 increases. A voltage obtained by dividing the output voltage of the second channel of the DC / DC converter 12 by the current limiting resistors 7 and 8 is applied to the control terminal CTL of the drive circuit 14 as an activation signal.

  Here, when a desired operation is not performed from the outside, the start / stop control circuit 16 controls the connection line to the drive circuit 14 for starting the charge pump circuit 13 to be open (T101 in FIG. 4). The output voltage of the second channel of the DC / DC converter 12 charges the output smoothing capacitor C4 via the parasitic diodes of the MOS transistors Q5 and Q6. In this embodiment, since the second channel of the DC / DC converter 12 performs a slow start at the time of startup, the inrush current to the output smoothing capacitor C4 can be reduced.

  The output voltage of the second channel of the DC / DC converter 12 is supplied to the power supply terminal VDD of the drive circuit 14, and the activation signal (the output voltage of the second channel of the DC / DC converter 12 is supplied to the control terminal CTL as current limiting resistors 17, 18). The voltage divided by is applied. Then, the drive circuit 14 outputs a drive signal (on / off control signal) to the MOS transistors Q6 and Q8 (T103 in FIG. 2). When the power supply voltage of the drive circuit 14 reaches the drive voltage of the MOS transistors Q6 and Q8 (T105 in FIG. 2), the MOS transistors Q6 and Q8 are turned on. In this state, the switched capacitor C3 is charged by the output voltage of the first channel of the DC / DC converter 12. Since the MOS transistors Q6 and Q8 are turned on at a low gate voltage, the on-resistances of the MOS transistors Q6 and Q8 are large, and the inrush current to the switched capacitor C3 is small.

  Next, the drive circuit 14 turns off the MOS transistors Q6 and Q8 and simultaneously turns on the MOS transistors Q5 and Q7 (T104 in FIG. 4). When the power supply voltage of drive circuit 14 reaches the drive voltage of MOS transistors Q5 and Q7 (T106 in FIG. 4), MOS transistors Q5 and Q7 are turned on. In this state, a voltage obtained by adding the charging voltage of the switched capacitor C3 to the output voltage of the first channel of the DC / DC converter 12 is applied to the output smoothing capacitor C4 to charge the output smoothing capacitor C4. Since the MOS transistors Q5 and Q7 are turned on at a low gate voltage, the on-resistances of the MOS transistors Q5 and Q7 are increased, and the inrush current to the output smoothing capacitor C4 is decreased.

  Next, the drive circuit 14 turns off the MOS transistors Q5 and Q7 and simultaneously turns on the MOS transistors Q6 and Q8. Thereby, the switched capacitor C3 is charged with the output voltage of the first channel of the DC / DC converter 12 (T108 in FIG. 4).

  The drive circuit 14 turns off the MOS transistors Q6 and Q8 and simultaneously turns on the MOS transistors Q5 and Q7 (T107 in FIG. 4). In this state, a voltage obtained by adding the charging voltage of the switched capacitor C3 to the output voltage of the first channel of the DC / DC converter 12 is applied to the output smoothing capacitor C4 to charge the output smoothing capacitor C4.

  When the MOS transistors Q5 and Q7 are turned on after the second time (or the MOS transistors Q6 and Q8 are turned on), charges remain in the switched capacitor C3 and the output smoothing capacitor C4. Therefore, the inrush current to the switched capacitor C3 and the output smoothing capacitor C4 is smaller than that in the conventional example.

  Thereafter, by repeating these operations, the output voltage of the output line 5 gradually increases, and finally becomes a voltage twice the output voltage of the first channel of the DC / DC converter 12 (FIG. 4). T107).

  When the stop operation of the charge pump circuit 13 is performed from the outside, the start / stop control circuit 16 sends a stop signal to the second channel of the DC / DC converter 12 (T109 in FIG. 4). With this stop signal, the second channel of the DC / DC converter 12 lowers the output voltage to the GND level (T109 to T110 in FIG. 4). In conjunction with a decrease in the output voltage of the second channel of the DC / DC converter 12, the voltages of the drive signals S107 and S108 decrease, and the output voltage (S112) of the charge pump circuit 13 also decreases.

When the charge pump circuit 13 is stopped from the outside, the output 4 of the second channel of the DC / DC converter 12 is not stopped and only the output voltage 5 of the charge pump circuit 13 is stopped. To do. That is, the start / stop control circuit 16 controls the connection line to the drive circuit 14 for starting the charge pump circuit 13 to the GND level (T111 to T112 in FIG. 4). As a result, the drive circuit 14 stops the operation of the charge pump circuit 13. As another method, the output voltage 5 of the charge pump circuit 13 may be stopped by stopping the first channel of the DC / DC converter 12 (T113 in FIG. 2).
In the second embodiment, the output of the second channel of the DC / DC converter 12 is connected to the start signal of the drive circuit 14 of the charge pump circuit 13. The output of the slowest channel among the plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit 13 of the DC / DC converter 12 is used as the power source of the charge pump circuit 3. Then, the operation of the charge pump circuit 13 is started during the slow start period of the DC / DC converter 12. Thereby, the inrush current to the switched capacitor C1 and the output smoothing capacitor C2 when the charge pump circuit 3 is started can be reduced. By starting the drive circuit 14 immediately before the voltage output start timing of the charge pump circuit 13, the standby current of the charge pump circuit 13 can be reduced.

Claims (9)

A DC / DC converter that converts a DC voltage supplied from a DC power source into another voltage, a DC / DC converter that performs a slow start from a voltage output start; and
A charge pump circuit that uses the output of the DC / DC converter as an input power supply and boosts the voltage of the input power supply by switching a plurality of switching elements;
A drive circuit for controlling the plurality of switching elements of the charge pump circuit;
A start / stop control circuit for controlling operation start and operation stop of the drive circuit;
The output of the DC / DC converter is supplied to the power supply of the drive circuit, and the output of the DC / DC converter and the drive circuit are connected in parallel, and the charge pump circuit is in a slow start period of the DC / DC converter. A voltage generation circuit characterized by starting operation. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
2. The voltage generation circuit according to claim 1, wherein an input power source of the charge pump circuit is a channel having a later voltage output start timing among the plurality of channels. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
3. The voltage generation circuit according to claim 1, wherein a power source of the driving circuit is a channel having a late voltage output start timing among the plurality of channels. 4. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
4. The output of the DC / DC converter connected in parallel with the drive circuit is a channel with a late voltage output start timing among the plurality of channels. Voltage generator circuit. 5. The voltage generation according to claim 1, wherein the drive circuit does not control operation start or operation stop of the drive circuit during a slow start period of the DC / DC converter. circuit. A DC / DC converter that converts a DC voltage supplied from a DC power source into another voltage, a DC / DC converter that performs a slow start from a voltage output start; and
A charge pump circuit that uses the output of the DC / DC converter as an input power supply and boosts the voltage of the input power supply by switching a plurality of switching elements;
A drive circuit for controlling the plurality of switching elements of the charge pump circuit,
The output of the DC / DC converter is supplied to the power supply of the drive circuit, and the output of the DC / DC converter is used as a control signal for controlling the start or stop of the operation of the charge pump circuit. A voltage generation circuit which starts operation of the charge pump circuit during a period. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
The voltage generation circuit according to claim 6, wherein an input power source of the charge pump circuit is a channel with a late voltage output start timing among the plurality of channels. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
8. The voltage generation circuit according to claim 6, wherein a power source of the drive circuit is a channel having a late voltage output start timing among the plurality of channels. 9. The DC / DC converter includes a plurality of channels that start voltage output before the voltage output start timing of the charge pump circuit,
7. The drive circuit generates a control signal for controlling the plurality of switching elements of the charge pump circuit from an output of a channel having a later voltage output start timing among the plurality of channels. 9. The voltage generation circuit according to claim 1.

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