JP2011108825A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a CMIS transistor, capable of reducing both the threshold voltage of a p-channel transistor and an n-channel transistor. <P>SOLUTION: The p-channel transistor has a first gate structure 150A formed on a first region in a semiconductor substrate 100 and a first spacer structure formed on a sidewall of a first gate structure 150A. The n-channel transistor has a second gate structure 150B formed on a second region in the semiconductor substrate 100 and a second spacer structure formed on a sidewall of the second gate structure 150B. The oxygen concentration in the contact portion to the sidewall of the first gate structure 150A in the first spacer structure is higher than the oxygen concentration in the contact portion to the sidewall of the second gate structure 150B in the second spacer structure. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a CMIS transistor and a manufacturing method thereof.

  2. Description of the Related Art As semiconductor integrated circuit devices have become highly integrated, highly functional, and high-speed in recent years, conventional silicon oxide films and poly-silicon films have been used as gate insulating films and gate electrodes constituting the gate structure of complementary metal insulator semiconductor (CMIS) transistors. A technique using a high dielectric constant oxide film and a metal-containing film (so-called high-k / metal structure) instead of a silicon film has been proposed.

  However, the high-k / polysilicon structure and the high-k / metal structure have a disadvantage that their interfaces and side surfaces are easily oxidized. For example, when a conventional offset spacer made of a silicon oxide film is used as the spacer structure provided on the side wall of the gate structure, fixed charges are generated at the interface and side surfaces of the gate structure, and the effective work function of the gate electrode changes. To do. As a result, the threshold voltage changes greatly in a short channel region (for example, a gate structure having a gate length of 100 nm or less) in which the influence of the gate end is significant. In addition, when a conventional offset spacer made of a silicon oxide film is used, there is a problem that the metal-containing film in the gate structure is oxidized.

  On the other hand, Non-Patent Document 1 and Patent Document 1 propose a technique that uses a non-oxidizing silicon nitride film as an offset spacer instead of a conventional silicon oxide film.

  On the other hand, a side wall spacer made of a silicon nitride film has been conventionally used as the spacer structure. However, this causes a relative increase in fringe capacity with miniaturization, and as a result, hinders improvement in driving capability. It is becoming a cause.

  On the other hand, Non-Patent Document 2 proposes a technique that uses a material having a dielectric constant lower than that of a silicon nitride film as a sidewall spacer material.

US Pat. No. 6,049,114

T. Watanabe et al., Impact of Hf Concentration on Performance and Reliability for HfSiON-CMOSFET, 2004 International Electron Devices Meeting, December 2004, p.507-510 C.H.Ko et al., A Novel CVD-SiBCN Low-K Spacer Technology for High-Speed Applications, 2008 Symposium on VLSI Technology Digest of Technical Papers, June 2008, p.108-109

  FIG. 6A shows a cross-sectional configuration of a conventional complementary metal oxide semiconductor (CMOS) transistor using an offset spacer made of a silicon oxide film. As shown in FIG. 6A, the semiconductor substrate 10 is partitioned into an NMOS region 10A and a PMOS region 10B by STI (shallow trench isolation) 11. A metal gate electrode 15A made of a metal-containing film is formed on the NMOS region 10B via a gate insulating film 14A made of a lower SiON film 12A and an upper high-k film 13A. A metal gate electrode 15B made of a metal-containing film is formed on the PMOS region 10B via a gate insulating film 14B made of a lower SiON film 12B and an upper high-k film 13B. Here, instead of the metal gate electrodes 15A and 15B, a multilayer gate electrode composed of a lower metal-containing film in contact with the gates 14A and 14B and an upper polysilicon film may be formed. An offset spacer 16A made of a silicon oxide film, an L-shaped side wall spacer 17A, and an LDD (lightly doped drain) side wall spacer 18A are sequentially formed on the side wall of the NMOS gate structure including the gate insulating film 14A and the metal gate electrode 15A. ing. An offset spacer 16B made of a silicon oxide film, an L-shaped side wall spacer 17B, and an LDD (lightly doped drain) side wall spacer 18B are sequentially formed on the side wall of the PMOS gate structure including the gate insulating film 14B and the metal gate electrode 15B. ing. An n-type LDD region 19A is formed below the spacer structure in the NMOS region 10A, and an n-type source / drain region 20A is formed outside the n-type LDD region 19A. A p-type LDD region 19B is formed below the spacer structure in the PMOS region 10B, and an n-type source / drain region 20B is formed outside the p-type LDD region 19B.

  When a silicon oxide film is used for the offset spacer as in the conventional CMOS transistor shown in FIG. 6A, negative fixed charges are generated at the interface and side surfaces of the gate structure as described above, and the gate electrode The effective work function of changes. FIG. 7A shows a work function (WF) before a fixed charge is generated in the gate structure, and FIG. 7B shows an effective work function after a negative fixed charge is generated in the gate structure (WF). eWF). 7A and 7B, PS is a polysilicon electrode, Metal is a metal electrode, HK is a high-k layer, IL is an interface layer, Si-sub is a silicon substrate, CB is a conduction band, and VB is Represents the valence band. As shown in FIG. 7B, when a negative fixed charge is generated in the gate structure, the effective work function usually increases. From the viewpoint of the threshold voltage, the absolute value of the threshold voltage increases in the n-channel transistor, which is disadvantageous, whereas the absolute value of the threshold voltage decreases in the p-channel transistor.

FIG. 8A shows a gate structure having a stacked structure of an interface layer and a high-k layer made of HfSiON, and a gate structure made of polysilicon (Poly-Si). In the figure, a negative fixed charge (Fix charge) is generated in the gate insulating film when an offset spacer (OSS) made of a silicon oxide film (SiO ₂ film) is formed. FIG. 8B shows the relationship between the gate length and the threshold voltage when the SiO ₂ film is used as the offset spacer of each of the n-channel transistor and the p-channel transistor. As shown in FIG. 8B, when the SiO ₂ film is used as the offset spacer, the absolute value of the threshold voltage is increased in the n-channel transistor, whereas the absolute value of the threshold voltage is decreased in the p-channel transistor. Yes.

  FIG. 6B shows a cross-sectional configuration of a conventional CMOS transistor using an offset spacer made of a silicon oxide film. In FIG. 6B, the same components as those in the conventional CMOS transistor shown in FIG. The conventional CMOS transistor shown in FIG. 6B is different from the conventional CMOS transistor shown in FIG. 6A on the sidewall of the NMOS gate structure composed of the gate insulating film 14A and the metal gate electrode 15A. Instead of the offset spacer 16A made of a silicon oxide film, an offset spacer 21A made of a non-oxidizing silicon nitride film is formed, and on the side wall of the PMOS gate structure made of the gate insulating film 14B and the metal gate electrode 15B, Instead of the offset spacer 16B made of a silicon oxide film, an offset spacer 21B made of a non-oxidizing silicon nitride film is formed.

  When a non-oxidizing silicon nitride film is used for the offset spacer as in the conventional CMOS transistor shown in FIG. 6B, the interface or side surface of the gate structure is compared with the case where a silicon oxide film is used. ) A relatively positive fixed charge is generated, and the effective work function of the gate electrode changes. FIG. 7A shows a work function (WF) before a fixed charge is generated in the gate structure, and FIG. 7C shows an effective work function after a positive fixed charge is generated in the gate structure (WF). eWF). 7A and 7C, PS is a polysilicon electrode, Metal is a metal electrode, HK is a high-k layer, IL is an interface layer, Si-sub is a silicon substrate, CB is a conduction band, and VB is Represents the valence band. As shown in FIG. 7C, when a positive fixed charge is generated in the gate structure, the effective work function usually decreases. From the viewpoint of the threshold voltage, the n-channel transistor is advantageous because the absolute value of the threshold voltage is decreased, whereas the p-channel transistor is disadvantageous because the absolute value of the threshold voltage is increased.

  FIG. 8B shows the relationship between the gate length and the threshold voltage when SiN films are used for the offset spacers of the n-channel transistor and the p-channel transistor. As shown in FIG. 8B, when the SiN film is used for the offset spacer, the absolute value of the threshold voltage is decreased in the n-channel transistor, whereas the absolute value of the threshold voltage is increased in the p-channel transistor. .

  From the viewpoint of fringe capacitance, if a silicon nitride film is used instead of a silicon oxide film as an offset spacer, the capacitance increases due to the higher dielectric constant of the silicon nitride film than that of the silicon oxide film. The demerit of doing so occurs.

  In view of the above, an object of the present invention is to provide a semiconductor device having a CMIS transistor capable of reducing both threshold voltages of a p-channel transistor and an n-channel transistor, and a method for manufacturing the same.

  As a result of various studies to achieve the above object, the inventors of the present application have used an oxide insulating film such as a silicon oxide film as a spacer structure material in a portion in contact with the gate structure side wall of the p-channel transistor. On the other hand, the inventors have devised an invention in which a non-oxidizing insulating film such as a silicon nitride film is used as a spacer structure material in a portion in contact with the gate structure side wall of the n-channel transistor.

  That is, a semiconductor device according to the present invention has a first gate structure formed on a first region in a semiconductor substrate and a first spacer structure formed on a side wall of the first gate structure. an n-channel transistor having a p-channel transistor, a second gate structure formed on a second region of the semiconductor substrate, and a second spacer structure formed on a sidewall of the second gate structure; The oxygen concentration in the contact portion with the side wall of the first gate structure in the first spacer structure is the oxygen content in the contact portion with the side wall of the second gate structure in the second spacer structure. Higher than concentration.

  According to the semiconductor device of the present invention, since the oxygen concentration (specifically, atomic% of oxygen: hereinafter the same) of the spacer structure in the portion in contact with the gate structure side wall of the p-channel transistor is high, the effective work function of the gate electrode Can be increased, so that the absolute value of the threshold voltage of the p-channel transistor can be decreased. Further, since the concentration of oxygen contained in the spacer structure in the portion contacting the side wall of the gate structure of the n-channel transistor is low, the effective work function of the gate electrode can be reduced, so that the absolute value of the threshold voltage of the n-channel transistor is reduced. be able to. Therefore, it is possible to provide a semiconductor device having a CMIS transistor in which the threshold voltage of the p-channel transistor and the n-channel transistor is reduced to improve the driving capability.

  In the semiconductor device according to the present invention, the first spacer structure includes a first offset spacer in contact with a sidewall of the first gate structure, and the second spacer structure is a sidewall of the second gate structure. And a second offset spacer made of an insulating film different from the first offset spacer. In this case, the first spacer structure includes another offset spacer formed on the side wall of the first gate structure via the first offset spacer and made of the same insulating film as the second offset spacer. Further, it may be included. Alternatively, the second spacer structure may further include another offset spacer formed on the sidewall of the second gate structure via the second offset spacer and made of the same insulating film as the first offset spacer. May be included. The width of each of the first offset spacer and the second offset spacer is not particularly limited, but is preferably 5 nm or more from the viewpoint of the threshold voltage reduction effect, and from the viewpoint of miniaturization. Is preferably 10 nm or less.

  In the semiconductor device according to the present invention, the first spacer structure includes an offset spacer that is in contact with a sidewall of the first gate structure, and the second spacer structure is in contact with a sidewall of the second gate structure; Sidewall spacers made of an insulating film different from the offset spacers may be included. In this case, the first spacer structure further includes another sidewall spacer formed on the sidewall of the first gate structure via the offset spacer and made of the same insulating film as the sidewall spacer. Also good. In the semiconductor device according to the present invention, the first spacer structure includes a sidewall spacer in contact with a sidewall of the first gate structure, and the second spacer structure is a sidewall of the second gate structure. And an offset spacer made of an insulating film different from the sidewall spacer. In this case, the second spacer structure further includes another sidewall spacer formed on the sidewall of the second gate structure via the offset spacer and made of the same insulating film as the sidewall spacer. Also good. The width of the offset spacer is not particularly limited, but is preferably 5 nm or more from the viewpoint of the threshold voltage reduction effect, and is preferably 10 nm or less from the viewpoint of miniaturization. The sidewall spacer may be an L-shaped sidewall spacer, an LDD sidewall spacer, or a laminated sidewall spacer formed in the order of an L-shaped sidewall spacer and an LDD sidewall spacer. Good.

  In the semiconductor device according to the present invention, the contact portion of the first spacer structure with the side wall of the first gate structure may be composed of a silicon oxide film or a silicon oxynitride film. In this way, it is possible to reliably increase the effective work function of the gate electrode of the p-channel transistor, thereby reliably reducing the absolute value of the threshold voltage of the p-channel transistor. In the semiconductor device according to the present invention, the contact portion of the second spacer structure with the side wall of the second gate structure may be a silicon nitride film or a low low relative dielectric constant less than 8 that does not substantially contain oxygen. You may be comprised from the dielectric constant insulating film. In this way, it is possible to reliably reduce the effective work function of the gate electrode of the n-channel transistor, thereby reliably reducing the absolute value of the threshold voltage of the n-channel transistor. In this case, the low dielectric constant insulating film may be a SiC film, a BN film, a SiBCN film, or a SiBN film. In the semiconductor device according to the present invention, as a whole CMIS, the use of a material having a high relative dielectric constant for the spacer structure is minimized, or the use of a low dielectric constant material for the spacer structure is promoted. As a result, the drive capability can be improved while suppressing the fringe capacity.

  In the semiconductor device according to the present invention, each of the first gate structure and the second gate structure may include a high dielectric constant insulating film and a metal-containing film formed on the high dielectric constant insulating film. Good.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first gate structure and a second gate structure on each of a p-channel transistor formation region and an n-channel transistor formation region in a semiconductor substrate; Forming a first spacer structure and a second spacer structure on respective sidewalls of the first gate structure and the second gate structure, and the first spacer structure in the first spacer structure. The oxygen concentration in the contact portion with the side wall of the first gate structure is higher than the oxygen concentration in the contact portion with the side wall of the second gate structure in the second spacer structure.

  According to the method for manufacturing a semiconductor device according to the present invention, the effective work function of the gate electrode can be increased because the concentration of oxygen contained in the spacer structure in the portion in contact with the side wall of the gate structure of the p-channel transistor is high. The absolute value of the threshold voltage of the transistor can be reduced. Further, since the concentration of oxygen contained in the spacer structure in the portion contacting the side wall of the gate structure of the n-channel transistor is low, the effective work function of the gate electrode can be reduced, so that the absolute value of the threshold voltage of the n-channel transistor is reduced. be able to. Therefore, it is possible to provide a semiconductor device having a CMIS transistor in which the threshold voltage of the p-channel transistor and the n-channel transistor is reduced to improve the driving capability. The order in which the gate structures of the transistors are formed is not particularly limited. For example, the gate structures of the transistors may be formed at the same time using the same material for the gate insulating film and the gate electrode of each transistor.

  In the method of manufacturing a semiconductor device according to the present invention, the spacer forming step includes a step of forming a first offset spacer in contact with a side wall of the first gate structure, a side wall of the second gate structure, and the step of forming the spacer. Forming a second offset spacer made of an insulating film different from the first offset spacer. Here, the formation order of each offset spacer is not particularly limited, and the second offset spacer may be formed after the first offset spacer is formed, or the second offset spacer is formed. A first offset spacer may be formed. In addition, after forming the first offset spacer and forming another offset spacer which is in contact with the side wall of the second gate structure and made of the same insulating film as the first offset spacer, the other offset spacer is formed. After the selective removal, the second offset spacer is formed, and at the same time, the second offset spacer is formed on the side wall of the first gate structure with the same insulating film as the second offset spacer through the first offset spacer. An offset spacer may be formed. Here, the other offset spacer formed on the side wall of the first gate structure may be further removed. Alternatively, after forming the second offset spacer and forming another offset spacer which is in contact with the side wall of the first gate structure and made of the same insulating film as the second offset spacer, the other offset spacer is After the selective removal, the first offset spacer is formed, and at the same time, the second offset spacer is formed on the side wall of the second gate structure through the second offset spacer and made of the same insulating film as the first offset spacer. An offset spacer may be formed. Here, the other offset spacer formed on the side wall of the second gate structure may be further removed. Further, the spacer forming step includes a step of forming a first sidewall spacer on the sidewall of the first gate structure via the first offset spacer, and a step of forming the spacer on the sidewall of the second gate structure. Forming a second sidewall spacer via a second offset spacer. Here, each of the first sidewall spacer and the second sidewall spacer may include an L-shaped sidewall spacer, and the first sidewall spacer and the second sidewall spacer may be included. After forming the L-shaped sidewall spacer and the LDD sidewall spacer sequentially, the LDD sidewall spacers may be removed.

  In the method of manufacturing a semiconductor device according to the present invention, the spacer forming step includes a step of forming an offset spacer in contact with a side wall of the first gate structure, a side wall of the second gate structure, and the offset spacer. A step of forming sidewall spacers made of different insulating films. In this case, after forming the offset spacer, another offset spacer which is in contact with the side wall of the second gate structure and is made of the same insulating film as the offset spacer is formed, and then the other offset spacer is selectively removed. Thereafter, at the same time as forming the sidewall spacer, another sidewall spacer made of the same insulating film as the sidewall spacer may be formed on the sidewall of the first gate structure via the offset spacer. Further, in the method of manufacturing a semiconductor device according to the present invention, the spacer forming step includes a step of forming a sidewall spacer in contact with the side wall of the first gate structure, a side wall of the second gate structure, and the step of forming the spacer. A step of forming an offset spacer made of an insulating film different from the sidewall spacer. In this case, after forming the offset spacer, another offset spacer which is in contact with the side wall of the first gate structure and is made of the same insulating film as the offset spacer is formed, and then the other offset spacer is selectively removed. Thereafter, at the same time as forming the sidewall spacer, another sidewall spacer made of the same insulating film as the sidewall spacer may be formed on the sidewall of the second gate structure via the offset spacer. The sidewall spacer and the other sidewall spacer may each include an L-shaped sidewall spacer, and the sidewall spacer and the other sidewall spacer may be an L-shaped sidewall spacer and an LDD side wall, respectively. After sequentially forming the wall spacers, the LDD sidewall spacers may be removed.

  According to the semiconductor device of the present invention, a semiconductor device having a high-performance CMIS transistor capable of reducing both the threshold voltages of the p-channel transistor and the n-channel transistor can be obtained.

  Further, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to provide the above-described semiconductor device that is excellent not only in performance but also in terms of workability.

FIGS. 1A to 1D are cross-sectional views illustrating respective steps of the method for manufacturing a semiconductor device according to the first embodiment. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment. 3A to 3D are cross-sectional views of the semiconductor device according to the modification of the first embodiment. 4A to 4D are cross-sectional views illustrating respective steps of the method for manufacturing a semiconductor device according to the second embodiment. FIGS. 5A to 5D are cross-sectional views of semiconductor devices according to modifications of the second embodiment. 6A and 6B are cross-sectional views of a conventional semiconductor device. FIG. 7A is a diagram showing a work function (WF) before a fixed charge is generated in the gate structure, and FIG. 7B is a graph showing the effective after the negative fixed charge is generated in the gate structure. FIG. 7C is a diagram showing the work function (eWF), and FIG. 7C is a diagram showing the effective work function (eWF) after positive fixed charges are generated in the gate structure. FIG. 8A shows a gate structure having a stacked structure of an interface layer and a high-k layer made of HfSiON, and a gate structure made of polysilicon (Poly-Si). FIG. 8B is a diagram showing a state where negative fixed charges (Fix charge) are generated in the gate insulating film when an offset spacer (OSS) made of a silicon oxide film (SiO ₂ film) is formed; ) Is a diagram showing the relationship between the gate length and the threshold voltage when a SiO ₂ film and a SiN film are used for the offset spacers of the n-channel transistor and the p-channel transistor, respectively.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 1A to 1D are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the first embodiment.

  First, as shown in FIG. 1A, an element isolation region 101 having an STI structure, for example, is formed on a semiconductor substrate 100, whereby an n-channel transistor formation region (hereinafter referred to as an nMIS region) 100A and a p-channel transistor formation region ( (Hereinafter referred to as pMIS region) 100B. Next, a gate electrode 105A made of a lower metal-containing film and an upper polysilicon film is formed on the nMIS region 100A through a gate insulating film 104A made of a lower interface layer 102A and an upper high-k layer 103A. In addition, a gate electrode 105B made of a lower metal-containing film and an upper polysilicon film is formed on the pMIS region 100B via a gate insulating film 104B made of a lower interface layer 102B and an upper high-k layer 103B. To do. Specifically, on the semiconductor substrate 100, for example, a silicon oxide film that becomes the interface layers 102A and 102B, a high dielectric constant insulating film (eg, HfSiON film) that becomes the high-k layers 103A and 103B, a metal-containing film, and polysilicon After sequentially forming the films, etching is performed on the films stacked as described above using a mask pattern that covers the gate formation regions of the n-channel transistor and the p-channel transistor. As a result, the gate structure 150A of the n-channel transistor including the gate insulating film 104A and the gate electrode 105A is formed, and the gate structure 150B of the p-channel transistor including the gate insulating film 104B and the gate electrode 105B is formed.

  Next, after depositing an oxide film (a film having a high oxygen concentration (specifically, oxygen atomic%)) such as a silicon oxide film over the entire surface of the semiconductor substrate 100, the silicon oxide film is then deposited. Etch back. As a result, as shown in FIG. 1A, oxidative offset spacers 106A and 106B made of a silicon oxide film are formed on the side walls of the gate structures 150A and 150B.

  In this state, since the spacer structure in contact with each of the gate structure 150A of the n-channel transistor and the gate structure 150B of the p-channel transistor is formed of an oxide film, a heat treatment such as a subsequent impurity activation annealing step is performed. , The side surfaces and interfaces of the gate structures 150A and 150B are oxidized. As a result, the effective work function of the gate electrode generally increases, so that the absolute value of the threshold voltage decreases in the p-channel transistor, which is advantageous, whereas the absolute value of the threshold voltage increases in the n-channel transistor, which is disadvantageous. .

  Therefore, in this embodiment, in order to make the spacer structure in contact with the gate structure 150A of the n-channel transistor non-oxidizing, as shown in FIG. 1A, the oxidation on the gate structure 150B and its sidewalls is performed. After selectively covering the pMIS region 100B including the oxidative offset spacer 106B with the photoresist 107, as shown in FIG. 1B, the oxidative offset spacer 106A on the sidewall of the gate structure 150A of the n-channel transistor is selectively selected. Then, the photoresist 107 is removed.

  In the present embodiment, the side surface and the interface of the gate structure 150A of the n-channel transistor are oxidized depending on the atmosphere at the time of depositing the oxide film to be the oxidizing offset spacers 106A and 106B and the atmosphere at the time of removing the photoresist 107. Therefore, there is a concern that the effective work function of the gate electrode is increased, thereby causing a demerit that the absolute value of the threshold voltage of the n-channel transistor slightly increases. However, compared with the disadvantages that occur when the spacer structure in contact with the gate structure 150A of the p-channel transistor remains an oxide film at the time of performing a heat treatment such as a subsequent impurity activation annealing step, As in the embodiment, the demerit caused by removing the oxidizing offset spacer 106A, that is, the oxide film, on the sidewall of the gate structure 150A of the p-channel transistor is small.

  Next, after depositing a non-oxidizing film (a film having a low oxygen concentration), such as a silicon nitride film, over the entire surface of the semiconductor substrate 100, the silicon nitride film is etched back. As a result, as shown in FIG. 1C, a non-oxidizing offset spacer 108A made of a silicon nitride film is formed on the sidewall of the gate structure 150A of the n-channel transistor, and the sidewall of the gate structure 150B of the p-channel transistor. A non-oxidizing offset spacer 108B made of a silicon nitride film is formed thereon via an oxidizing offset spacer 106B.

  In this state, the spacer structure in the portion in contact with the gate structure 150A of the n-channel transistor can be made non-oxidizing and the spacer structure in the portion in contact with the gate structure 150B of the p-channel transistor can be made oxidizing. The threshold voltage of each of the transistor and the p-channel transistor can be lowered.

  Next, the pMIS region 100B including the gate structure 150B and the oxidizing offset spacer 106B and the non-oxidizing offset spacer 108B on the sidewall thereof is selectively covered with a photoresist (not shown), and then the gate structure 150A and the sidewall thereof. As shown in FIG. 1D, an n-type LDD region 111A is formed by ion-implanting n-type impurities into the nMIS region 100A using the non-oxidizing offset spacer 108A as a mask. Further, after selectively covering the nMIS region 100A including the gate structure 150A and the non-oxidizing offset spacer 108A on the sidewall thereof with a photoresist (not shown), the gate structure 150B and the oxidizing offset spacer 106B on the sidewall and Using the non-oxidizing offset spacer 108B as a mask, p-type impurities are ion-implanted into the pMIS region 100B, thereby forming a p-type LDD region 111B as shown in FIG.

  Next, as shown in FIG. 1D, an L-shaped sidewall spacer 109A and an LDD sidewall spacer 110A are sequentially formed on the sidewall of the gate structure 150A via a non-oxidizing offset spacer 108A, and the gate structure On the side wall of 150B, an L-shaped sidewall spacer 109B and an LDD sidewall spacer 110B are sequentially formed via an oxidizing offset spacer 106B and a non-oxidizing offset spacer 108B. That is, the spacer structure formed on the sidewall of the gate structure 150A of the n-channel transistor includes the non-oxidizing offset spacer 108A, the L-shaped sidewall spacer 109A, and the LDD sidewall spacer 110A. The spacer structure formed on the side wall includes an oxidizing offset spacer 106B, a non-oxidizing offset spacer 108B, an L-shaped side wall spacer 109B, and an LDD side wall spacer 110B.

  Next, the pMIS region 100B including the gate structure 150B and the spacer structure on the sidewall thereof is selectively covered with a photoresist (not shown), and then the nMIS region 100A using the gate structure 150A and the spacer structure on the sidewall as a mask. An n-type impurity is ion-implanted to form an n-type source / drain region 112A as shown in FIG. In addition, after selectively covering the nMIS region 100A including the gate structure 150A and the spacer structure on the side wall with a photoresist (not shown), the pMIS region 100B is formed using the gate structure 150B and the spacer structure on the side wall as a mask. By implanting p-type impurities, p-type source / drain regions 112B are formed as shown in FIG.

  Finally, activation annealing for activating the implanted impurities in the LDD regions 111A and 111B and the source / drain regions 112A and 112B is performed.

  According to the present embodiment described above, the spacer structure in contact with the side wall of the gate structure 150B of the p-channel transistor, that is, the oxidizable offset spacer 106B is oxidizable (that is, the oxygen concentration is high). Since the effective work function can be increased, the absolute value of the threshold voltage of the p-channel transistor can be decreased. In addition, since the spacer structure in contact with the sidewall of the gate structure 150A of the n-channel transistor, that is, the non-oxidizing offset spacer 108A has non-oxidizing properties (that is, the oxygen concentration is low), the effective work function of the gate electrode is reduced. Therefore, the absolute value of the threshold voltage of the n-channel transistor can be reduced. Therefore, it is possible to provide a semiconductor device having a CMIS transistor in which the threshold voltage of the p-channel transistor and the n-channel transistor is reduced to improve the driving capability.

  In this embodiment, the spacer structure formed on the side wall of the gate structure 150B of the p-channel transistor has a structure in which an oxidative offset spacer 106B and a non-oxidative offset spacer 108B are stacked. However, when a silicon nitride film having a high relative dielectric constant is used for the non-oxidizing offset spacer 108B, the fringe capacity increases, which is disadvantageous in terms of driving capability. Therefore, after forming the non-oxidizing offset spacers 108A and 108B as shown in FIG. 1C, the gate structure 150A and the non-oxidizing offset spacers 108A on the side walls thereof are formed as shown in FIG. After selectively covering the included nMIS region 100A with the photoresist 121, as shown in FIG. 2B, the non-oxidizing offset spacer 108B on the sidewall of the gate structure 150B may be selectively removed. Thereafter, after removing the photoresist 121, a semiconductor device shown in FIG. 2C can be obtained by performing a process similar to the process shown in FIG.

  In addition, in the semiconductor device of this embodiment shown in FIG. 1D, after impurity activation annealing, for example, to strengthen stress application by a stress liner film, as shown in FIG. The LDD sidewall spacers 110A on the sidewalls may be removed and the LDD sidewall spacers 110B on the sidewalls of the gate structure 150B may be removed. Similarly, in the semiconductor device according to the modification of the present embodiment shown in FIG. 2C, the LDD sidewall spacer 110A on the side wall of the gate structure 150A is removed and the gate structure is removed as shown in FIG. The LDD sidewall spacer 110B on the 150B sidewall may be removed.

  Further, in this embodiment, after the oxide offset spacer 106A on the sidewall of the gate structure 150A of the n-channel transistor is selectively removed in the step shown in FIG. 1B, the step shown in FIG. Then, non-oxidizing offset spacers 108A and 108B were deposited on the respective sidewalls of the gate structures 150A and 150B. However, instead of performing the deposition process of the non-oxidizing offset spacers 108A and 108B shown in FIG. 1C, as shown in FIG. 3C, on the sidewall of the gate structure 150A of the n-channel transistor. In addition, a non-oxidizing L-shaped sidewall spacer 109A and an LDD sidewall spacer 110A are sequentially formed, and an L-shaped side spacer is formed on the sidewall of the gate structure 150B of the p-channel transistor via the oxidizing offset spacer 106B. The wall spacer 109B and the LDD sidewall spacer 110B may be sequentially formed. In this case, for example, after the impurity activation annealing, the LDD sidewall spacer 110A on the side wall of the gate structure 150A is removed and the LDD side wall on the side wall of the gate structure 150B, for example, for strengthening stress application by a stress liner film. The spacer 110B may be removed. Alternatively, the non-oxidizing offset spacers 108A and 108B shown in FIG. 1C can be formed on the sidewall of the gate structure 150A of the n-channel transistor as shown in FIG. In addition, the LDD sidewall spacer 110B may be formed on the sidewall of the gate structure 150B of the p-channel transistor via the oxidizing offset spacer 106B. That is, the formation of the L-shaped sidewall spacers 109A and 109B may be omitted.

  As described above, there are various variations in the spacer structure that achieves the same effect as in the present embodiment. However, the selection of the configuration of the present embodiment or the configuration of any one of the variations is difficult for a process such as ion implantation. Etc. are taken into consideration.

  In the present embodiment, the widths of the oxidizing offset spacers 106A and 106B and the non-oxidizing offset spacers 108A and 108B are not particularly limited, but are 5 nm or more from the viewpoint of the effect of reducing the threshold voltage. From the viewpoint of miniaturization, it is preferably 10 nm or less.

  In this embodiment, silicon oxide films are used as the oxidative offset spacers 106A and 106B. However, other oxygen-containing insulating films such as silicon oxynitride films may be used instead.

  In this embodiment, silicon nitride films are used as the non-oxidizing offset spacers 108A and 108B. Instead, the oxygen concentration is lower than that of the oxidizing offset spacers 106A and 106B, or oxygen is substantially contained. Other insulating films not included may be used. In particular, from the viewpoint of reducing the fringe capacity, it is preferable to use a low dielectric constant insulating film that does not substantially contain oxygen and has a relative dielectric constant of less than 8, such as a SiC film, a BN film, a SiBCN film, or a SiBN film. In addition, when the non-oxidizing L-shaped side wall spacer 109A or the LDD side wall spacer 110A is used as the spacer structure in contact with the side wall of the gate structure 150A of the n-channel transistor (see FIGS. 3C and 3D). Needless to say, a silicon nitride film or the above-described low dielectric constant insulating film or the like may be used as these sidewall spacers. Furthermore, in the semiconductor device of the present embodiment, as a whole CMIS, the use of a material having a high relative dielectric constant for the spacer structure is minimized, or the use of a low dielectric constant material for the spacer structure is promoted. As a result, the drive capability can be improved while suppressing the fringe capacity.

  In this embodiment, the gate electrodes 105A and 105B have a laminated structure including a lower metal-containing film and an upper polysilicon film. However, it goes without saying that the structures of the gate electrodes 105A and 105B are not particularly limited. For example, different materials may be used for the gate electrode 105A of the n-channel transistor and the gate electrode 105B of the p-channel transistor. The same applies to the gate insulating films 104A and 104B. Further, the order of forming the gate structures 150A and 150B of the transistors is not particularly limited. For example, the same material is used for the gate insulating films 104A and 104B and the gate electrodes 105A and 105B of the transistors as in the present embodiment. May be used, the gate structures 150A and 150B of each transistor may be formed simultaneously.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, as a spacer structure of each transistor, an oxidizing offset spacer is formed and then a non-oxidizing offset spacer is formed. On the other hand, in this embodiment, the non-oxidizing offset spacer is formed as the spacer structure of each transistor, and then the oxidizing offset spacer is formed.

  4A to 4D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the second embodiment.

  First, as shown in FIG. 4A, an element isolation region 201 having an STI structure, for example, is formed on a semiconductor substrate 200, whereby an n-channel transistor formation region (hereinafter referred to as an nMIS region) 200A and a p-channel transistor formation region ( (Hereinafter referred to as pMIS region) 200B. Next, a gate electrode 205A made of a lower metal-containing film and an upper polysilicon film is formed on the nMIS region 200A via a gate insulating film 204A made of a lower interface layer 202A and an upper high-k layer 203A. In addition, a gate electrode 205B made of a lower metal-containing film and an upper polysilicon film is formed on the pMIS region 200B via a gate insulating film 204B made of a lower interface layer 202B and an upper high-k layer 203B. To do. Specifically, on the semiconductor substrate 200, for example, a silicon oxide film that becomes the interface layers 202A and 202B, a high dielectric constant insulating film (eg, HfSiON film) that becomes the high-k layers 203A and 203B, a metal-containing film, and polysilicon After sequentially forming the films, etching is performed on the films stacked as described above using a mask pattern that covers the gate formation regions of the n-channel transistor and the p-channel transistor. Thus, an n-channel transistor gate structure 250A composed of the gate insulating film 204A and the gate electrode 205A is formed, and a p-channel transistor gate structure 250B composed of the gate insulating film 204B and the gate electrode 205B is formed.

  Next, after depositing a non-oxidizing film (a film having a low oxygen concentration (specifically, oxygen atomic%)) such as a silicon nitride film over the entire surface of the semiconductor substrate 200, the silicon nitride film is formed. Etch back is performed. As a result, as shown in FIG. 4A, non-oxidizing offset spacers 206A and 206B made of a silicon nitride film are formed on the side walls of the gate structures 250A and 250B, respectively.

  In this state, the spacer structure in contact with each of the gate structure 250A of the n-channel transistor and the gate structure 250B of the p-channel transistor is composed of the non-oxidizing film. In the heat treatment, the side surfaces and interfaces of the gate structures 250A and 250B are reduced. This generally reduces the effective work function of the gate electrode, so that the absolute value of the threshold voltage decreases in the n-channel transistor, which is advantageous, but the absolute value of the threshold voltage increases in the p-channel transistor, which is disadvantageous. .

  Therefore, in this embodiment, in order to make the spacer structure in contact with the gate structure 250B of the p-channel transistor oxidizable, as shown in FIG. After selectively covering the nMIS region 200A including the conductive offset spacer 206A with the photoresist 207, the non-oxidizing offset spacer 206B on the sidewall of the gate structure 250B of the p-channel transistor is selected as shown in FIG. 4B. Then, the photoresist 207 is removed.

  Next, an oxide film (a film having a high oxygen concentration), for example, a silicon oxide film is deposited over the entire surface of the semiconductor substrate 200, and then the silicon oxide film is etched back. As a result, as shown in FIG. 4C, an oxidizing offset spacer 208A made of a silicon oxide film is formed on the sidewall of the gate structure 250A of the n-channel transistor via the non-oxidizing offset spacer 206A. An oxidizing offset spacer 208B made of a silicon oxide film is formed on the side wall of the gate structure 250B of the channel transistor.

  In this state, the spacer structure in contact with the gate structure 250A of the n-channel transistor can be made non-oxidizing, and the spacer structure in contact with the gate structure 250B of the p-channel transistor can be made oxidizing. The threshold voltage of each of the transistor and the p-channel transistor can be lowered.

  Next, after selectively covering the pMIS region 200B including the gate structure 250B and the oxidizable offset spacer 208B on the sidewall thereof with a photoresist (not shown), the gate structure 250A and the non-oxidized offset spacer 206A on the sidewall thereof. Then, using the oxidative offset spacer 208A as a mask, n-type impurities are ion-implanted into the nMIS region 200A, thereby forming an n-type LDD region 211A as shown in FIG. In addition, after selectively covering the gate structure 250A and the nMIS region 200A including the non-oxidizing offset spacer 206A and the oxidizing offset spacer 208A on the sidewall thereof with a photoresist (not shown), the gate structure 250B and the sidewall on the sidewall. Using the oxidative offset spacer 208B as a mask, p-type impurities are ion-implanted into the pMIS region 200B, thereby forming a p-type LDD region 211B as shown in FIG. 4D.

  Next, as shown in FIG. 4D, an L-shaped sidewall spacer 209A and an LDD sidewall spacer 210A are formed on the sidewall of the gate structure 250A via a non-oxidizing offset spacer 206A and an oxidizing offset spacer 208A. At the same time, an L-shaped sidewall spacer 209B and an LDD sidewall spacer 210B are sequentially formed on the side wall of the gate structure 250B via an oxidative offset spacer 208B. That is, the spacer structure formed on the side wall of the gate structure 250A of the n-channel transistor includes a non-oxidizing offset spacer 206A, an oxidizing offset spacer 208A, an L-shaped side wall spacer 209A, and an LDD side wall spacer 210A. The spacer structure formed on the sidewall of the transistor gate structure 250B includes an oxidizing offset spacer 208B, an L-shaped sidewall spacer 209B, and an LDD sidewall spacer 210B.

  Next, the pMIS region 200B including the gate structure 250B and the spacer structure on the sidewall thereof is selectively covered with a photoresist (not shown), and then the nMIS region 200A is formed using the gate structure 250A and the spacer structure on the sidewall as a mask. Then, n-type impurities are ion-implanted to form n-type source / drain regions 212A as shown in FIG. In addition, after selectively covering the nMIS region 200A including the gate structure 250A and the spacer structure on the sidewall thereof with a photoresist (not shown), the pMIS region 200B is formed using the gate structure 250B and the spacer structure on the sidewall as a mask. By implanting p-type impurities, p-type source / drain regions 212B are formed as shown in FIG.

  Finally, activation annealing for activating the implanted impurities in the LDD regions 211A and 211B and the source / drain regions 212A and 212B is performed.

  According to the present embodiment described above, the spacer structure, that is, the oxidizable offset spacer 208B in contact with the side wall of the gate structure 250B of the p-channel transistor has an oxidizing property (that is, the oxygen concentration is high). Since the effective work function can be increased, the absolute value of the threshold voltage of the p-channel transistor can be decreased. In addition, since the spacer structure in contact with the sidewall of the gate structure 250A of the n-channel transistor, that is, the non-oxidizing offset spacer 206A has non-oxidizing properties (that is, the oxygen concentration is low), the effective work function of the gate electrode is reduced. Therefore, the absolute value of the threshold voltage of the n-channel transistor can be reduced. Therefore, it is possible to provide a semiconductor device having a CMIS transistor in which the threshold voltage of the p-channel transistor and the n-channel transistor is reduced to improve the driving capability.

  In the first embodiment, the oxidizing offset spacer is formed first, whereas in this embodiment, the non-oxidizing offset spacer is formed first. Here, whether the interface or side surface in the gate structure composed of the gate insulating film and the gate electrode is oxidized or reduced is basically determined in the gate structure during the heat treatment such as the impurity activation annealing step later. Depending on whether the spacer structure in contact with the sidewall is oxidizing or non-oxidizing, the formation of the spacer structure in contact with the sidewall of the gate structure also oxidizes the interface and side surfaces in the gate structure. It is thought that it has some influence on whether it is reduced.

  That is, when only the oxidative offset spacer of the n-channel transistor is removed after forming the oxidative offset spacer first as in the first embodiment, the interface and side surfaces in the gate structure are oxidized. Therefore, since the effective work function of the gate electrode increases, there is a concern that a demerit that the threshold voltage increases in the n-channel transistor may occur. On the other hand, when only the non-oxidizing offset spacer of the p-channel transistor is removed after forming the non-oxidizing offset spacer first as in this embodiment, the interface and side surfaces in the gate structure are reduced. Therefore, since the effective work function of the gate electrode is reduced, there is a concern that the threshold voltage increases in the p-channel transistor. Therefore, which one of the oxidizing offset spacer and the non-oxidizing offset spacer is formed first is selected in consideration of which one of the n-channel transistor and the p-channel transistor is preferentially considered and the difficulty of the process. .

  In this embodiment, the spacer structure formed on the side wall of the gate structure 250B of the n-channel transistor has a structure in which a non-oxidizing offset spacer 206A and an oxidizing offset spacer 208A are stacked. However, instead of forming the offset offset spacers 208A and 208B, as shown in FIG. 4C, the pMIS region 200A including the gate structure 250B and the oxide offset spacer 208B on the sidewall thereof is removed from the photoresist. After the selective covering (not shown), the oxidizing offset spacer 208A on the sidewall of the gate structure 250A may be selectively removed. Thereafter, after the photoresist is removed, a semiconductor device shown in FIG. 5A can be obtained by performing a process similar to the process shown in FIG.

  Further, in the semiconductor device of the present embodiment shown in FIG. 4D, the gate structure 250A as shown in FIG. 5B after impurity activation annealing is performed, for example, to enhance stress application by a stress liner film. The LDD sidewall spacers 210A on the sidewalls may be removed, and the LDD sidewall spacers 210B on the sidewalls of the gate structure 250B may be removed. Similarly, in the semiconductor device of the modified example of the present embodiment shown in FIG. 5A, the LDD sidewall spacer 210A on the sidewall of the gate structure 250A is removed and the gate structure is removed as shown in FIG. The LDD sidewall spacer 210B on the 250B sidewall may be removed.

  In this embodiment, after the non-oxidizing offset spacer 206B on the side wall of the gate structure 250B of the p-channel transistor is selectively removed in the step shown in FIG. 4B, the step shown in FIG. In the process, oxidative offset spacers 208A and 208B were deposited on the respective sidewalls of each gate structure 250A and 250B. However, instead of performing the deposition process of the oxidative offset spacers 208A and 208B shown in FIG. 4C, as shown in FIG. 5D, on the side wall of the gate structure 250A of the n-channel transistor. An L-shaped sidewall spacer 209A and an LDD sidewall spacer 210A are sequentially formed through the non-oxidizing offset spacer 206A, and an oxidizing L-shaped sidewall spacer 209B is formed on the sidewall of the gate structure 250B of the p-channel transistor. , And LDD sidewall spacers 210B may be formed sequentially. In this case, for example, after the impurity activation annealing, the LDD sidewall spacers 210A on the sidewalls of the gate structure 250A are removed and the LDD sidewalls on the sidewalls of the gate structure 250B to enhance stress application by a stress liner film. The spacer 210B may be removed. Alternatively, as shown in FIG. 5E, the non-oxidizing offset spacers are formed on the sidewalls of the gate structure 250A of the n-channel transistor without performing the deposition process of the oxidizing offset spacers 208A and 208B shown in FIG. The LDD sidewall spacer 210A may be formed via 206A, and the LDD sidewall spacer 210B having oxidation property may be formed on the sidewall of the gate structure 250B of the p-channel transistor. That is, the formation of the L-shaped sidewall spacers 209A and 209B may be omitted.

  As described above, there are various variations in the spacer structure that achieves the same effect as in the present embodiment. However, the selection of the configuration of the present embodiment or the configuration of any one of the variations is difficult for a process such as ion implantation. Etc. are taken into consideration.

  In the present embodiment, the widths of the non-oxidizing offset spacers 206A and 206B and the oxidizing offset spacers 208A and 208B are not particularly limited, but are 5 nm or more from the viewpoint of the effect of reducing the threshold voltage. From the viewpoint of miniaturization, it is preferably 10 nm or less.

  In this embodiment, silicon oxide films are used as the oxidative offset spacers 208A and 208B. However, other oxygen-containing insulating films such as silicon oxynitride films may be used instead. Further, when an L-shaped side wall spacer 209B or an LDD side wall spacer 210B having an oxidizing property is used as the spacer structure in contact with the side wall of the gate structure 250A of the p-channel transistor (see FIGS. 5D and 5E), It goes without saying that a silicon oxide film or the aforementioned silicon oxynitride film may be used as these sidewall spacers.

  In this embodiment, silicon nitride films are used as the non-oxidizing offset spacers 206A and 206B. Instead, the oxygen concentration is lower or substantially lower than that of the oxidizing offset spacers 208A and 208B. Other insulating films not included may be used. In particular, from the viewpoint of reducing the fringe capacity, it is preferable to use a low dielectric constant insulating film that does not substantially contain oxygen and has a relative dielectric constant of less than 8, such as a SiC film, a BN film, a SiBCN film, or a SiBN film. Furthermore, in the semiconductor device of the present embodiment, as a whole CMIS, the use of a material having a high relative dielectric constant for the spacer structure is minimized, or the use of a low dielectric constant material for the spacer structure is promoted. As a result, the drive capability can be improved while suppressing the fringe capacity.

  In the present embodiment, the gate electrodes 205A and 205B have a stacked structure including a lower metal-containing film and an upper polysilicon film. However, it goes without saying that the structures of the gate electrodes 205A and 205B are not particularly limited. For example, different materials may be used for the gate electrode 205A of the n-channel transistor and the gate electrode 205B of the p-channel transistor. The same applies to the gate insulating films 204A and 204B. Further, the order of forming the gate structures 250A and 250B of each transistor is not particularly limited. For example, the same material is used for the gate insulating films 204A and 204B and the gate electrodes 205A and 205B of each transistor as in this embodiment. May be used, the gate structures 250A and 250B of each transistor may be formed simultaneously.

  As described above, the present invention is useful for realizing a semiconductor device having a high-performance CMIS transistor.

100, 200 Semiconductor substrate 100A, 200A nMIS region 100B, 200B pMIS region 101, 201 Element isolation region 102A, 102B, 202A, 202B Interface layer 103A, 103B, 203A, 203B High-k layer 104A, 104B, 204A, 204B Gate insulation Film 105A, 105B, 205A, 205B Gate electrode 106A, 106B, 208A, 208B Oxidizing offset spacer 107, 121, 207 Photoresist 108A, 108B, 206A, 206B Non-oxidizing offset spacer 109A, 109B, 209A, 209B L-shaped side Wall spacer 110A, 110B, 210A, 210B LDD sidewall spacer 111A, 211A n-type LDD region 111B, 211B p-type LD Regions 112A, 212A n-type source and drain regions 112B, 212B p-type source and drain regions 150A, 150B, 250A, 250B gate structure

Claims (28)

A p-channel transistor having a first gate structure formed on a first region in a semiconductor substrate and a first spacer structure formed on a sidewall of the first gate structure;
An n-channel transistor having a second gate structure formed on a second region of the semiconductor substrate and a second spacer structure formed on a sidewall of the second gate structure;
The oxygen concentration in the contact portion with the sidewall of the first gate structure in the first spacer structure is higher than the oxygen concentration in the contact portion with the sidewall of the second gate structure in the second spacer structure. A semiconductor device characterized by being expensive. The semiconductor device according to claim 1,
The first spacer structure includes a first offset spacer in contact with a sidewall of the first gate structure;
2. The semiconductor device according to claim 1, wherein the second spacer structure includes a second offset spacer made of an insulating film in contact with a side wall of the second gate structure and different from the first offset spacer. The semiconductor device according to claim 2,
The first spacer structure further includes another offset spacer formed on the side wall of the first gate structure via the first offset spacer and made of the same insulating film as the second offset spacer. A semiconductor device characterized by the above. The semiconductor device according to claim 2,
The second spacer structure further includes another offset spacer formed on the side wall of the second gate structure via the second offset spacer and made of the same insulating film as the first offset spacer. A semiconductor device characterized by the above. The semiconductor device according to any one of claims 2 to 4,
A width of each of the first offset spacer and the second offset spacer is 5 nm or more and 10 nm or less. The semiconductor device according to claim 1,
The first spacer structure includes an offset spacer in contact with a sidewall of the first gate structure;
The semiconductor device, wherein the second spacer structure includes a sidewall spacer made of an insulating film that is in contact with a sidewall of the second gate structure and is different from the offset spacer. The semiconductor device according to claim 6.
The first spacer structure further includes another sidewall spacer formed on the sidewall of the first gate structure via the offset spacer and made of the same insulating film as the sidewall spacer. Semiconductor device. The semiconductor device according to claim 1,
The first spacer structure includes a sidewall spacer in contact with a sidewall of the first gate structure;
The semiconductor device, wherein the second spacer structure includes an offset spacer made of an insulating film that is in contact with a side wall of the second gate structure and is different from the sidewall spacer. The semiconductor device according to claim 8,
The second spacer structure further includes another sidewall spacer formed on the sidewall of the second gate structure via the offset spacer and made of the same insulating film as the sidewall spacer. Semiconductor device. The semiconductor device according to any one of claims 6 to 9,
The width of the offset spacer is 5 nm or more and 10 nm or less. The semiconductor device according to claim 6, wherein
The sidewall spacer is an L-shaped sidewall spacer, an LDD sidewall spacer, or a laminated sidewall spacer formed in the order of an L-shaped sidewall spacer and an LDD sidewall spacer. Semiconductor device. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a contact portion of the first spacer structure with a side wall of the first gate structure is made of a silicon oxide film or a silicon oxynitride film. The semiconductor device according to any one of claims 1 to 12,
The contact portion of the second spacer structure with the side wall of the second gate structure is made of a silicon nitride film or a low dielectric constant insulating film having a relative dielectric constant of less than 8 that substantially does not contain oxygen. Semiconductor device. The semiconductor device according to claim 13,
The semiconductor device, wherein the low dielectric constant insulating film is a SiC film, a BN film, a SiBCN film, or a SiBN film. The semiconductor device according to claim 1,
Each of the first gate structure and the second gate structure includes a high dielectric constant insulating film and a metal-containing film formed on the high dielectric constant insulating film. Forming a first gate structure and a second gate structure on each of the p-channel transistor formation region and the n-channel transistor formation region in the semiconductor substrate;
A spacer forming step of forming a first spacer structure and a second spacer structure on respective sidewalls of the first gate structure and the second gate structure;
The oxygen concentration in the contact portion with the sidewall of the first gate structure in the first spacer structure is higher than the oxygen concentration in the contact portion with the sidewall of the second gate structure in the second spacer structure. A method for manufacturing a semiconductor device, which is expensive. In the manufacturing method of the semiconductor device according to claim 16,
The spacer forming step includes
Forming a first offset spacer in contact with a sidewall of the first gate structure;
Forming a second offset spacer made of an insulating film that is in contact with the side wall of the second gate structure and is different from the first offset spacer. In the manufacturing method of the semiconductor device according to claim 17,
After forming the first offset spacer and forming another offset spacer which is in contact with the side wall of the second gate structure and made of the same insulating film as the first offset spacer, the other offset spacer is selectively used. After that, the second offset spacer is formed, and at the same time, another offset made of the same insulating film as the second offset spacer is formed on the side wall of the first gate structure via the first offset spacer. The manufacturing method of the semiconductor device characterized by forming a spacer. In the manufacturing method of the semiconductor device according to claim 17,
After forming the second offset spacer and forming another offset spacer which is in contact with the side wall of the first gate structure and made of the same insulating film as the second offset spacer, the other offset spacer is selectively used. Then, the first offset spacer is formed, and at the same time, another offset made of the same insulating film as the first offset spacer is formed on the side wall of the second gate structure via the second offset spacer. The manufacturing method of the semiconductor device characterized by forming a spacer. In the manufacturing method of the semiconductor device of any one of Claims 17-19,
The spacer forming step includes
Forming a first sidewall spacer on the sidewall of the first gate structure via the first offset spacer;
Forming a second sidewall spacer on the sidewall of the second gate structure via the second offset spacer. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 20,
The method of manufacturing a semiconductor device, wherein the first sidewall spacer and the second sidewall spacer each include an L-shaped sidewall spacer. In the manufacturing method of the semiconductor device according to claim 20,
An L-shaped sidewall spacer and an LDD sidewall spacer are sequentially formed as the first sidewall spacer and the second sidewall spacer, and then each LDD sidewall spacer is removed. Production method. In the manufacturing method of the semiconductor device according to claim 16,
The spacer forming step includes
Forming an offset spacer in contact with a sidewall of the first gate structure;
Forming a sidewall spacer which is in contact with a side wall of the second gate structure and is made of an insulating film different from the offset spacer. 24. The method of manufacturing a semiconductor device according to claim 23,
After forming the offset spacer and forming another offset spacer that is in contact with the side wall of the second gate structure and made of the same insulating film as the offset spacer, the other offset spacer is selectively removed, and then In the semiconductor device, the side wall spacer is formed and another side wall spacer made of the same insulating film as the side wall spacer is formed on the side wall of the first gate structure via the offset spacer. Production method. In the manufacturing method of the semiconductor device according to claim 16,
The spacer forming step includes
Forming a sidewall spacer in contact with a sidewall of the first gate structure;
Forming an offset spacer made of an insulating film which is in contact with a side wall of the second gate structure and is different from the side wall spacer. In the manufacturing method of the semiconductor device according to claim 25,
After forming the offset spacer and forming another offset spacer that is in contact with the side wall of the first gate structure and made of the same insulating film as the offset spacer, the other offset spacer is selectively removed, and then In the semiconductor device, the side wall spacer is formed and another side wall spacer made of the same insulating film as the side wall spacer is formed on the side wall of the second gate structure via the offset spacer. Production method. In the manufacturing method of the semiconductor device according to claim 24 or 26,
The method for manufacturing a semiconductor device, wherein the sidewall spacer and the other sidewall spacer each include an L-shaped sidewall spacer. In the manufacturing method of the semiconductor device according to claim 24 or 26,
An L-shaped sidewall spacer and an LDD sidewall spacer are sequentially formed as the sidewall spacer and the other sidewall spacer, and then the LDD sidewall spacer is removed.