JP2011108769A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor device that achieves low resistance and high breakdown voltage by preventing a vertical structure and a different kind of structure from adversely affecting each other even if the vertical structure and the different kind of structure are integrated with each other. <P>SOLUTION: The semiconductor device 1 is equipped with: a p-substrate 21; a surface n-layer 22 formed on the surface side of the p-substrate 21; a p-base layer 31 disposed and formed on the surface side of the surface n-layer 22 and formed with a channel CH; a connection p-layer 34 formed between the p-substrate 21 and the p-base layer 31; a vertical n-layer 41 connected to the surface n-layer 22 and formed on the side face of the p-substrate 21; a source electrode 13 formed on the surface side of the p-base layer 31; a gate electrode 12 formed on the surface side of the surface n-layer 22 so as to control the channel CH; and a drain electrode 14 formed on the rear-surface side of the p-substrate 21. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device that can be applied to a vertical field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a diode, a thyristor, and the like.

  In general, semiconductor devices are roughly classified into a vertical structure in which current flows in the thickness direction of the substrate and a horizontal structure in which current flows in the in-plane direction of the substrate. Power MOSFETs and semiconductor relays (SSR: Solid State Relay) that require a high breakdown voltage are often configured as vertical double-diffused MOSFETs (DMOSFETs).

In short, this DMOSFET includes, for example, an n ⁻ drift layer formed of n type silicon, a p type base layer formed by diffusing impurities on the surface side of the n ⁻ drift layer, and a p type base layer. structure and a drain electrode formed on the back surface side of the drift layer ^- and n ⁺ layer formed by diffusing impurities within, n ^- a gate electrode and a source electrode formed on the surface side of the drift layer, n It is. In such a structure, when a predetermined voltage is applied to the gate electrode, n ^- channel p-type base layer between the drift layer and the n ⁺ layer is formed, it is supplied from the source electrode n ⁺ layer and the p-type base A current passing through channels formed in the layer sequentially flows in the n ⁻ drift layer in the thickness direction of the substrate and flows into the drain electrode.

  In Patent Document 1 below, by forming a layer having a conductivity type different from that used for the drift layer on the side surface of the drift layer, a guard ring and a field plate for preventing the depletion layer from spreading are not required. A technique for realizing high breakdown voltage and high reliability while reducing the size of a semiconductor device is disclosed. Non-Patent Document 2 below specifically discloses characteristics and the like of the prototype of the semiconductor device disclosed in Patent Document 1.

JP 2004-319974 A

Tomonori Komachi, two others, "3000V class MOSFET switch for semiconductor relay using MEMS process", Yokogawa Technical Report, Vol. 52, no. 4,2008

  By the way, since the mounting area of the semiconductor device is often limited as the various devices on which the semiconductor device is mounted are downsized and highly functional, the size of the semiconductor device is being reduced. In the future, since the mounting area of the semiconductor device is expected to be increasingly limited, it is considered that not only miniaturization but also high integration is required for the semiconductor device. In order to increase the integration density of semiconductor devices, it may be necessary to integrate a vertical structure semiconductor device and a horizontal structure semiconductor device on one chip. For example, this is a case where a vertical high breakdown voltage MOSFET and a horizontal low breakdown voltage MOSFET or bipolar transistor are integrated on one chip.

  However, when a vertical semiconductor device and a horizontal semiconductor device are integrated, since a current flows in the thickness direction of the substrate in the vertical semiconductor device, a semiconductor with a horizontal structure in which a part of the current is integrated It is conceivable to flow into the device. As a result, the semiconductor device having the lateral structure operates differently from the original operation due to this current, and there is a possibility that the operation becomes unstable or malfunctions.

  The present invention has been made in view of the above circumstances, and it is possible to realize a small size, low resistance and high breakdown voltage without adversely affecting each other even if a vertical structure and another structure are integrated. An object is to provide a semiconductor device.

In order to solve the above problems, a semiconductor device of the present invention includes a substrate (21, 51) forming a first region of a first conductivity type, and a second conductivity type of a second conductivity type formed on the surface side of the first region. Two regions (22, 52), a third region (31, 61) of a first conductivity type arranged on the surface side of the second region to form a channel (CH), the first region, A first conductivity type connection region (34, 64) formed between the third region and a second conductivity type fourth region connected to the second region and formed on a side surface of the first region. A region (41, 71), a first electrode (13) formed on the surface side of the third region, and a second electrode (12) formed on the surface side of the second region to control the channel, And a third electrode (14) formed on the back side of the first region.
According to the present invention, carriers through the channel formed in the third region are guided by the second region to the side surface of the substrate, which is the first region, and then transferred to the back surface side through the side surface of the substrate by the fourth region. Thus, the light is guided from the front surface side to the back surface side so as to bypass the substrate.
The semiconductor device of the present invention is characterized in that the connection region is formed between the first region and all the third regions.
Moreover, the semiconductor device of the present invention is characterized in that the fourth region is formed on all side surfaces of the first region.
The semiconductor device according to the present invention is characterized in that the layout of the fourth region is formed in a comb shape.
Further, the semiconductor device of the present invention includes a first array region formed in a state where the third region is covered only by the second region with respect to one first region, the second region, A second array region formed in a state covered with the connection region; a third array region formed in an outermost periphery in a state covered by the second region, the connection region, and the fourth region; The first conductivity type is p-type, the second conductivity type is n-type, and the vertical p-layer (42) formed on the side surface of the fourth region and the vertical p-layer A side oxide film (43) formed on a side surface and an n ⁺ layer (23) formed between the first region and the third electrode and in contact with the fourth region are provided.
In addition, the semiconductor device of the present invention is characterized by including a horizontal circuit portion (R1) formed in the central portion and a vertical power supply portion (R2) formed in the peripheral portion.

  According to the present invention, the carrier via the channel formed in the third region is guided to the side surface side of the substrate which is the first region by the second region, and is guided to the back surface side by way of the fourth region through the side surface of the substrate. Since the carrier is guided from the front surface side to the back surface side of the substrate so as to bypass the substrate, the carrier via the channel of the element related to the vertical structure even if the vertical structure and other structures are integrated Is not led to an element having another structure, so that there is an effect that a small size, a low resistance and a high breakdown voltage can be realized without adversely affecting each other.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which follows the AA line in FIG. It is sectional drawing which follows the BB line in FIG. It is sectional drawing which shows the 1st modification of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the 2nd modification of the semiconductor device by 1st Embodiment of this invention. 1 is a diagram illustrating a layout example of a semiconductor device according to a first embodiment of the present invention. It is a top view of the semiconductor device by a 2nd embodiment of the present invention. It is sectional drawing which follows the CC line in FIG.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following, a semiconductor device having a vertical double diffusion MOSFET (DMOSFET) structure will be described as an example. However, the semiconductor device of the present invention can be applied to IGBTs, diodes, thyristors, etc. in addition to DMOSFETs. is there.

[First Embodiment]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, for easy understanding, only a part of the semiconductor device is illustrated in an enlarged manner, and electrodes (source electrode and gate electrode) and oxide films formed on the surface side of the semiconductor device are illustrated. The state where a part is peeled is shown. 2 and 3 are cross-sectional views of the semiconductor device, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is taken along line BB in FIG. It is sectional drawing.

  As shown in FIGS. 1 to 3, in the semiconductor device 1 of this embodiment, the gate electrode 12 (second electrode) and the source electrode 13 (first electrode) are on the back side of the substrate 11. A drain electrode 14 (third electrode) is provided, and carriers (electrons) flowing from the source electrode 13 to the drain electrode 14 through the substrate 11 are controlled by a voltage applied to the gate electrode 12. 2 and 3, the layer with the symbol “n” means a layer (second conductivity type layer) having electrons as majority carriers, and the layer with the symbol “p” has holes. It means a layer (first conductivity type layer) used as a majority carrier. Further, the symbol “+” accompanying the symbol “n” or the symbol “p” means that the layer has a relatively high impurity concentration.

The gate electrode 12 is formed of, for example, polysilicon, and is formed over almost the entire surface of the substrate 11 except for the vicinity of the end of the semiconductor device 1. In the gate electrode 12, contact holes H having a rectangular shape in plan view and a predetermined size are arranged in a plane parallel to the surface of the substrate 11 with a predetermined interval. An oxide film 15 such as SiO ₂ is formed so as to surround the gate electrode 12 over almost the entire surface of the substrate 11. The source electrode 13 is formed on almost the entire surface of the substrate 11 so as to cover the gate electrode 12 through the oxide film 15 and fill the contact hole H formed in the gate electrode 12. The drain electrode 14 is formed over almost the entire back surface of the substrate 11.

The substrate 11 includes a p substrate 21 (first region), a surface n layer 22 (second region) formed on the p substrate 21, an n ⁺ layer 23 formed on the lower portion of the p substrate 21, and the like. The p substrate 21 is supplied from the source electrode 13 and prevents a current from flowing in the thickness direction of the substrate 11 through a channel CH (details will be described later) formed by a voltage applied to the gate electrode 12. . For this reason, current through the channel CH does not flow into the drain electrode 14 through the p substrate 21.

The surface n layer 22 guides the current through the channel CH to the side surface side of the p substrate 21. As described above, since the current through the channel CH does not flow through the p substrate 21, the current through the channel CH is bypassed through the channel CH in order to bypass the current through the channel CH and guide it to the drain electrode 14 formed on the back surface of the substrate 11. A current is guided to the side surface side of the p substrate 21 by the surface n layer 22. The n ⁺ layer 23 is formed in order to obtain an ohmic contact with the drain electrode 14.

On the surface side of the surface n layer 22, a p base layer 31 (third region) is arranged and formed by diffusion of impurities using the contact hole H of the gate electrode 12. The p ⁺ layer 32 and the n ⁺ layer 33 are formed by impurity diffusion using the 12 contact holes H again. The p base layer 31, the p ⁺ layer 32, and the n ⁺ layer 33 have a rectangular shape as seen in a plan view as shown in FIG. A connection p layer 34 (connection region) for connecting the p base layer 31 and the p substrate 21 is provided on the back surface side (side in contact with the p substrate 21) of the surface n layer 22 in the portion where the p base layer 31 is formed. Is formed. Here, it can be said that the p base layer 31 is a region (second array region) formed in a state covered with the surface n layer 22 and the connection p layer 34.

The distance Lg between the contact holes H formed in the gate electrode 12 described above corresponds to the length of the gate electrode 12 and is formed from the n ⁺ layer 33 formed in one of the adjacent p base layers 31 to the other. This is the length up to the n ⁺ layer 33. The interval Lg needs to be set to a length that does not reduce the resistance when the semiconductor device 1 is turned on. The size of the contact hole H is determined by the size Ls of the source electrode 13 and the thickness of the oxide film 15 in the contact hole H. In order to increase the breakdown voltage of the semiconductor device 1, it is preferable to set the distance Lg between the contact holes H wider than the size Ls of the source electrode 13.

Here, among the p base layers 31 arranged and formed on the surface n layer 22, the one located at the outermost periphery is the outermost peripheral p base layer 31a. In the outermost peripheral p base layer 31a, a p ⁺ layer 32a and an n ⁺ layer 33a similar to the p ⁺ layer 32 and the n ⁺ layer 33 provided in the p base layer 31 are formed, respectively. However, as shown in FIG. 1, unlike the p base layer 31 having a rectangular shape in plan view, the outermost peripheral p base layer 31 a is formed in a belt shape in plan view along the outer periphery of the semiconductor device 1. Has been. Further, in the p base layer 31, the n ⁺ layer 33 is formed so as to surround the p ⁺ layer 32 in plan view, but in the outermost peripheral p base layer 31a, the n ⁺ layer 33a is in one side of the p ⁺ layer 32a in plan view. It is formed only on the side opposite to the side facing the end of the semiconductor device 1.

A vertical n layer 41 (fourth region), a vertical p layer 42, and a side oxide film 43 are formed at the end of the semiconductor device 1. The vertical n layer 41 guides the current guided to the side surface of the p substrate 21 by the surface n layer 22 to the drain electrode 14 provided on the back surface of the substrate 11 (to be precise, to the n ⁺ layer 23). And is formed on the side surface of the p substrate 21. Specifically, the vertical n layer 41 is formed on the side surface of the p substrate 21 so that the upper end is connected to the end of the surface n layer 22 and the lower end is connected to the n ⁺ layer 23. For example, when the shape of the p substrate 21 in a plan view is a rectangular shape, the p substrate 21 is formed on four side surfaces of the p substrate 21 so as to surround the p substrate 21.

  The vertical n layer 41 is preferably formed so as to surround the four sides of the p substrate 21 from the viewpoint of reducing resistance. However, it is not necessarily formed so as to surround the four sides of the p substrate 21 in plan view. For example, it may be formed on only one to three side surfaces of the p substrate 21, or one of the side surfaces may be formed. You may form only in part. Here, it can be said that the outermost peripheral p base layer 31a is a region (third array region) formed in a state covered with the surface n layer 22, the connection p layer 34, and the vertical n layer 41.

The vertical p layer 42 is provided to reduce the size of the semiconductor device 1 (to reduce the size in plan view), and is bonded to the vertical n layer 41 with few defects. Specifically, the vertical p layer 42 is joined to the vertical n layer 41 so that the upper end is connected to the outermost peripheral p base layer 31 a and the lower end is connected to the n ⁺ layer 23. The vertical p layer 42 is depleted when a reverse bias is applied by the voltage applied to the gate electrode 12 when the semiconductor device 1 is in an off state (a state where the channel CH is not formed).

The side oxide film 43 is formed of SiO ₂ or the like formed on the side surface of the semiconductor device 1 to protect the outermost peripheral p base layer 31a, the vertical p layer 42, and the n ⁺ layer 23 exposed at the end of the semiconductor device 1. This is an oxide film. The side oxide film 43 has an upper end connected to the oxide film 15 formed on the surface side of the substrate 11, and the lower end does not expose the n ⁺ layer 23 from the side surface of the semiconductor device 1.

Next, the operation of the semiconductor device 1 having the above configuration will be described. When the value of the voltage V _ds applied between the source electrode 13 and the drain electrode 14 is positive, the semiconductor device 1 has the value of the voltage V _gs applied between the gate electrode 12 and the source electrode 13. Is turned off when is zero, and is turned on when the value of the voltage V _gs is larger than a predetermined threshold value V _th . Hereinafter, the operation in the on state and the operation in the off state will be described in order.

[Operation when on]
When the voltage V _gs applied between the gate electrode 12 and the source electrode 13 becomes larger than a predetermined threshold value V _th , a channel CH is formed above the p base layer 31 and below the oxide film 15 ( (See FIG. 2). In FIG. 2, only a part of the channel CH formed in the p base layer 31 is shown. However, the channel CH is a portion where the p base layer 31 and the oxide film 15 are in contact with each other (a rectangular ring shape in plan view). Part (see FIG. 1)).

When the channel CH is formed, carriers (electrons) supplied from the source electrode 13 to the n ⁺ layer 33 flow into the surface n layer 22 after passing through the channel CH of the p base layer 31. The carriers (electrons) that have flowed into the surface n layer 22 are guided to the side surface side of the p substrate 21 by the surface n layer 22 and then flow into the vertical n layer 41 formed on the side surface of the p substrate 21. The carriers (electrons) that have flowed into the vertical n layer 41 are guided to the n ⁺ layer 23 by the vertical n layer 41 and then flow into the drain electrode 14 through the n ⁺ layer 23. In this way, the source electrode 13 formed on the surface of the substrate 11 is formed on the back surface of the substrate 11 via the substrate 11 (via the surface n layer 22 and the vertical n layer 41 formed on the substrate 11). A current flows through the drain electrode 14.

[Operation when off]
When the value of the voltage V _gs applied between the gate electrode 12 and the source electrode 13 is zero, a bias voltage is applied to the drain electrode 14 and the voltage V _ds between the source electrode 13 and the drain electrode 14 is _reduced . When the value becomes positive, the depletion layer of the pn junction formed at the boundary between the p base layer 31 and the outermost peripheral p base layer 31a and the surface n layer 22 expands. This depletion layer extends in both the thickness direction of the substrate 11 and the in-plane direction of the substrate 11. As a result, the channel CH described above is not formed in the p base layer 31 and the outermost peripheral p base layer 31a, so that the source electrode 13 formed on the surface of the substrate 11 is changed to the drain electrode 14 formed on the back surface of the substrate 11. No current flows.

  Here, the spread of the depletion layer is determined by the impurity concentration of the p substrate 21, the surface n layer 22, the p base layer 31, the outermost peripheral p base layer 31a, the vertical n layer 41, the vertical p layer 42, and the like. However, in this embodiment, an interface charge is generated between the side oxide film 43 and the vertical p layer 42. For this reason, the impurity concentration of the p substrate 21, the vertical n layer 41, and the vertical p layer 42 is completely depleted in a state where a high bias is applied in the off state in consideration of the charge amount of the interface charge. It is desirable to set so that

Next, a method for manufacturing the semiconductor device 1 having the above configuration will be briefly described. First, an oxide film is formed over the entire surface of the substrate 11 on which the n ⁺ layer 23, the p substrate 21, and the surface n layer 22 are formed, and then an electrode layer such as polysilicon is formed over the entire surface of the oxide film. Form. Next, a contact hole H is formed by removing a portion where the p base layer 31 is to be formed from the oxide film and electrode layer formed over the entire surface of the substrate 11. Thereby, a part of the oxide film 15 and the gate electrode 12 are formed on the substrate 11.

Next, using the gate electrode 12 as a mask, impurities are diffused from the contact hole H formed in the gate electrode 12 into the surface n layer 22 of the substrate 11 to form a connection p layer 34. Similarly, using the gate electrode 12 as a mask, impurities are diffused from the contact hole H formed in the gate electrode 12 into the surface n layer 22 of the substrate 11 to form the p base layer 31 and the outermost peripheral p base layer 31a. . When the p base layer 31 and the outermost peripheral p base layer 31a are formed, impurities are transferred from the contact hole H formed in the gate electrode 12 to the p base layer 31 and the outermost peripheral p base layer 31a using the gate electrode 12 as a mask. Diffusion is performed to form n ⁺ layers 33 and 33a. When the above steps are completed, the step of forming the oxide film 15 around the base electrode 12 and the step of forming the source electrode 13 are sequentially performed.

Next, the portions where the vertical n layer 41 and the vertical p layer 42 of the substrate 11 are to be formed are vertically etched by ICP (Inductively Coupled Plasma) used in silicon MEMS (Micro Electro Mechanical Systems) technology, A hole reaching the n ⁺ layer 23 of the substrate 11 is formed. After the etching using ICP is completed, the inside of the hole formed using ICP is etched by a wet etching method using an appropriate chemical solution.

When the above processing is completed, a vertical n layer 41 is first formed by epitaxial growth in a hole formed using ICP, and then a vertical p layer 42 is formed by epitaxial growth. Next, a side oxide film 43 that protects the outermost peripheral p base layer 31 a, the vertical p layer 42, and the n ⁺ layer 23 exposed at the end of the semiconductor device 1 is formed. Finally, a step of forming a drain electrode on the back surface side of the substrate 11 is performed, and the semiconductor device 1 is manufactured by separating into individual chips.

  As described above, in the semiconductor device 1 of the present embodiment, the p substrate 21 in which no current flows through the channel CH flows inside the substrate 11, and the current through the channel CH by the surface n layer 22 and the vertical n layer 41. Is bypassed (bypassing the p substrate 21) and led to the back side of the substrate 11. For this reason, even if the vertical structure element in which the current flows in the thickness direction of the substrate 11 and the horizontal structure element in which the current flows in the in-plane direction of the substrate 11 are integrated, the current flowing through the vertical structure element is the surface n layer 22. In addition, since they are not guided to the vertical n layer 41 and flow into the lateral element, they do not adversely affect each other. In addition, the semiconductor device 1 of the present embodiment can be reduced in size by providing the vertical p layer 42, and can be reduced in resistance by increasing the area of the vertical n layer 41 in plan view. By appropriately setting the sizes of the gate electrode 12 and the source electrode 13, the thickness of the substrate 11, and the like, a high breakdown voltage can be realized.

  FIG. 4 is a sectional view showing a first modification of the semiconductor device according to the first embodiment of the present invention. The cross-sectional view shown in FIG. 4 is a cross-sectional view of a portion corresponding to the line AA in FIG. In the semiconductor device 1 shown in FIG. 2, all p base layers 31 formed on the surface side of the substrate 11 and connection p layers 34 are formed between the outermost peripheral p base layer 31 a and the p substrate 21. The p base layer 31 and the outermost peripheral p base layer 31 a were connected to the p substrate 21.

  On the other hand, the semiconductor device 2 shown in FIG. 4 has a structure in which the p base layer 31 that is not connected to the p substrate 21 exists in part without the connection p layer 34 being formed. With such a structure, the area of the surface n layer 22 (area in plan view) can be increased, and the resistance of the surface n layer 22 can be reduced. Here, it can be said that the p base layer 31 having such a structure is a region (first arrangement region) formed in a state covered only by the surface n layer 22.

  If the connection p layer 34 is not formed at all and all the p base layers 31 are not connected to the p substrate 21, the potential of the source electrode 13 is not transmitted to the p substrate 21. Cannot be efficiently depleted, leading to a decrease in breakdown voltage. For this reason, it is necessary to have a structure in which at least one p base layer 31 is connected to the p substrate 21. That is, the connection between the p base layer 31 and the p substrate 21 is determined by the resistance of the surface n layer 22 and the degree of depletion (withstand voltage) of the vertical n layer 41.

FIG. 5 is a sectional view showing a second modification of the semiconductor device according to the first embodiment of the present invention. The cross-sectional view shown in FIG. 5 is also a cross-sectional view of a portion corresponding to the line AA in FIG. In the semiconductor device 3 shown in FIG. 5, the n-type semiconductor in the substrate 11 is a p-type semiconductor, and the p-type semiconductor is an n-type semiconductor. Specifically, the p substrate 21, the surface n layer 22, and the n ⁺ layer 23 shown in FIG. 2 are changed to an n substrate 51, a surface p layer 52, and a p ⁺ layer 53, respectively. Further, the p base layer 31, the outermost peripheral p base layer 31a, the p ⁺ layers 32 and 32a, the n ⁺ layers 33 and 33a, and the connection p layer 34 shown in FIG. 2 are the n base layer 61 and the outermost peripheral n base layer 61a. , N ⁺ layers 62 and 62a, p ⁺ layers 63 and 63a, and connection n layer 64 (connection region).

  Further, the vertical n layer 41 shown in FIG. 2 is changed to a vertical p layer 71. However, the semiconductor device 3 shown in FIG. 5 does not have a configuration corresponding to the vertical p layer 42 shown in FIG. When the side oxide film 43 is formed so as to cover the vertical p layer 71, depletion of the vertical p layer 42 is promoted by the negative charge generated at the interface, and the configuration corresponding to the vertical p layer 42 shown in FIG. 2 is omitted. be able to. In this modification as well, as in the first modification shown in FIG. 4, the n-type base layer 61 that is not connected to the n-substrate 51 and does not have the connection n-layer 64 is partially formed. Is also possible.

  6A and 6B are diagrams showing a layout example of the semiconductor device according to the first embodiment of the present invention, wherein FIGS. 6A to 6C are plan views and FIG. 6D is a perspective view. In FIG. 6, a member denoted by reference symbol P <b> 1 is a gate pad formed on the surface of the semiconductor device, and is electrically connected to the gate electrode 12 to serve as an external electrode. A member denoted by reference symbol P2 is a source pad formed on the surface of the semiconductor device, and is electrically connected to the source electrode 13 to serve as an external electrode.

  The layout shown in FIG. 6A is a commonly used general layout, and the shape of the semiconductor device in plan view is a substantially rectangular shape. When the semiconductor devices 1 and 2 shown in FIGS. 1 to 4 have the layout shown in FIG. 6A, the p substrate 21 is formed in a rectangular shape in plan view, and is perpendicular to surround the p substrate 21. An n layer 41 is formed. That is, the vertical n layer 41 is formed on each of the four side surfaces (planes) of the p substrate 21. When the semiconductor device 3 shown in FIG. 5 has the layout shown in FIG. 6A, the vertical p layer 71 is formed so as to surround the periphery of the rectangular n substrate 52.

  The layouts shown in FIGS. 6B and 6C are layouts for increasing the peripheral length of the semiconductor device. In FIG. 6B, comb-like protrusions are formed in the left-right direction on the paper surface. In FIG. 6C, comb-like protrusions are formed in the vertical and horizontal directions on the paper surface. When the semiconductor devices 1 and 2 shown in FIGS. 1 to 4 have the layouts shown in FIGS. 6B and 6C, the shape of the p substrate 21 in plan view is formed as shown in the figure. A vertical n layer 41 is formed so as to surround. In the case of the semiconductor device 3 shown in FIG. 5, the vertical p layer 71 is formed so as to surround the periphery of the n substrate 52 having the shape shown in FIGS. Since the area of the vertical n layer 41 and the vertical p layer 71 (area in plan view) can be increased by increasing the peripheral length of the semiconductor device, the resistance of the vertical n layer 41 and the vertical p layer 71 can be reduced. .

  In the layout shown in FIG. 6D, a plurality of semiconductor devices having a rectangular shape in plan view are prepared, and the back electrode (drain electrode 14) of each semiconductor device is used in common. Note that the gate pads P1 and the source pads P2 formed on the surface side of each semiconductor device are connected by, for example, wire bonding. When the layout shown in FIG. 6D is adopted, the on-resistance can be reduced as compared with the conventional element while the breakdown voltage is increased.

[Second Embodiment]
FIG. 7 is a plan view of a semiconductor device according to a second embodiment of the present invention. 8 is a cross-sectional view of the semiconductor device taken along line CC in FIG. The semiconductor device 4 of the present embodiment is an integration of the high breakdown voltage vertical structure elements shown in FIGS. 1 to 3 and the low breakdown voltage lateral structure elements in which a current flows in the in-plane direction of the substrate 11. In FIG. 8, members corresponding to the members shown in FIGS.

  As shown in FIGS. 7 and 8, the semiconductor device 4 of the present embodiment has a rectangular outer shape in plan view, the circuit portion R1 is disposed at the center thereof, and the power supply portion R2 is disposed at the periphery thereof. Has been placed. A low breakdown voltage lateral element is formed in the circuit part R1, and a high breakdown voltage vertical element is formed in the power supply part R2. Referring to FIG. 8, it can be seen that an element having the same structure as that shown in FIG. 2 is formed in the power supply unit R2. Further, in FIG. 8, a PMOS (p-channel MOS) 80 and an NMOS (n-channel MOS) 90 are shown as lateral elements formed in the circuit portion R1.

Here, as shown in FIG. 8, the p substrate 21 provided to prevent the current flowing through the channel CH from flowing in the thickness direction of the substrate 11 and the n ⁺ layer 23 formed on the back surface of the p substrate 21 are The semiconductor device 4 is provided over almost the entire surface except the end. The PMOS 80 in the circuit portion R1 forms an n layer 81 on the surface side of the substrate 11 (p substrate 21), forms a p ⁺ layer 82 inside the n layer 81, and includes a gate electrode 83, a source electrode 84, and a drain. It is formed by forming the electrode 85. The NMOS 90 in the circuit unit R1 includes a p layer 91 formed on the surface side of the substrate 11 (p substrate 21), an n ⁺ layer 92 formed inside the p layer 91, a gate electrode 93, a source electrode 94, And the drain electrode 95 is formed.

Referring to FIG. 8, the surface n layer 22 and the vertical n layer 41 are formed only in the power supply unit R2. For this reason, the current supplied from the source electrode 13 (the source electrode related to the vertical element formed in the power supply unit R2) via the n ⁺ layer 33 and the channel CH is supplied to the end of the semiconductor device 4 by the surface n layer 22. After being guided to the portion, the vertical n layer 41 guides to the back side of the substrate 11. Accordingly, current through the channel CH does not flow into the circuit portion R1, and the operations of the PMOS 81 and the NMOS 82 do not become unstable or malfunction.

  Note that the power supply unit R2 in which the elements having the vertical structure are formed is not necessarily formed so as to surround the circuit unit R1, but may be formed in a part of the outer periphery of the semiconductor device 4. Also in the present embodiment, the modifications shown in FIGS. 4 and 5 can be applied, and various layouts as shown in FIG. 6 can be used.

  As described above, also in the semiconductor device 4 of the present embodiment, the p substrate 21 in which no current flows through the channel CH flows inside the substrate 11, and the current through the channel CH by the surface n layer 22 and the vertical n layer 41. Is bypassed (bypassing the p substrate 21) and led to the back side of the substrate 11. For this reason, even if the PMOS 80 and NMOS 90 having the horizontal structure are integrated, the current flowing through the vertical structure element is not guided to the surface n layer 22 and the vertical n layer 41 and flows into the horizontal structure element. There is no effect. Also, the semiconductor device 4 of this embodiment can be reduced in size by providing the vertical p layer 42, and can be reduced in resistance by increasing the area of the vertical n layer 41 in plan view. By appropriately setting the sizes of the gate electrode 12 and the source electrode 13, the thickness of the substrate 11, and the like, a high breakdown voltage can be realized.

  Although the semiconductor device according to the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and can be freely changed within the scope of the present invention. For example, the substrate 11 is not limited to silicon (Si), and silicon carbide (SiC) can be used. In addition, the end portion (end surface) of the semiconductor device is not necessarily formed perpendicular to the surface of the substrate 11 and may be formed obliquely. That is, the side surfaces of the p substrate 21 and the n substrate 51 may be formed obliquely, and the vertical n layer 41, the vertical p layer 71, and further the side oxide film 43 may be formed obliquely accordingly.

1-4 Semiconductor devices 12 Gate electrode 13 Source electrode 14 Drain electrode 21 P substrate 22 Surface n layer 23 n ⁺ layer 31 p base layer 31a Outermost peripheral p base layer 34 Connection p layer 41 Vertical n layer 42 Vertical p layer 43 Side surface oxidation Film 51 n substrate 52 surface p layer 61 n base layer 61a outermost peripheral n base layer 64 connection n layer 71 vertical p layer CH channel R1 circuit unit R2 power supply unit

Claims (6)

A substrate forming a first region of a first conductivity type;
A second region of the second conductivity type formed on the surface side of the first region;
A third region of a first conductivity type arranged on the surface side of the second region to form a channel;
A connection region of a first conductivity type formed between the first region and the third region;
A fourth region of a second conductivity type connected to the second region and formed on a side surface of the first region;
A first electrode formed on the surface side of the third region;
A second electrode formed on the surface side of the second region to control the channel;
A semiconductor device comprising: a third electrode formed on a back surface side of the first region.   The semiconductor device according to claim 1, wherein the connection region is formed between the first region and all the third regions.   The semiconductor device according to claim 1, wherein the fourth region is formed on all side surfaces of the first region.   The semiconductor device according to claim 1, wherein the layout of the fourth region is formed in a comb shape. The third region is a single first region.
A first array region formed in a state covered only by the second region;
A second array region formed in a state covered with the second region and the connection region;
A third array region formed on the outermost periphery in a state covered with the second region, the connection region, and the fourth region;
The first conductivity type is p-type;
The second conductivity type is n-type;
A vertical p layer formed on a side surface of the fourth region; a side oxide film formed on a side surface of the vertical p layer;
The semiconductor device according to claim 1, further comprising: an n ⁺ layer formed between the first region and the third electrode and in contact with the fourth region. A lateral circuit portion formed in the central portion;
The semiconductor device according to claim 1, further comprising: a vertical power supply unit formed in a peripheral portion.

Images