JP2011102764A - Semiconductor integrated circuit, semiconductor integrated circuit design method, and semiconductor integrated circuit design program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, a semiconductor integrated circuit design method and a semiconductor integrated circuit design program capable of reducing the number of test patterns with respect to a semiconductor integrated circuit including an internal clock domain having data path dependency operated in the same frequency. <P>SOLUTION: This semiconductor integrated circuit includes: a first clock domain; a second clock domain operated in the same frequency as the first clock domain, and connected to the first clock domain through a data path; and a path interruption circuit for switching conduction to/from interruption of data transfer through the data path. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, a semiconductor integrated circuit design method, and a semiconductor integrated circuit design program.

  In creating a semiconductor integrated circuit, it is essential to perform a function test in order to ensure quality. However, in recent years, since the scale of semiconductor integrated circuits and the complexity of functions have progressed, the number of test patterns in function tests tends to increase. For this reason, the number of test patterns implemented for maintaining the quality of semiconductor integrated circuits has become enormous. Also, in order to reduce the number of test patterns and perform a function test, it is necessary to add many terminals for inputting / outputting test patterns.

  Therefore, there is a problem that the test cost increases due to the execution of a huge number of test patterns, and there is a problem that the chip area increases due to the addition of a large number of terminals, thereby increasing the chip cost. For this reason, it is desired to reduce the number of test patterns and reduce the cost in the production of a semiconductor integrated circuit.

  Here, Patent Literature 1 discloses a technique that can suppress an increase in test patterns and addition of terminals by the applicant of the present application. In the technique disclosed in Patent Document 1, when a DFT (Design For Testability) circuit that supplies a scan clock signal to an internal clock domain is inserted, a frequency group is extracted based on the test frequency of the internal clock domain to be tested, and the data path A frequency subgroup is extracted from the frequency group based on the dependency relationship. Based on the frequency group, a control circuit capable of selectively supplying a scan clock signal to an arbitrary internal clock domain is added to the circuit information, and the number of scan clock output terminals of the control circuit is determined based on the frequency subgroup. . Thus, it is possible to generate and execute a test pattern for simultaneously testing internal clock domains having different test frequencies and having no data path dependency.

  Here, a specific example will be described with reference to FIG. FIG. 8 shows a frequency group FG101 including frequency subgroups FSG111 and FSG112, a frequency group FG102 including frequency subgroups FSG121 and FSG122, and a frequency group FG103 including frequency subgroups FSG131 and FSG132 by the technique disclosed in Patent Document 1. It is a figure which shows the semiconductor integrated circuit from which these are extracted. The control circuits 141a, 141b, and 141c are not shown.

  The frequency sub group FSG 111 includes an internal clock domain 121, and the frequency sub group FSG 122 includes an internal clock domain 122. The frequency subgroup FSG 121 includes an internal clock domain 123, and the frequency subgroup FSG 122 includes internal clock domains 124 and 125. The frequency subgroup FSG 131 includes an internal clock domain 126, and the frequency subgroup FSG 132 includes an internal clock domain 127.

  The internal clock domain 121 has a data path dependency with the internal clock domain 122, the internal clock domain 124 has a data dependency with the internal clock domain 123, and the internal clock domain 125 has a data dependency with the internal clock domain 126. The internal clock domain 127 has a data dependency relationship with the internal clock domain 126.

  When performing a functional test in this semiconductor integrated circuit, the control circuits 141a to 141c are either in the frequency subgroup FSG111 or FSG112 in the frequency group FG101, and in any of the frequency subgroup FSG121 or FSG122 in the frequency group FG102. In the frequency group FG103, a scan clock signal is selectively supplied to either the frequency subgroup FSG131 or the FSG132. Accordingly, the scan clock signal is selectively supplied to the first test group including the internal clock domains 121, 123, and 126 or the second test group including the internal clock domains 122, 124, 125, and 127. it can.

  In this way, by selectively supplying the scan clock signal to the first and second test groups that are grouped so that the internal clock domains included in each do not have a data path dependency relationship, It is possible to generate and execute a test pattern for simultaneously testing a plurality of internal clock domains included in a test group. This makes it possible to suppress an increase in the number of test patterns.

  However, since the technique disclosed in Patent Document 1 is to perform a test by selectively supplying a scan clock signal to an arbitrary test group by the control circuits 141a to 141c, a test pattern is always set for each test group. Need to generate and execute. That is, since the internal clock domains having the data path dependency cannot be tested at the same time, there is a problem that the number of test patterns cannot be reduced sufficiently.

  In Patent Document 2, when testing a circuit having an interface signal path between a first clock domain and a second clock domain having different phases, the second signal passes through the interface signal path from the first clock domain. A technique for solving the problem that data can be transmitted in an unpredictable cycle in the clock domain is disclosed. Patent Document 2 discloses a technique in which all clock domains can be controlled predictably during a test by adding a seam circuit that causes some additional delay in the interface signal path. In addition, a technique is disclosed in which clock regions having different phases can be separated from each other and tested separately by a seam circuit.

  However, the technique disclosed in Patent Document 2 enables simultaneous testing when there is a data path dependency between internal clock domains operating at the same frequency as in the frequency group described above, and the number of test patterns It does not disclose a specific technique for reducing the amount.

JP 2007-212339 A Japanese Patent No. 3848686

  As described in the background art, there is a problem that the number of test patterns cannot be sufficiently reduced for a semiconductor integrated circuit including an internal clock domain having a data path dependency that operates at the same frequency.

  The semiconductor integrated circuit according to the first aspect of the present invention operates with a first clock domain and a second clock that operates at the same frequency as the first clock domain and is connected to the first clock domain by a data path. And a path blocking circuit for switching conduction and blocking of data transfer in the data path.

  The semiconductor integrated circuit design method according to the second aspect of the present invention detects a data path connecting a first clock domain and a second clock domain operating at the same frequency as the first clock domain. Then, a path blocking circuit for switching conduction and blocking of data transfer in the detected data path is inserted.

  A semiconductor integrated circuit design program according to a third aspect of the present invention detects a data path connecting a first clock domain and a second clock domain operating at the same frequency as the first clock domain. The computer is caused to execute a process and a process of inserting a path blocking circuit for switching between conduction and blocking of data transfer in the detected data path.

  As a result, tests can be performed in parallel on the first clock domain and the second clock domain, so that the number of test patterns can be reduced.

  According to each aspect described above, a semiconductor integrated circuit and a semiconductor integrated circuit design method capable of reducing the number of test patterns for a semiconductor integrated circuit including an internal clock domain having a data path dependency that operates at the same frequency. In addition, a semiconductor integrated circuit design program can be provided.

1 is a configuration diagram of a semiconductor integrated circuit design system according to a first exemplary embodiment of the present invention. It is a flowchart which shows the process of the semiconductor integrated circuit design system concerning Embodiment 1 of this invention. It is a figure which shows the example of the group of the internal clock domain in which the DFT circuit concerning Embodiment 1 of this invention was inserted. 1 is a diagram showing an example of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 5 is a diagram showing an example of a semiconductor integrated circuit generated by background art based on pre-DFT circuit information generated by the semiconductor integrated circuit shown in FIG. 4. It is a figure which shows an example of the circuit after DFT insertion concerning embodiment of the other invention of this invention. It is a figure which shows an example of the circuit after DFT insertion concerning embodiment of the other invention of this invention. It is a figure which shows the semiconductor integrated circuit concerning background art.

Embodiment 1 of the present invention
With reference to FIG. 1, the configuration of the semiconductor integrated circuit design system according to the first exemplary embodiment of the present invention will be described. FIG. 1 is a configuration diagram of a semiconductor integrated circuit design system according to a first embodiment of the present invention.

  The semiconductor integrated circuit design system 10 includes computers 11 and 12 and a server 13. The computers 11 and 12 and the server 13 are connected to each other via the Internet 19. The computer 11 includes a CPU (Central Processing Unit) 14 and a storage device 15. The computer 12 has a CPU 16 and a storage device 17. The server 13 has a storage device 18. The semiconductor integrated circuit design system 10 is preferably realized by a computer system that performs parallel distributed processing.

The computers 11 and 12 acquire the semiconductor integrated circuit design program and the circuit information before the DFT circuit insertion (hereinafter referred to as “circuit information before the DFT circuit insertion”) from the server 13, and the acquired circuit before the DFT circuit insertion. Based on the information, circuit information in which the DFT circuit is inserted (hereinafter, circuit information after insertion of the DFT circuit) is generated. The computers 11 and 12 are information processing apparatuses such as an engineering workstation or a PC (Personal Computer).
The server 13 transmits the semiconductor integrated circuit design program stored in the storage device 18 and the circuit information before the DFT circuit insertion to the computers 11 and 12.

The CPUs 14 and 16 execute the semiconductor integrated circuit design program acquired from the server 13 and generate post-DFT circuit information.
The storage devices 15 and 17 are, for example, hard disks or memories.
The storage device 18 stores a semiconductor integrated circuit design program for generating circuit information after DFT circuit insertion and circuit information before DFT circuit insertion. The storage device 18 is, for example, a hard disk or a memory. The circuit information is, for example, net list data.

  The Internet 19 may be any network as long as it can transmit and receive arbitrary data between the computers 11 and 12 and the server 13. For example, in addition to the Internet, there are a LAN and a telephone communication line.

Next, an outline of the operation when the semiconductor integrated circuit design system generates circuit information after inserting the DFT circuit will be described.
First, the computer 11 downloads a semiconductor integrated circuit design program stored in the storage device 18 from the server 13 via the network 19. Then, the computer 11 stores the downloaded semiconductor integrated circuit design program in the storage device 14.

  The CPU 14 of the computer 11 acquires and executes a semiconductor integrated circuit design program from the storage device 14 in accordance with an instruction from a user input to an input device (not shown) of the computer 11. Here, the input device is, for example, a mouse or a keyboard. Further, the CPU 14 acquires circuit information before DFT circuit insertion stored in the recording medium 18 of the server 13 via the Internet 19 in accordance with an instruction of the semiconductor integrated circuit design program to be executed. Then, the CPU 14 temporarily stores the acquired DFT circuit pre-insertion circuit information in the storage device 15.

  The CPU 14 inserts a DFT circuit into the circuit information before DFT circuit insertion temporarily stored in the storage device 15, and generates circuit information after insertion of the DFT circuit. Then, the generated circuit information after inserting the DFT circuit is stored in the storage device 14 of the server 13 via the storage device 15 or the Internet 19. The same applies to the case where the computer 12 generates circuit information after the DFT circuit is inserted, and a description thereof will be omitted.

  Next, processing of the semiconductor integrated circuit design system according to the first exemplary embodiment of the present invention will be described with reference to FIG. FIG. 2 is a flowchart showing processing of the semiconductor integrated circuit design system according to the first exemplary embodiment of the present invention. Here, a case where circuit information after DFT insertion is generated by the computer 11 is illustrated.

  First, the computer 11 acquires pre-DFT circuit insertion circuit information F1 stored in the storage device 18 of the server 13 (S101). The CPU 14 extracts the internal clock domain based on the pre-DFT circuit insertion circuit information F1 (S102). Based on the extracted internal clock domain information, the CPU 14 inserts a scan clock signal supply multiplexer into the pre-DFT circuit insertion circuit information F1 for each of the internal clock domains (S103). Specifically, a multiplexer is added to each of the internal clock domains so as to selectively supply either an internal clock signal supplied during normal operation or a scan clock signal supplied during testing. Hereinafter, the working DFT circuit pre-insertion circuit information F1 is stored in the storage device 15 such as a memory, and a circuit is added to this information.

  The CPU 14 acquires the DFT circuit insertion upper limit value stored in the storage device 18 of the server 13 (S104). Here, the DFT circuit insertion upper limit value input by the user may be acquired by the input device of the computer 11. Alternatively, the DFT circuit insertion upper limit value may be stored in the storage device 15 in advance, and the one specified automatically or by input from the user may be acquired. Then, the CPU 14 stores the DFT circuit insertion upper limit value in the DFT circuit insertion upper limit storage area M <b> 5 provided in the storage device 15. Here, the DFT circuit insertion upper limit value indicates, for example, the scale of a circuit that can be added without increasing the chip area of the semiconductor integrated circuit. More specifically, the information can specify the number of DFT circuits that can be inserted.

  The CPU 14 acquires the test frequency information F2 stored in the storage device 18 of the server 13 (S105). Here, the test frequency information F2 may be acquired from a user input or from the storage device 15 in the same manner as the DFT circuit insertion upper limit value. Then, the CPU 14 stores the test frequency information F2 in the test frequency storage area M1 provided in the storage device 15. Here, the test frequency information F2 is information indicating the frequency of the scan clock signal supplied to each of the internal clock domains in the function test.

  The CPU 14 extracts the dependency relationship of the path (hereinafter referred to as “data path”) through which data is transferred between the internal clock domains extracted in step S102 (S106). In other words, if there is a data path connecting between the internal clock domains in any set of internal clock domains, the data path dependency relationship is established. Then, the CPU 14 stores data path dependency relationship information indicating the data path dependency relationship between the internal clock domains in the data path dependency relationship storage area M <b> 2 provided in the storage device 15.

  Based on the internal clock domain information extracted in step S102 and the test frequency information F2 stored in the test frequency storage area M1, the CPU 14 groups the internal clock domains to which the scan clock signal having the same frequency is supplied in the function test. The frequency group information indicating the converted frequency group is generated (S107). Then, the CPU 14 stores the frequency group information in a frequency group storage area M <b> 3 provided in the storage device 15.

  Based on the frequency group information stored in the frequency group storage region M3 and the data path dependency relationship information stored in the data path dependency relationship storage region M2, the CPU 14 mutually selects internal clock domains belonging to the same frequency group. Frequency subgroup information indicating a frequency subgroup obtained by grouping internal clock domains that operate independently is generated (S108). That is, the frequency subgroup information is a grouping of internal clock domains that do not have data path dependency among clock domains belonging to the same frequency group. Then, the CPU 14 stores the frequency subgroup information in the frequency subgroup storage area M4 provided in the storage device 15.

  Based on the data path dependency relationship information stored in the data path dependency storage area M2, the CPU 14 calculates the number of DFT circuit insertions required for all of the internal clock domain groups in which the data path exists (S109). . The DFT circuit here is a circuit that is inserted into a data path between any two internal clock domains and switches between conduction and interruption of data transfer in the data path. That is, the number of DFT circuit insertions calculated here is the number of data paths in each set of internal clock domains.

  The CPU 14 extracts the number of scan flip-flops (hereinafter referred to as “scan F / F”) included in the set of internal clock domains in which the data path exists. Here, generally, when the number of scan F / Fs is large, the data length of a test pattern to be generated (hereinafter referred to as “test pattern length”) tends to be long. Here, since the number of test patterns generally tends to increase in proportion to the increase in test pattern length, the extracted scan F / F number is used as a value indicating the number of test patterns to be generated.

  The CPU 14 extracts two arbitrary sets from the entire semiconductor integrated circuit, with the preceding internal clock domain and the subsequent internal clock domain connected by the data path as a set. The CPU 14 determines the larger number of scan F / Fs (hereinafter referred to as “maximum”) among the total number of scan F / Fs included in the set of extracted internal clock domains and the number of scan F / Fs included in each of the preceding and subsequent stages. The value obtained by subtracting the maximum scan F / F number from the sum of the scan F / F numbers is used as a comparison value for the set of internal clock domains. In other words, the smaller number of scan F / Fs out of the number of scan F / Fs included in the internal clock domains of the preceding stage and the subsequent stage is the comparison value.

Then, the CPU 14 compares the comparison values of the two sets of the extracted internal clock domains, and if the number is not the same, sets the priority of the set of the internal clock domains having the larger comparison value, and sets the same number. If there is, the higher priority is set for the group having the smaller number of DFT circuit insertions calculated in step S109.
Also, if the number of DFT circuit insertions is the same, for example, the priority order is set based on a predetermined index such as the arrangement order of internal clock domains managed in the circuit information before DFT circuit insertion. To do. In this way, the process is repeated until the priority order is set for all the sets of internal clock domains in which the data path exists (S110).

  In accordance with the priority order determined in step S103, the CPU 14 inserts a DFT circuit for the data path connecting the preceding internal clock domain and the subsequent internal clock domain in order from the set of internal clock domains with higher priorities. (S111). Specifically, when a DFT circuit can be inserted into all of the data paths existing in the set of internal clock domains having a high priority, the data paths existing in the set of internal clock domains having the next highest priority. In contrast, a DFT circuit is inserted.

  Here, an example of the DFT circuit inserted in step S111 will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a set of internal clock domains in which a DFT circuit is inserted. The DFT circuit corresponds to a path cutoff circuit.

  FIG. 3 shows a front internal clock domain 21 and a rear internal clock domain 22 in a set of internal clock domains. The internal clock domain 21 of the frequency subgroup FSG11 includes scan F / Fs 52 and 53, and the internal clock domain 22 of the frequency subgroup FSG12 includes scan F / Fs 54 and 55. The multiplexers 31 and 32 selectively supply either the internal clock or the scan clock supply terminal SCKin to the internal clock domains 21 and 22. The selection of signals by the multiplexers 31 and 32 is performed by the test mode control signal AMC input to each.

  Here, the input terminals of the multiplexer 38, the scan F / F 51, and the scan clock signal SCK shown in FIG. 3 correspond to the DFT circuit. With this DFT circuit, it is possible to switch between conduction and interruption of data transfer in the data path connecting the internal clock domain 21 at the preceding stage and the internal clock domain 22 at the subsequent stage.

  Specifically, when the test mode control signal AMC “0” is input to the multiplexer 38, the data transfer from the internal clock domain 21 in the previous stage to the internal clock domain 22 in the subsequent stage can be conducted. When the test mode control signal AMC “1” is input to the multiplexer 38, the scan F / F 51 can block data transfer from the internal clock domain 21 at the previous stage to the internal clock domain 22 at the subsequent stage. Also, by controlling the scan clock signal SCK supplied to the scan F / F 51, an arbitrary test value stored in the scan F / F 51 can be output to the internal clock domain 22 at the subsequent stage.

When the number of inserted DFT circuits does not exceed the DFT circuit insertion upper limit value stored in the DFT circuit insertion upper limit storage area M5, the CPU 14 repeats the process of step S104 (S112: NO). Specifically, if the number of inserted DFT circuits does not exceed the upper limit of the number of DFT circuit insertions specified by the DFT circuit insertion upper limit value, the process of step S104 is repeated.
When the number of inserted DFT circuits exceeds the DFT circuit insertion upper limit value stored in the DFT circuit insertion upper limit storage area M5, the CPU 14 ends the insertion of the DFT circuit (S112: YES).

  When there are data paths connected to other internal clock domains for the internal clock domains included in the frequency group based on the frequency group information stored in the frequency group storage area M3, the CPU 14 determines all the data paths. In step S111, it is determined whether a DFT circuit is inserted. When all the data paths have DFT circuits inserted and data transfer in the data paths can be cut off, the control for selectively supplying the scan clock signal to the frequency subgroup in the frequency group It is determined that the frequency group does not require a circuit. The CPU 14 extracts a frequency group that does not require a control circuit, and stores control circuit unnecessary frequency group information indicating the frequency group in the control circuit unnecessary frequency group information storage area M6 (S113).

  Based on the control circuit unnecessary frequency group information stored in the control circuit unnecessary frequency group information storage area M6, the CPU 14 sets a signal line that supplies a scan clock signal to a frequency group that is not determined to be unnecessary. A control circuit and a scan clock supply terminal SCKin are inserted (S114). In addition, the CPU 14 inserts a scan clock supply terminal SCKin for a frequency group determined to require no control circuit.

The CPU 14 adds a multiplexer added to the working DFT circuit pre-insertion circuit information F1 based on the frequency group information stored in the frequency group storage area M3 and the frequency subgroup information stored in the frequency subgroup storage area M4. The control circuit, the scan clock supply terminal SCKin, and the internal clock domain are connected (S115).
Through the above processing, the computer 11 inserts the DFT circuit into the working DFT circuit pre-insertion circuit information F1, and generates DFT circuit post-insertion circuit information F3. The CPU 14 outputs the circuit information F3 after the DFT circuit is inserted, and stores it in the storage device 14 of the server 13 via the storage device 15 or the Internet 19 (S116).

  Next, a generation example of a circuit after DFT insertion will be described with reference to FIGS. FIG. 4 is a diagram illustrating an example of a semiconductor integrated circuit indicated by circuit information after DFT insertion generated by the semiconductor integrated circuit design system according to the first exemplary embodiment of the present invention. For comparison, FIG. 5 shows a semiconductor integrated circuit indicated by circuit information after DFT insertion generated by the technique disclosed in Patent Document 1 based on circuit information before DFT insertion in which the semiconductor integrated circuit shown in FIG. 4 is generated. It is a figure which shows an example of a circuit. The circuit after the DFT insertion shown in FIG. 5 is the same as that disclosed in Patent Document 1, and thus the description thereof is omitted.

In step S101, circuit information F1 before DFT circuit insertion is acquired.
In step S102, the internal clock domains 21 to 27 are extracted.
In step S103, multiplexers 31-37 for supplying scan clock signals are inserted into the internal clock domains 21-27, respectively.
In step S104, the DFT circuit insertion upper limit value is acquired. In step S105, test frequency information F2 is acquired.

  In step S 106, a data path for transferring data from the internal clock domain 22 to the internal clock domain 21, a data path for transferring data from the internal clock domain 23 to the internal clock domain 24, and an internal clock domain 26 to the internal clock domain 25. A data path for transferring data and a data path for transferring data from the internal clock domain 26 to the internal clock domain 27 are extracted.

  In step S107, the internal clock domains 21, 22 having the same test frequency are set as the frequency group FG1, and the internal clock domains 23, 24, 25 being the same test frequency are set as the frequency group FG2, and the internal clock having the same test frequency is set. Domains 26 and 27 are extracted as a frequency group FG3.

  In step S108, for the frequency group FG1, since the internal clock domain 21 and the internal clock domain 22 have a data path dependency, the internal clock domain 21 is extracted as the frequency subgroup FSG11 and the internal clock domain 22 is extracted as the frequency subgroup FSG12. To do. For the frequency group FG2, the internal clock domain 23 and the internal clock domain 24 have a data path dependency relationship, and the internal clock domain 24 and the internal clock domain 25 have no data path dependency relationship. As the group FSG21, the internal clock domains 24 and 25 are extracted as the frequency subgroup FSG22. Similarly, for the frequency group FG3, the internal clock domain 26 is extracted as the frequency subgroup FSG31, and the internal clock domain 27 is extracted as the frequency subgroup FSG32.

  In step S109, the internal clock domain 21 and the internal clock domain 22 having the data path dependency, the internal clock domain 23 and the internal clock domain 24, the internal clock domain 25 and the internal clock domain 26, and the internal clock domain 26 and the internal clock domain 27 For each combination, the necessary number of DFT circuit insertions is calculated.

  In step S110, the internal clock domain 21 and the internal clock domain 22 having the data path dependency, the internal clock domain 23 and the internal clock domain 24, the internal clock domain 25 and the internal clock domain 26, and the internal clock domain 26 and the internal clock domain 27 Priorities are set for each set. Here, the comparison values of the internal clock domains are set in the order of the internal clock domains 21 and 22, the internal clock domains 23 and 24, the internal clock domains 25 and 26, and the internal clock domains 26 and 27. It is assumed that the number of scan F / Fs is large, that is, the priority order is high.

In step S111, first, a DFT circuit is inserted into the data path from the internal clock domain 22 to the internal clock domain 21 having the highest priority. In step S112, the number of DFT circuit insertions is checked. If the upper limit of the number of DFT circuit insertions has not been reached, the process returns to step S111.
In the second step S111, a DFT circuit is inserted into the data path from the internal clock domain 23 to the internal clock domain 24 having the next highest priority. Then, in the second step S112, the number of DFT circuit insertions is checked. If the number of DFT circuit insertions has reached the upper limit of the number of DFT circuit insertions, the process proceeds to step S113.

  The timing for determining the number of DFT circuit insertions here is not limited to when DFT circuits are inserted for all data paths existing in a set of internal clock domains. For example, when a DFT circuit is inserted into the data path and the upper limit of the number of inserted DFT circuits is reached, the process may proceed to step S113.

Here, a DFT circuit capable of blocking data transfer in the data path is inserted for all data paths existing in the set of internal clock domains 21 and 22 and all data paths existing in the set of internal clock domains 23 and 24. Has been. Accordingly, for example, by interrupting data transfer in the data path at the time of the test, data is not transferred from the internal clock domain 22 to the internal clock domain 21, so that the internal clock domains 21 and 22 are tested in parallel. Is possible. Therefore, it is not necessary to divide these internal clock domains into test groups for performing tests separately, and selective to either the internal clock domain 21 or the internal clock domain 22, the internal clock domain 23, or the internal clock domains 24, 25. There is no need to supply a scan clock signal.
Therefore, in step S113, the frequency group FG1 including the internal clock domains 21 and 22 and the frequency group FG2 including the internal clock domains 23, 24, and 25 are used as frequency groups that do not require a control circuit that selectively supplies the scan clock signal. To extract.

  In step S114, the control circuit 41c and the scan clock supply terminal SCKin are inserted into the signal line for supplying the scan clock signal for the frequency group FG3 for which the control circuit is not determined to be unnecessary. For the frequency group FG3, a FreqSubCTL signal input control terminal and an SMC signal input control terminal are also inserted. Further, a scan clock supply terminal SCKin is inserted into the frequency groups FG1 and FG2 that are determined to be unnecessary for the control circuit.

In step S115, the scan clock supply terminal SCKin for the frequency group FG1 and the multiplexers 31 and 32 are connected. Further, the multiplexer 31 and the internal clock domain 21 are connected, and the multiplexer 32 and the internal clock domain 22 are connected.
Further, the scan clock supply terminal SCKin for the frequency group FG2 and the multiplexers 33, 34, and 35 are connected. Further, the multiplexer 33 and the internal clock domain 23 are connected, the multiplexer 34 and the internal clock domain 24 are connected, and the multiplexer 35 and the internal clock domain 25 are connected.

  Further, the control circuit 41c is connected to each of the scan clock supply terminal SCKin, the FreqSubCTL signal input control terminal, and the SMC signal input control terminal for the frequency group FG2. Further, the scan clock output terminal SCK1 of the control circuit 41c and the multiplexer 36 are connected, and the scan clock output terminal SCK2 of the control circuit 41c and the multiplexer 37 are connected. Further, the multiplexer 36 and the internal clock domain 26 are connected, and the multiplexer 37 and the internal clock domain 27 are connected. Here, the control circuit 41c selectively outputs a scan clock signal from one of the scan clock output terminals SCK1 and SCK2 in accordance with signal values input from the FreqSubCTL signal input control terminal and the SMC signal input control terminal. Circuit.

  In step S116, the post-DFT circuit insertion circuit information F3 of the semiconductor integrated circuit shown in FIG. 4 is stored in the storage device 14 or the storage device 14 of the server 13 via the Internet 19.

  The semiconductor integrated circuit shown in FIG. 4 created in this way includes a DFT circuit capable of interrupting data transfer in a data path existing in the set of internal clock domains 21 and 22 and the set of internal clock domains 23, 24, and 25. By inserting the test, it is possible to perform tests on the internal clock domains 21 and 22 and the internal clock domains 23, 24, and 25 in parallel, so that the number of test patterns can be reduced.

  Specifically, in the semiconductor integrated circuit shown in FIG. 5, as shown in FIG. 8, a first test group including internal clock domains 21, 23, and 26 so as not to have a data path dependency relationship, A test is performed by selectively supplying a scan clock signal to the second test group including the internal clock domains 22, 24, 25, and 27. Therefore, the number of test patterns of this semiconductor integrated circuit is the largest number of test patterns among the number of test patterns of the internal clock domains 21, 23, and 26 included in the first test group, and the second test group. Of the number of test patterns in each of the included internal clock domains 22, 24, 25, and 27, this is the sum of the largest number of test patterns.

  On the other hand, in the semiconductor integrated circuit shown in FIG. 4, the first test group including the internal clock domains 21, 22, 23, 24, 25, and 27, and the internal clock domain so as not to have the data path dependency relationship. 26 to a second test group.

  Here, in the first embodiment, a DFT circuit is preferentially inserted from a set of internal clock domains having a large number of scan F / Fs as a comparison value among a set of internal clock domains. That is, data transfer in the data path can be preferentially cut off from a set including an internal clock domain having a long test pattern length, so that tests can be executed in parallel. Therefore, in the semiconductor integrated circuit shown in FIG. 4, the test pattern length in the second test group including the internal clock domain 26 is the same as the test pattern length including the internal clock domains 22, 24, 25, and 27 in the semiconductor integrated circuit shown in FIG. The test pattern length in the second test group can be made shorter. In other words, the number of test patterns of the semiconductor integrated circuit shown in FIG. 4 can be made smaller than the number of test patterns of the semiconductor integrated circuit shown in FIG.

  In the semiconductor integrated circuit shown in FIG. 4, the internal clock domains 21, 22, 23, 24, 25, and 27 included in the first test group can block data transfer even in the presence of a data path, and are parallel. So that the test can be carried out. Therefore, even when the number of internal clock domains included in the first test group increases, the test pattern length is the largest among the test patterns of the internal clock domains 21, 22, 23, 24, 25, and 27. Never exceed the length.

  Therefore, according to the semiconductor integrated circuit shown in FIG. 4, the second test pattern length can be shortened without making the test pattern length in the first test group as long as possible. That is, according to the semiconductor integrated circuit shown in FIG. 4, the number of second test patterns can be reduced without increasing the number of test patterns in the first test group as much as possible.

  Therefore, the number of test patterns of the semiconductor integrated circuit shown in FIG. 4 is the largest number of test patterns among the test patterns of the internal clock domains 21, 22, 23, 24, 25, and 27 included in the first test pattern. Although this is the sum of the number of test patterns of the internal clock domain 26 included in the second test group, the number of test patterns can be reduced more than the number of test patterns of the semiconductor integrated circuit shown in FIG.

Further, since the test pattern length of the semiconductor integrated circuit shown in FIG. 4 can be made shorter than the test pattern length of the semiconductor integrated circuit shown in FIG. 5, the test value is set to the scan F / F when performing the test. In contrast, the time required for input / output can be reduced.
Further, in the semiconductor integrated circuit shown in FIG. 4, the number of control circuits 41a and 41b can be reduced as compared with the semiconductor integrated circuit shown in FIG. 5, so that the cost can be reduced.

  In the first embodiment, when the priority order is determined, if the number of scan F / Fs is the same, the DFT circuit is preferentially inserted from the set of internal clock domains with the smaller number of DFT circuit insertions. I am doing so. Therefore, even when the DFT circuit can be inserted only up to the DFT circuit insertion upper limit value, it is possible to block the data paths existing in the set for more sets of internal clock domains.

  Further, according to the first embodiment, before the DFT circuit insertion upper limit value is reached, when the DFT circuit can be inserted into the data paths existing in all the internal clock domain sets included in the semiconductor integrated circuit, Tests can be performed in parallel for all of the internal clock domains. In this case, the number of test patterns is the largest number of test patterns among all the internal clock domain test patterns, and the number of test patterns can be greatly reduced.

  Further, according to the first embodiment, an arbitrary test value is set in the scan F / F 51 of the DFT circuit and the scan clock signal SCK is controlled, so that the test value can be transferred to the internal clock domain in the subsequent stage at an arbitrary timing. Can be output. Therefore, a test pattern that can detect a stuck-at fault can be generated, and the stuck-at fault detection rate is not lowered.

  As described above, according to the first embodiment, in the semiconductor integrated circuit including the first clock domain and the second clock domain that operate at the same frequency, the first clock domain and the first clock domain A path cut-off circuit for switching conduction and cut-off of data transfer in the data path connecting the two clock domains is inserted. Therefore, since the test can be performed in parallel without selectively supplying the scan clock signal to the first clock domain and the second clock domain and performing the test individually, the number of test patterns Can be reduced.

Other embodiments of the invention.
Instead of the DFT circuit illustrated in FIG. 3, the DFT circuit illustrated in FIG. 6 may be inserted in step S111.
The OR circuit 56 illustrated in FIG. 6 corresponds to the DFT circuit. By inputting the test mode control signal AMC “1” to the OR circuit, the output of the OR circuit is fixed to “1”, and the data transfer from the internal clock domain 21 in the previous stage to the internal clock domain 22 in the subsequent stage is cut off. be able to.

Further, instead of the DFT circuit illustrated in FIG. 3, the DFT circuit illustrated in FIG. 7 may be inserted in step S111.
An AND circuit 57 and an INVERTER circuit 58 illustrated in FIG. 7 correspond to the DFT circuit. By inputting the test mode control signal AMC “1” to the INVERTER circuit, the output of the AND circuit is fixed to “0”, and the data transfer from the internal clock domain 21 in the previous stage to the internal clock domain 22 in the subsequent stage is cut off. be able to.

  As described above, in other embodiments of the invention, the DFT circuit can be configured with a smaller number of elements than the DFT circuit configured with the scan F / F illustrated in the first embodiment. The chip area can be reduced and the cost can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention. For example, as the comparison value for determining the priority order, the smaller scan F / F number of the scan F / F numbers included in each of the internal clock domains in the preceding stage and the subsequent stage is used. As long as the number of scan flip-flops included in is not limited to this. For example, the sum of the scan F / F numbers or the maximum scan F / F number may be used as the comparison value.

  The semiconductor integrated circuit design program according to the present invention described above can be stored in various types of storage media, and can be transmitted via a communication medium. Here, examples of the storage medium include a flexible disk, a hard disk, a magnetic disk, a magneto-optical disk, a CD-ROM (Compact Disc Read Only Memory), a DVD (Digital Versatile Disc), and a BD (Blu-ray (registered trademark) Disc. ), ROM (Read Only Memory) cartridge, RAM (Random Access Memory) with battery backup, memory cartridge, flash memory cartridge, and nonvolatile RAM cartridge. The communication medium includes a wired communication medium such as a telephone line and a wireless communication medium such as a microwave line. Moreover, the above-mentioned program can also be transmitted via the Internet.

  Further, when the computer executes the semiconductor integrated circuit design program, not only the functions of the above-described embodiments are realized, but also an OS (Operating System) or a computer running on the computer based on an instruction of the program. The case where the functions of the above-described embodiment are realized in cooperation with application software is also included in the embodiment of the invention.

  Furthermore, when all or part of the processing of the semiconductor integrated circuit design program is performed by a function expansion board inserted into the computer or a function expansion unit connected to the computer, the functions of the above-described embodiments may be realized. It is contained in embodiment of invention.

10 Semiconductor Integrated Circuit Design System 11, 12 Computer 13 Server 14, 16 CPU
15, 17, 18 Storage device 19 Internet 21, 22, 23, 24, 25, 26, 27 Internal clock domain 31, 32, 33, 34, 35, 36, 37, 38 Multiplexer 41a, 41b, 41c Control circuit 51, 52, 53, 54, 55 Scan flip-flop 56 OR circuit 57 AND circuit 58 INVERTER circuit F1 DFT circuit pre-insertion circuit information F2 Test frequency information F3 DFT circuit post-insertion circuit information M1 Test frequency storage area M2 Data path dependency storage area M3 Frequency group storage area M4 Frequency subgroup storage area M5 DFT circuit insertion upper limit storage area M6 Control circuit unnecessary frequency group information storage areas FG1, FG2, FG3, FG101, FG102, FG103 Frequency groups FSG11, FSG12, FS G21, FSG22, FSG31, FSG32, FSG111, FSG112, FSG121, FSG122, FSG131, FSG132 Frequency subgroup AMC Test mode control signal SMC Scan mode control signal FreqSubCTL Frequency subgroup selection signal SCK Scan clock signal SCK1, SCK2 Scan clock output terminal SCKin Scan clock supply pin

Claims (12)

A first clock domain;
A second clock domain that operates at the same frequency as the first clock domain and is connected to the first clock domain by a data path;
A semiconductor integrated circuit comprising: a path cutoff circuit that switches conduction and interruption of data transfer in the data path. The semiconductor integrated circuit has a plurality of sets of the first and second clock domains,
The number of the path cutoff circuits corresponding to the number of scan flip-flops included in the first and second clock domain sets is provided for the first and second clock domain sets. The semiconductor integrated circuit as described.   The path cutoff circuit has a path cutoff circuit preferentially with respect to the set of the first and second clock domains in which the smaller number of scan flip-flops among the first and second clock domains is larger. Item 3. The semiconductor integrated circuit according to Item 2.   The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit has a number of path cutoff circuits not exceeding an upper limit number of arbitrary path cutoff circuits.   When the semiconductor integrated circuit does not have a path blocking circuit for all data paths connecting the first and second clock domains, the semiconductor integrated circuit selectively scans to either the first or second clock domain. 5. The semiconductor integrated circuit according to claim 2, further comprising a control circuit that supplies a clock signal.   6. The semiconductor according to claim 1, wherein the plurality of first and second clock domain sets includes one that operates at a different frequency for each of the first and second clock domain sets. Integrated circuit.   The semiconductor integrated circuit according to claim 1, wherein the path cutoff circuit includes a scan flip-flop, and the data path is shut off by the scan flip-flop.   7. The semiconductor integrated circuit according to claim 1, wherein the path cut-off circuit switches between conduction and cut-off of the data transfer by an OR circuit, an AND circuit, and an INVERTER circuit. A method of designing a semiconductor integrated circuit executed by a computer,
Read circuit information and frequency information from the storage unit, detect a data path connecting the first clock domain and the second clock domain operating at the same frequency as the first clock domain,
A method for designing a semiconductor integrated circuit, wherein a path blocking circuit for switching conduction and blocking of data transfer in the detected data path is inserted. In the detection of the data path, a data path is detected for a plurality of sets of the first and second clock domains,
Further, out of the number of scan flip-flops included in each of the first and second clock domains, the smaller number of scan flip-flops is calculated,
10. The semiconductor integrated circuit design according to claim 9, wherein in inserting the path cutoff circuit, a path cutoff circuit is inserted preferentially with respect to the set of the first and second clock domains having a large number of the calculated scan flip-flops. Method. Processing for reading circuit information and frequency information from the storage unit and detecting a data path connecting the first clock domain and the second clock domain operating at the same frequency as the first clock domain;
A semiconductor integrated circuit design program for causing a computer to execute a process of inserting a path blocking circuit for switching conduction and blocking of data transfer in the detected data path. In the process of detecting the data path, a data path is detected for a plurality of sets of the first and second clock domains,
Further, a process of calculating a smaller number of scan flip-flops among the number of scan flip-flops included in each of the first and second clock domains is performed,
12. The semiconductor integrated circuit according to claim 11, wherein in the process of inserting the path cutoff circuit, a path cutoff circuit is inserted preferentially with respect to the set of the first and second clock domains having a large number of the calculated scan flip-flops. Circuit design program.

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