JP2011099734A - Impact detecting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an impact detecting device acquiring the degree of an impact while saving on power by keeping down the amount of data and the frequency of data processing, the device having a simple circuit configuration dispensing with any A/D converter. <P>SOLUTION: This impact detecting device 1 is equipped with: an acceleration sensor element 11, a capacitor 20 for step integration, an operational amplifier 18, a recording circuit 6, and an FET 22 for electric charge resetting. The sensor element 11 outputs an impact detection value that changes depending on the degree of impact. Electric charge corresponding to the detection value is stored in the capacitor 20. The quantity of electric charge stored in the capacitor 20 having reached a stipulated value cause an output of the operational amplifier 18 to change. A real time clock is recorded in the recording circuit 6 when the output of the operational amplifier 18 is changed. The quantity of electric charge stored in the capacitor 20 is reset by the FET 22 when the output of the operational amplifier 18 is changed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an impact detection apparatus that performs predetermined processing based on an impact detection value that detects the degree of impact.

  An impact detection device is used to detect the degree of vibration and impact that an article receives during transportation. Since a general impact detection device is used when an article is transported, a portable battery is used for a power supply circuit. In the impact detection device, an impact detection value (specifically, acceleration or the like) is detected by a sensor, and an output signal of the sensor is sampled and recorded at a predetermined sampling rate. Since the impact is generated with a time width of several tens of millimeters SEC to several seconds, the impact detection device requires a time resolution of about 1/10 of the time width of the impact. For this reason, the amount of data to be recorded increases depending on the sampling rate, and the memory capacity may become a problem. In addition, since high-speed data processing is required and the frequency of data processing increases, power consumption required for data processing becomes excessive, and battery capacity may become a problem.

  Therefore, by using an impact detection device that records only the impact detection value that is larger than a certain level and the impact detection value, the amount of data and the frequency of data processing may be suppressed to save power ( For example, see Patent Document 1.)

FIG. 1 is a block diagram of a configuration example of a conventional impact detection device with reference to Patent Document 1. In FIG.
The impact detection apparatus 101 includes an arithmetic processing unit 102, an impact detector 103, a filter 104, an amplifier 105, a peak hold unit 106, an A / D converter 107, a comparator 108, and a power supply circuit 109. The power supply circuit 109 supplies power to the arithmetic processing unit 102 and the A / D converter 107 when the power switch is turned on. The impact detector 103 receives an impact and outputs an impact detection signal. The filter 104 removes noise components from the impact detection signal. The amplifier 105 amplifies the impact detection signal. The peak hold unit 106 stores the peak value of the impact detection signal. The A / D converter 107 converts the peak value of the impact detection signal from analog data to digital data. The comparator 108 outputs a trigger signal when an impact detection signal exceeding the threshold level is input. The arithmetic processing unit 102 records the generation time of the trigger signal and the digital data in the memory.

JP-A-1-265165

  As in the impact detection device of Patent Literature 1, holding the impact detection value can suppress the data amount and the data processing frequency. However, this impact detection device requires a peak hold circuit and an A / D converter, which complicates the circuit configuration and hinders power saving. In addition, the accuracy of the data may deteriorate due to the performance of the A / D converter. For example, if the time resolution of the A / D converter is low, there may be a case where only one peak value can be acquired even if multiple impacts occur at extremely short time intervals.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an impact detection device having a simple circuit configuration that can grasp the degree of impact while suppressing power consumption by suppressing the amount of data and the data processing frequency, and does not require an A / D converter. To do.

  The impact detection device of the present invention includes an impact detection unit, a power storage unit, a charge level determination unit, a time measurement processing unit, and a charge level control unit. The impact detection unit outputs an impact detection value that changes according to the degree of impact. The power storage unit stores a charge corresponding to the impact detection value. The output of the charge level determination unit changes when the amount of charge stored in the power storage unit reaches a specified value. The timing processing unit records the value of the real-time clock when the output of the charge level determination unit changes. The charge level control unit resets the amount of charge stored in the power storage unit when the output of the charge level determination unit changes.

  In this configuration, the power storage unit stores the amount of power stored by integrating the impact detection value. Then, the time interval at which the stored amount of electricity becomes the specified value is recorded by the time measuring processor. Therefore, it becomes possible to grasp the degree of impact from this time interval. The timing processing unit only needs to know the recording timing of the real-time clock value from the output of the charge level determination unit, and does not require an A / D converter. Therefore, the circuit configuration can be simplified and power saving can be promoted.

  In the impact detection device of the present invention, it is preferable that at least the timing processing unit is intermittently operated, and the transition from the sleep state to the active state is caused by the occurrence of an impact greater than a predetermined level. With this configuration, it is possible to further reduce power consumption by suppressing the data amount and the data processing frequency.

  According to this invention, the impact detection value of the generated impact is integrated, and the time interval at which the integration amount becomes a predetermined amount is recorded. Since the impact detection value is not recorded as in the prior art, an A / D converter is not required, and a simple circuit configuration can be used to save power. Further, it is not necessary to perform complicated data processing, and it is possible to grasp the degree of impact that occurs while reducing the amount of data and the frequency of data processing and saving power.

It is a schematic circuit diagram of the impact detection apparatus which concerns on a prior art example. It is a figure explaining the schematic structural example of the impact detection apparatus which concerns on the 1st Embodiment of this invention. It is a figure explaining the schematic structural example of the impact detection circuit with which the impact detection apparatus of FIG. 2 is provided. It is a figure explaining the schematic structural example of the full wave rectifier circuit with which the impact detection apparatus of FIG. 2 is provided. It is a figure explaining the schematic structural example of the step integration circuit with which the impact detection apparatus of FIG. 2 is provided. It is a figure explaining the schematic structural example of the impact detection apparatus which concerns on the 2nd Embodiment of this invention.

The impact detection device according to the first embodiment of the present invention will be described below.
FIG. 2 is a diagram illustrating a schematic configuration example of the impact detection device 1.
The impact detection device 1 includes an impact detection circuit 3, a full-wave rectification circuit 4, a step integration circuit 5, a recording circuit 6, an RTC (Real Time Clock) unit 7, and a battery 8.

  The battery 8 supplies a power supply voltage Vcc to each part. The RTC unit 7 measures the value of the real time clock RTC.

  The impact detection circuit 3 includes an acceleration sensor (not shown), amplifies the output of the acceleration sensor, and outputs an analog detection signal Vout that changes according to the acceleration to the full-wave rectification circuit 4. Further, a binary signal Vt1 that becomes HIGH while the output of the acceleration sensor is equal to or higher than a predetermined level is output to the recording circuit 6.

  The full wave rectification circuit 4 performs full wave rectification on the analog detection signal Vout input from the shock detection circuit 3.

  The step integration circuit 5 stores electric charge based on the analog detection signal Vout input from the full-wave rectification circuit 4, resets the electric storage when the electric charge reaches the threshold level, and goes to the HIGH level at the moment of resetting the electric storage. The binary signal (pulse signal) Vt2 is output to the recording circuit 6.

  The recording circuit 6 is a timing processing unit of the present invention, and is configured to intermittently operate in a sleep state and an active state. In the active state, the binary signal Vt2 output from the step integration circuit 5 rises to a high level. As a trigger, the value of the real-time clock RTC is recorded in the memory. The recording circuit 6 in the sleep state starts rising to the active state when the binary signal Vt1 output from the impact detection circuit 3 becomes HIGH level. In order for the recording circuit 6 to shift from the active state to the sleep state, the binary signal Vt1 output from the impact detection unit 2 is at the LOW level for a certain period of time, or a certain period of time has elapsed since the activation of the active state. It is preferable to make these conditions. By performing the intermittent operation in this way, the amount of data processed by the recording circuit 6 and the data processing frequency can be suppressed, and power saving can be promoted.

FIG. 3A is a diagram illustrating a schematic configuration example of the impact detection circuit 3.
The impact detection circuit 3 includes an acceleration sensor element 11, operational amplifiers 12 and 13, and an FET 14. The acceleration sensor element 11 outputs an impact detection value that changes according to the acceleration generated by the impact. The operational amplifiers 12 and 13 each constitute an operation amplification circuit that also serves as a low-pass filter, and outputs an analog detection signal Vout obtained by amplifying the impact detection value of the acceleration sensor element 11. The FET 14 outputs a binary signal Vt1 that becomes HIGH while the impact detection value of the acceleration sensor element 11 exceeds a predetermined level. FIG. 3B is a diagram illustrating the waveform of the analog detection signal Vout output from the impact detection circuit 3.

FIG. 4A is a diagram illustrating a schematic configuration example of the full-wave rectifier circuit 4.
The full-wave rectifier circuit 4 includes operational amplifiers 15 and 16. The operational amplifier 15 constitutes an inverting half-wave rectifier circuit. When the input voltage to the full-wave rectifier circuit 4 is positive, the output voltage is inverted, and when the input voltage is negative, the output voltage is zero. The operational amplifier 16 constitutes an inverting type / adder circuit, adds the input voltage to the full-wave rectifier circuit 4 and the output voltage of the operational amplifier 15 at a ratio of 1: 2, inverts and outputs the result. As a result, the full-wave rectified analog detection signal Vout is output from the full-wave rectifier circuit 4. FIG. 4B is a diagram illustrating the waveform of the analog detection signal Vout output from the full-wave rectifier circuit 4.

FIG. 5A is a diagram for explaining a schematic configuration example of the step integration circuit 5.
The step integration circuit 5 includes a charge buffer capacitor 20, a step integration capacitor 21, an operational amplifier 17, a comparator 18, a threshold level adjusting resistor 19, and a charge reset FET 22. The charge buffer capacitor 20, the step integration capacitor 21, and the operational amplifier 17 constitute a power storage unit according to the present invention, and charge stored in the charge buffer capacitor 20 by the analog detection signal Vout input from the full-wave rectifier circuit 4. Then, it is added to the step integration capacitor 21 and stored. The comparator 18 and the threshold level adjustment resistor 19 constitute a charge level determination unit of the present invention, and the charge voltage of the step integration capacitor 21 is compared with a reference voltage determined by the threshold level adjustment resistor 19, and the step integration capacitor 21. A binary signal Vt2 that goes high while the charge voltage of is higher than a predetermined level is output. The charge reset FET 22 corresponds to the charge level control unit of the present invention, and is turned on when the binary signal Vt2 is inputted to the gate and the binary signal Vt2 becomes HIGH level, and both ends of the step integration capacitor 21 are short-circuited. Let As a result, when the binary signal Vt2 becomes HIGH level, the charge of the step integration capacitor 21 is reset, and the binary signal Vt2 becomes LOW level again. FIG. 5B is a diagram illustrating the waveform of the charge voltage Va of the step integration capacitor 21, and FIG. 5C is a diagram illustrating the waveform of the binary signal Vt 2 output from the step integration circuit 5.

  With the above configuration, in the impact detection device 1, the stored charge amount obtained by integrating the output of the impact detection circuit 3 is stored in the staircase integration circuit 5, and the pulse signal Vt2 that becomes HIGH when the stored charge amount is reset to a specified value. Is output. In the recording circuit 6, the real time clock RTC is recorded at the timing when the pulse signal Vt2 rises. Therefore, the recording circuit 6 does not record the analog detection signal Vout of the shock detection circuit 3 or the full-wave rectification circuit 4 as it is, and does not require an A / D converter, so that the circuit configuration can be simplified.

  From the value of the real-time clock RTC recorded in the memory, it is possible to grasp the time interval at which the charged amount becomes the specified value. This time interval is equivalent to the time interval from when the impact detection unit 2 detects an impact until the output integrated amount of the impact detection circuit 3 reaches a specified value. Therefore, it can be understood that if the time interval is wide, the degree of vibration is moderate, and if the time interval is narrow, the degree of vibration is severe.

  The impact detection device 1 can grasp the degree of impact with a simple circuit configuration that does not require an A / D converter, and can suppress the amount of data recorded in the memory, the data processing frequency, and the power consumption of the entire device.

  The present invention can be implemented with various other configurations of the above-described embodiments. For example, a sensor may be provided separately from the impact detection circuit 3, and the binary signal Vt1 may be acquired by causing the sensor to detect an impact. Further, the configuration for acquiring the binary signal Vt1 may be omitted, and the recording circuit 6 may always be normally operated. The recording circuit may be configured to transmit data via the communication circuit without performing recording in the memory. The present invention can be suitably implemented by using a circuit configuration that can grasp at least a certain amount of charge stored based on the impact detection signal and the time interval for storing the charge.

Next, an impact detection apparatus according to a second embodiment of the present invention will be described.
FIG. 6 is a diagram illustrating a schematic configuration example of the impact detection device 31. The impact detection device 31 includes an impact presence / absence detection unit 32 and an intermittent operation control unit 33 in addition to the same configuration as the impact detection device 1 described above. The impact presence / absence detection unit 32 uses an acceleration sensor with lower accuracy and lower power consumption than the impact detection circuit 3, and outputs a binary signal Vt 1 instead of the impact detection circuit 3. The battery 8 directly supplies operating power to the intermittent operation control unit 33, the impact presence / absence detection unit 32, the RTC unit 7, and the recording circuit 6, and the impact detection circuit 3, the full-wave rectification circuit 4, and the step integration circuit. 5 is indirectly supplied with operating power via the intermittent operation control unit 33. The intermittent operation control unit 33 supplies the power supply voltage Vcc to the impact detection circuit 3, the full-wave rectification circuit 4, and the period in synchronization with the period in which the recording circuit 6 is activated by the binary signal Vt 1 from the impact presence / absence detection unit 32. This is supplied to the step integration circuit 5.

  Even with such a configuration, the present invention can be suitably implemented. With this configuration, the impact detection circuit 3, the full-wave rectification circuit 4, and the step integration circuit 5 are also intermittently operated to further advance power saving. Is possible.

DESCRIPTION OF SYMBOLS 1 ... Impact detection apparatus 2 ... Impact detection part 3 ... Impact detection circuit 4 ... Full wave rectification circuit 5 ... Stair integration circuit 6 ... Recording circuit 7 ... RTC part 8 ... Battery 11 ... Acceleration sensor element 12, 13, 15, 16, 17, 18 ... operational amplifier 14 ... FET
DESCRIPTION OF SYMBOLS 19 ... Resistor for threshold level adjustment 20 ... Capacitor for charge buffer 21 ... Capacitor for step integration 22 ... FET for charge reset

Claims (2)

An impact detector that outputs an impact detection value that changes according to the degree of impact;
A power storage unit that stores electric charge according to the impact detection value;
A charge level determination unit whose output changes when the amount of charge stored in the power storage unit reaches a specified value;
A clock processing unit for recording a real-time clock when the output of the charge level determination unit changes; and
An impact detection apparatus comprising: a charge level control unit that resets an amount of charge stored in the power storage unit when the output of the charge level determination unit changes.   The impact detection apparatus according to claim 1, wherein at least the timing processing unit is intermittently operated to shift from a sleep state to an active state when an impact greater than a predetermined level occurs.

Images