JP2011097021A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the withstand voltage, regardless of whether there are dumps and dips formed by deep recess parts. <P>SOLUTION: At a position adjacent to an embedded insulating film 4 in an active layer 3 under a semiconductor element, a ring-shaped p-type region 10 and a ring-shaped n-type region 11 are alternately formed in a repeated manner so as to surround a circular center region 10a. As a result of this, when an anode electrode 9 and a support substrate 2 are connected to GND as well as a high voltage is applied to a cathode 8, charges are induced at a position adjacent to the embedded insulating film 4 in the p-type region 10, arranged between the n-type regions 11, but charges are not induced in a position adjacent to the embedded insulating film 4 in the n-type region 11. Accordingly, it is possible to constitute a pseudo-field plate, and the breakdown voltage can be improved. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor element is formed using an SOI (Silicon on insulator) substrate and a manufacturing method thereof.

  Conventionally, there is a semiconductor device in which a semiconductor element is formed using an SOI substrate in which a support substrate and an active layer are bonded together through a buried insulating film. In this semiconductor device, the support substrate is fixed at a predetermined potential (for example, GND) during use, but when a high voltage is applied to a desired portion of the active layer with the support substrate fixed at a predetermined voltage, the support substrate is embedded in the active layer. Electric charges are induced in a portion adjacent to the buried insulating film, and an inversion layer is formed. This causes a problem that electric field concentration occurs and the breakdown voltage is lowered. This problem will be described with reference to FIG.

FIG. 22 is a cross-sectional view showing an equipotential distribution of a semiconductor device in which a lateral PN diode is formed on the SOI substrate J1. When a high voltage is applied to the cathode electrode J2 of the PN diode and the anode electrode J3 is set to GND, an inversion layer is formed by the + charges induced in the active layer J4 adjacent to the buried insulating film J5. The As a result, the equipotential lines are narrowed between the n ⁺ -type cathode region J6 and the buried insulating film J5. For this reason, electric field concentration occurs in this portion, and the breakdown voltage is lowered.

  In order to prevent such a decrease in breakdown voltage, Patent Document 1 proposes a semiconductor device in which the surface of a buried insulating film has an uneven shape. FIG. 23 is a diagram showing a cross-sectional structure of this semiconductor device. As shown in this figure, a recess J5a and a protrusion J5b are formed in the buried insulating film J5, and a pseudo field plate is formed by localizing + charges in the recess J5a. By forming such a pseudo field plate, equipotential lines are distributed in the vertical direction toward the convex portion J5b. For this reason, the interval between equipotential lines is corrected and the breakdown voltage can be improved.

Japanese Patent No. 3959125

  However, when forming a concave and convex embedded insulating film, various steps are required to form the concave and convex portion, and there is a problem that the manufacturing process is difficult. Specifically, before bonding the silicon substrate constituting the active layer to the support substrate, the concave-convex forming step for forming the concave-convex shape on the back surface of the silicon substrate by performing photo-etching on the back surface of the silicon substrate to form a concave portion In addition, it is necessary to perform an insulating film forming step for forming an insulating film on the uneven surface and a flattening step for flattening the surface of the insulating film. In order to localize the electric charges in the recesses, the recesses having a certain depth must be formed in the unevenness forming process, and the insulating film is thick enough to be embedded in the insulating film forming process. A film must be formed. Furthermore, regarding the planarization process, the thick insulating film must be planarized. Therefore, the manufacturing process of the semiconductor device becomes complicated and the difficulty becomes high.

  In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the withstand voltage even if there is no unevenness constituted by deep recesses.

  In order to achieve the above object, according to the first aspect of the present invention, the active layer (3) has a layout corresponding to the semiconductor element on the buried insulating film (4) side, and is formed in the surface layer portion. Second conductivity type regions (10) alternately and repeatedly formed in the direction from the first impurity layer (5, 77, 88) to the second impurity layer (6, 71, 81), and the active layer (3) The first conductivity type region (11) having a higher concentration is provided in one element isolation region surrounded by the element isolation structure in the active layer (3).

  In such a semiconductor device, the second conductivity type region (10) has the first conductivity type region (11) at a position adjacent to the buried insulating film (4) below the semiconductor element in the active layer (3). By sandwiching, it becomes a structure arranged at a predetermined interval. For this reason, an electric charge is induced at a position adjacent to the buried insulating film (4) in the second conductivity type region (10). That is, no charge is induced in the first conductivity type region (11) adjacent to the buried insulating film (4), and the inversion layer can be localized in the second conductivity type region (10). . For this reason, a pseudo field plate can be formed, and a voltage drop can be evenly generated in accordance with the interval between the first conductivity type regions (11) below the active layer (3).

  In the invention according to claim 2, a radial layout corresponding to the semiconductor element is formed on the surface of the active layer (3) which is bonded to the buried insulating film (4), and is alternately and repeatedly formed. Further, a pseudo field plate including the second conductivity type region (10) and the first conductivity type region (11) is provided.

  Even in such a semiconductor device, the second conductivity type region (10) forms the first conductivity type region (11) at a position adjacent to the buried insulating film (4) below the semiconductor element in the active layer (3). By sandwiching, it becomes a structure arranged at a predetermined interval. For this reason, an electric charge is induced at a position adjacent to the buried insulating film (4) in the second conductivity type region (10). That is, no charge is induced in the first conductivity type region (11) adjacent to the buried insulating film (4), and the inversion layer can be localized in the second conductivity type region (10). . For this reason, a pseudo field plate can be formed, and a voltage drop can be evenly generated in accordance with the interval between the first conductivity type regions (11) below the active layer (3).

  Thus, the equipotential lines are distributed so as to extend in the vertical direction toward the first conductivity type region (11), and the interval between the equipotential lines is corrected and the breakdown voltage can be improved. Therefore, a semiconductor device that can improve the withstand voltage can be obtained without the unevenness formed by the deep recesses.

  In the invention described in claim 3, a trench isolation structure (20) reaching the buried insulating film (4) from the surface of the active layer (3) is provided. A pseudo field plate composed of the second conductivity type region (10) and the first conductivity type region (11) is surrounded.

  Thus, by surrounding the semiconductor element with the trench isolation structure (20), it is possible to isolate the element from elements formed in other regions of the active layer (3). This makes it possible to integrate the semiconductor element with another circuit element such as a logic circuit on one chip.

  In the invention described in claim 4, a spiral resistance field plate (30) or a radial capacitive field plate (40) corresponding to the semiconductor element is provided on the semiconductor element in the active layer (3). It is characterized by having.

  As described above, the resistance field plate (30) or the capacitance field plate (40) is provided not only below the active layer (3) but also above the active layer (3), so that it is vertically directed toward the first conductivity type region (11). The width of equipotential lines distributed so as to extend in the direction is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  In the fifth aspect of the present invention, a SIPOS layer (50) composed of Poly-Si having higher resistance than the active layer (3) is provided between the active layer (3) and the buried insulating film (4). ) Is provided.

  As described above, when the SIPOS film (50) is provided, the SIPOS film (50) functions as a semi-insulating layer (high resistance layer). Therefore, due to the internal resistance of the SIPOS film (50), below the active layer (3). Further, it is possible to cause a voltage drop to uniformly occur between the high voltage side and the low voltage side according to the distance. For this reason, the width of the equipotential lines distributed so as to extend in the vertical direction toward the first conductivity type region (11) is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  The invention according to claim 6 is characterized in that a charge storage layer (60) having a layout corresponding to the first conductivity type region (11) is provided in the buried insulating film (4). Yes.

  By providing such a charge storage layer (60), the charge can be induced below the first conductivity type region (11) by the charge stored in the charge storage layer (60). For this reason, the width of the equipotential lines distributed so as to extend in the vertical direction toward the first conductivity type region (11) is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  For example, as described in claim 7, when the first conductivity type region (11) is an n-type region, + charge may be stored in the charge storage layer (60).

  The invention according to claim 8 is characterized in that a concave-convex shape including a concave portion (4a) and a convex portion (4b) is formed on the surface of the embedded insulating film (4) on the support substrate (2) side. It is said.

  In the semiconductor device having such a structure, the thickness of the buried insulating film (4) is increased in the portion of the buried insulating film (4) that is the protrusion (4b). As a result, in the portion of the support substrate (2) corresponding to the recess (4a) of the buried insulating film (4), the thickness of the buried insulating film (4) is reduced, so that charges are easily induced. In the portion of the support substrate (2) corresponding to the convex portion (4b) of the embedded insulating film (4), the thickness of the embedded insulating film (4) is thick, and thus electric charges are hardly induced. For this reason, the width of the equipotential lines distributed so as to extend in the vertical direction toward the first conductivity type region (11) is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  According to the ninth aspect of the present invention, the surface of the buried insulating film (4) on the side of the active layer (3) is formed with a concave / convex shape including the concave portion (4a) and the convex portion (4b). The conductive type region (10) is disposed in the concave portion (4a), and the first conductive type region (11) is disposed on the convex portion (4b).

  With such a structure, with respect to the thickness of the buried insulating film (4), the thickness of the first conductive type from the support substrate (2) is larger than the thickness between the support substrate (2) and the second conductive type region (10). The thickness up to the region (11) becomes thicker. For this reason, it is further difficult to induce charges in a portion of the first conductivity type region (11) adjacent to the buried insulating film (4). As a result, the width of the equipotential lines distributed so as to extend in the vertical direction toward the first conductivity type region (11) is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  The invention according to claim 10 is characterized in that the pseudo field plate including the second conductivity type region (10) and the first conductivity type region (11) is formed in the entire region corresponding to the semiconductor element. It is said.

  As described above, it is preferable that the pseudo field plate including the second conductivity type region (10) and the first conductivity type region (11) is formed in the entire region corresponding to the semiconductor element, but partially formed. It does not matter even if it is not done.

  As a semiconductor element provided in the semiconductor device having the above structure, one having various structures can be applied.

  For example, as described in claim 11, as a semiconductor element, the first conductivity type cathode region (5) corresponding to the first impurity layer formed in the surface layer portion of the active layer (3) and the second impurity layer are provided. A corresponding second conductivity type anode region (6), a cathode electrode (8) electrically connected to the cathode region (5), and an anode electrode (9) electrically connected to the anode region (6) A PN diode having a layout in which the cathode region (5) is surrounded by the anode region (6) can be applied. In this case, the pseudo field plate composed of the second conductivity type region (10) and the first conductivity type region (11) also has a position corresponding to the cathode region (5) as the center region (10a). ).

  According to a twelfth aspect of the present invention, as a semiconductor element, a channel layer (70) of the second conductivity type formed in the surface layer portion of the active layer (3), and the channel layer (70) in the channel layer (70) 70) and a first conductivity type source region (71) corresponding to the second impurity layer formed in the surface layer portion, and a first layer formed separately from the channel layer (70) in the surface layer portion of the active layer (3). A portion of the surface of the first conductivity type drain region (77) corresponding to one impurity layer and the channel layer (70) located between the active layer (3) and the source region (71) is a channel region (73). ) As a gate electrode (75) provided on the channel region (73) via a gate insulating film (74), and a source electrode electrically connected to the source region (71) and the channel layer (70). (76) and the drain region (7 And a drain electrode (78) electrically connected to each other, and an LDMOS having a layout in which the drain region (77) is surrounded by the source region (71) and the channel region (70) can also be applied. . In this case, the pseudo field plate composed of the second conductivity type region (10) and the first conductivity type region (11) also has a position corresponding to the drain region (77) as the center region (10a). ).

  Further, as described in claim 13, as a semiconductor element, a base region (80) of a second conductivity type formed in a surface layer portion of the active layer (3), and the base region (80) in the base region (80) 80) the first conductivity type emitter region (81) corresponding to the second impurity layer formed in the surface layer portion, and the first layer formed in the surface layer portion of the active layer (3) apart from the base region (80). A portion of the surface of the base region (80) between the active layer (3) and the emitter region (81) of the second conductivity type collector region (88) corresponding to one impurity layer is defined as a channel region (83). ) And a gate electrode (85) provided on the channel region (83) via a gate insulating film (84), and an emitter electrode electrically connected to the emitter region (81) and the base region (80). (86) and collector An IGBT having a collector electrode (89) electrically connected to the region (88) and having a layout surrounding the collector region (88) in the emitter region (81) and the base region (80) is applied. You can also Also in this case, the pseudo field plate composed of the second conductivity type region (10) and the first conductivity type region (11) also has a position corresponding to the collector region (88) as the center region (10a). A layout surrounding (10a) can be obtained.

  With regard to the semiconductor device described in the first to thirteenth aspects described above, for example, as described in the fourteenth aspect, a step of preparing a first conductivity type silicon substrate (12) and a surface of the silicon substrate (12) are provided. A step of forming a pseudo field plate having a radial layout centered on a predetermined location (10a) and consisting of second conductivity type regions (10) and first conductivity type regions (11) that are alternately repeated. And the silicon substrate (12) on which the pseudo field plate is formed and the support substrate (2), and the surface of the silicon substrate (12) on which the pseudo field plate is formed is on the support substrate (2) side. And a step of bonding through the buried insulating film (4) and a pseudo field of the silicon substrate (12) bonded to the support substrate (2). The step of forming the active layer (3) made of silicon by removing the surface opposite to the surface on which the rate is formed, and the opposite of the active insulating layer (3) to the buried insulating film (4) The first impurity layer (5, 77, 88) and the second impurity layer (6, 71, 81) correspond to the first impurity layer (5 , 77, 88), and forming a semiconductor element having a top layout in which the second impurity layer (6, 71, 81) is radially surrounded around the periphery. it can.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a top surface layout and a bottom surface layout of the semiconductor device illustrated in FIG. 1. (A) is sectional drawing which showed equipotential distribution of the semiconductor device shown in FIG. 1, (b) is the expanded sectional view which showed typically a mode that the electric charge was induced. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 2 is a layout diagram illustrating an example of a wiring lead structure of the semiconductor device illustrated in FIG. 1. It is sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. FIG. 7 is a diagram showing a top layout and a bottom layout of the semiconductor device shown in FIG. 6. It is sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. FIG. 9 is a diagram illustrating a top surface layout and a bottom surface layout of the semiconductor device illustrated in FIG. 8. It is sectional drawing of the semiconductor device concerning 4th Embodiment of this invention. It is the figure which showed the upper surface layout and bottom surface layout of the semiconductor device shown in FIG. It is sectional drawing of the semiconductor device concerning 5th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 6th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 7th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 8th Embodiment of this invention. It is sectional drawing of the semiconductor device demonstrated in other embodiment of this invention. It is sectional drawing of the semiconductor device demonstrated in other embodiment of this invention. It is sectional drawing of the semiconductor device demonstrated in other embodiment of this invention. It is sectional drawing of the semiconductor device provided with LDMOS demonstrated in other embodiment of this invention. It is sectional drawing of the semiconductor device provided with IGBT demonstrated by other embodiment of this invention. It is sectional drawing of the semiconductor device demonstrated in other embodiment of this invention. It is sectional drawing which showed equipotential distribution in the semiconductor device which formed the lateral PN diode with respect to SOI substrate J1. It is sectional drawing of the semiconductor device which made uneven | corrugated shape the surface of the buried insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, one embodiment of the present invention is applied to a semiconductor device in which a lateral PN diode is formed as a semiconductor element. FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. FIG. 2 is a diagram showing a top layout and a bottom layout of the semiconductor device of FIG. With reference to these drawings, the semiconductor device of this embodiment will be described.

As shown in FIG. 1, the semiconductor device is configured using an SOI substrate 1. The SOI substrate 1 is formed by bonding, for example, a support substrate 2 made of a silicon substrate and an active layer 3 formed by thinning an n ⁻ type silicon substrate through a buried insulating film 4 made of an oxide film or the like. Has been. The active layer 3 is divided into a plurality of element isolation regions by the element isolation structure, and the PN diode of this embodiment is formed in one element isolation region surrounded by the element isolation structure.

The thickness of the active layer 3 is, for example, 5 to 25 μm, and an n ⁺ -type cathode region (first impurity layer) 5 formed of a diffusion layer on the surface layer portion of the active layer 3 and a p ⁺ -type anode region ( Second impurity layer) 6 is formed. The n ⁺ -type cathode region 5 has, for example, an n-type impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ and a junction depth of 0.1 to 0.5 μm. The p ⁺ -type anode region 6 has, for example, a p-type impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ and a junction depth of 0.1 to 1.0 μm. The n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6 are formed from the n ⁺ -type cathode region 5 around the n ⁺ -type cathode region 5 formed in a circular shape, as shown in the top layout of FIG. The p ⁺ -type anode region 6 is arranged so as to surround the periphery at a position spaced apart by a predetermined interval.

A LOCOS oxide film 7 is formed on the surface of the active layer 3 between the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6. Are separated by the LOCOS oxide film 7, on the n ⁺ -type cathode region 5 is a cathode electrode 8 which is electrically connected to the n ⁺ -type cathode region 5 is formed, on the p ⁺ -type anode region 6 An anode electrode 9 electrically connected to the p ⁺ type anode region 6 is formed. The active layer 3, the n ⁺ -type cathode region 5, the p ⁺ -type anode region 6, the cathode electrode 8, and the anode electrode 9 provided in this way constitute a lateral PN diode.

A PN junction composed of a plurality of p-type regions 10 and a plurality of n-type regions 11 below the PN diode thus configured, that is, in the active layer 3 adjacent to the buried insulating film 4. The part is formed. As shown in the bottom layout of FIG. 2, the plurality of p-type regions 10 and the plurality of n-type regions 11 are formed as a central region 10a in which one of the plurality of p-type regions 10 is formed in a circular shape. The n-type region 11 and the p-type region 10 that are ring-shaped so as to surround the region are alternately arranged concentrically. In this embodiment, the p-type region 10 and the n-type region 11 have the same junction depth from the buried insulating film 4 of 1.0 to 10 μm, and the p-type region 10 has a p-type impurity concentration of 1 ×. 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ and the n-type region 11 has an n-type impurity concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ .

  As described above, the semiconductor device of this embodiment is configured. In such a semiconductor device, the ring-shaped p-type region 10 and the n-type region 11 so as to surround the circular central region 10a at a position adjacent to the buried insulating film 4 below the semiconductor element in the active layer 3. It becomes the structure where is repeatedly arranged alternately. For this reason, the following operations and effects can be achieved.

When a high voltage is applied to the cathode electrode 8 and the anode electrode 9 and the support substrate 2 are set to GND, + charge is induced at a position adjacent to the buried insulating film 4 in the p-type region 10. That is, the impurity concentration is so high that the n-type region 11 does not become an inversion layer, and no positive charge is induced in the n-type region 11 adjacent to the buried insulating film 4. The inversion layer can be localized in the part. Therefore, a pseudo field plate can be formed, and in accordance with the interval between the p-type regions 10 between the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6 below the active layer 3. Voltage drop evenly.

  In addition, when only the n-type region 11 is formed, the depletion layer from the n-type region 11 does not sufficiently spread, and a RESURF (Reduced SUrface Field) effect cannot be obtained, and an expected breakdown voltage is obtained. Although it may not be possible, since the p-type region 10 is formed, the depletion layer can be sufficiently expanded. Therefore, the expected breakdown voltage can be obtained.

  These can also be confirmed from the equipotential distribution of the semiconductor device of this embodiment. FIG. 3A is a cross section showing an equipotential distribution when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to GND in the semiconductor device of this embodiment. FIG. 3B is an enlarged cross-sectional view schematically showing a state in which charges are induced.

  As shown in FIG. 3B, since a charge is induced at a position adjacent to the buried insulating film 4 in the p-type region 10, a pseudo field plate is formed by the p-type region 10 and the n-type region 11. Is configured. Therefore, as shown in FIG. 3A, the equipotential lines are distributed so as to extend in the vertical direction toward the n-type region 11. Therefore, as in the case where the conventional buried insulating film is formed in a concavo-convex shape, the equipotential line interval is corrected, and the breakdown voltage can be improved.

  Thus, in the semiconductor device of this embodiment, the p-type region 10 and the n-type region 11 are provided in the active layer 3 at a position adjacent to the buried insulating film 4 below the semiconductor element. Accordingly, since the breakdown voltage can be improved, a semiconductor device that can improve the breakdown voltage can be obtained without the unevenness formed by the deep recesses.

  Next, a method for manufacturing the semiconductor device of the present embodiment configured as described above will be described. FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device of this embodiment. This will be described with reference to this figure.

[Step shown in FIG. 4 (a)]
First, an n ⁻ type silicon substrate 12 for forming the active layer 3 is prepared, and a mask (not shown) in which a region where a p-type region 10 is to be formed is opened on the surface of the silicon substrate 12 by photoetching. After that, p-type impurities are ion-implanted from above the mask. Subsequently, after removing the mask used for p-type impurity implantation, a mask (not shown) in which a region where the n-type region 11 is to be formed is opened is formed on the surface of the silicon substrate 12 by photoetching. An n-type impurity is ion-implanted. Then, after removing the mask, the p-type region 10 and the n-type region 11 are formed by diffusing the p-type impurity and the n-type impurity implanted by thermal diffusion.

  Note that the height of the p-type region 10 and the n-type region 11 (the distance to the farthest part from the buried insulating film 4) is determined by the amount of impurity diffusion during thermal diffusion. It is set so as not to be higher than the n-type region 11. This is because when the p-type region 10 becomes higher than the n-type region 11 and the adjacent p-type regions 10 overlap with each other above the n-type region 11, a role as a pseudo field plate cannot be expected. Because. The heights of the p-type region 10 and the n-type region 11 are set so as to reliably prevent such a state.

[Step shown in FIG. 4B]
A support substrate 2 made of, for example, a silicon substrate is bonded to the silicon substrate 12 on which the p-type region 10 and the n-type region 11 are formed via the buried insulating film 4. Thereby, the SOI substrate 1 is configured.

[Step shown in FIG. 4 (c)]
The surface of the SOI substrate 1 on the side of the silicon substrate 12 is removed by grinding or the like, and then the surface is polished by CMP (Chemical Mechanical Polishing). Thereby, the active layer 3 is constituted by the silicon substrate 12.

[Step shown in FIG. 4 (d)]
LOCOS oxidation is performed on the surface of the active layer 3 to form a LOCOS oxide film 7 in which regions where the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6 are to be formed are opened. Then, after forming a mask (not shown) in which a region where the n ⁺ -type cathode region 5 is to be formed is opened by photoetching, n-type impurities are ion-implanted from above the mask. Subsequently, after removing the mask used for n-type impurity implantation, a mask (not shown) in which a region where the p ⁺ -type anode region 6 is to be formed is opened by photoetching, and p-type impurities are removed from the mask. Ion implantation. Then, after removing the mask, the p type impurity and the n type impurity implanted by thermal diffusion are diffused to form the n ⁺ type cathode region 5 and the p ⁺ type anode region 6.

  After this, although not shown in the drawings, this embodiment shown in FIG. 1 is performed by performing well-known steps such as a step of forming an interlayer insulating film, a step of forming the cathode electrode 8 and the anode electrode 9, and a step of forming a protective film. The semiconductor device can be manufactured.

Various layouts are conceivable as the wiring drawing structure of the semiconductor device having such a configuration. For example, a layout structure as shown in FIG. 5 is preferable.
In this embodiment, the n ⁺ type cathode region 5 is surrounded by the p ⁺ type anode region 6. In such a structure, the cathode electrode 8 electrically connected to the n ⁺ -type cathode region 5 and a pad for electrical connection with the outside can be formed only on the n ⁺ -type cathode region 5. The pad layout area is reduced.

For this reason, it is preferable that the wiring lead-out structure has the layout shown in FIG. As shown in this figure, the connection portion of the anode electrode 9 with the p ⁺ type anode region 6 is formed in a U shape, and the cathode electrode 8 is connected to the p ⁺ type anode region from the inside of the U shape of the anode electrode 9. It is designed to be pulled out to the outside of 6. In other words, the anode electrode 9 is not arranged over the entire p ⁺ type anode region 6 which is circular, but the electrical connection portion with the anode electrode 9 is divided and provided above and below the p ⁺ type anode region 6. I have to. The anode electrode 9 and the cathode electrode 8 are drawn out to the outside of the region where the PN diode is formed, and are connected to the anode pad 9a and the cathode pad 8a, respectively.

With such a structure, the cathode pad 8a need not be formed only on the n ⁺ -type cathode region 5, and the arrangement area of the cathode pad 8a can be prevented from being reduced.

(Second Embodiment)
A second embodiment of the present invention will be described. The semiconductor device according to the present embodiment is a part of the first embodiment and the other configurations are the same as those of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment. FIG. 7 is a diagram showing a top layout and a bottom layout of the semiconductor device of FIG. As shown in these drawings, in the semiconductor device of this embodiment, a trench isolation structure 20 is provided so as to surround the outer periphery of the p ⁺ -type anode region 6. The trench isolation structure 20 is constituted by a groove 21 reaching from the surface of the active layer 3 to the buried insulating film 4 and an insulating film 22 formed so as to be buried in the groove 21. For example, the trench 21 is formed by etching the active layer 3 using a mask formed by photoetching, and then the trench 21 is filled with an insulating film 22 by embedding an insulating material by thermal oxidation or deposition. A trench isolation structure 20 can be formed.

  As described above, by surrounding the semiconductor element constituted by the PN diode or the like by the trench isolation structure 20, it is possible to isolate the element from elements formed in other regions of the active layer 3. As a result, even if the PN diode having the structure of the first embodiment is integrated with another circuit element such as a logic circuit on one chip, it is possible to prevent the circuit element from being affected by a high voltage. Therefore, it is possible to achieve one chip.

(Third embodiment)
A third embodiment of the present invention will be described. The semiconductor device according to the present embodiment is a part of the first embodiment and the other configurations are the same as those of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

FIG. 8 is a cross-sectional view of the semiconductor device according to the present embodiment. FIG. 9 is a diagram showing a top layout and a bottom layout of the semiconductor device of FIG. As shown in these drawings, in the semiconductor device of the present embodiment, a resistive field plate 30 is formed on a PN diode via a LOCOS oxide film 7. The resistance type field plate 30 is composed of a high resistance layer formed of non-doped Poly-Si, for example, and reaches the p ⁺ type anode region 6 by spreading spirally around the n ⁺ type cathode region 5.

In such a resistance type field plate 30, a voltage corresponding to the distance of the high resistance layer by the internal resistance of the high resistance layer between the high potential n ⁺ type cathode region 5 and the p ⁺ type anode region 6. A descent can occur. Therefore, in the radial direction around the n ⁺ -type cathode region 5, evenly voltage can be as gradually drops in accordance with the distance from the n ⁺ -type cathode region 5 up to the p ⁺ -type anode region 6.

  Therefore, by providing the resistive field plate 30 not only below the active layer 3 but also above, a high voltage is applied to the cathode electrode 8 of the PN diode, and the anode electrode 9 and the support substrate 2 are fixed to GND. In this case, the equipotential lines extending in the vertical direction from the surface of the active layer 3 toward the n-type region 11 are more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

The manufacturing method of the semiconductor device having such a structure is almost the same as that of the first embodiment, and it is only necessary to add a step of forming the resistance type field plate 30. For example, after the formation process of the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6 is completed as a formation process of the resistance type field plate 30, a high resistance layer is formed on the surface of the LOCOS oxide film 7. A process of patterning the resistive layer to form the resistive field plate 30 is performed. Thereafter, the semiconductor device according to the present embodiment can be manufactured by performing an interlayer insulating film forming process, an electrode forming process, a protective film forming process, and the like.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The semiconductor device according to the present embodiment is also a part of the first embodiment and the other configuration is the same as that of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

FIG. 10 is a cross-sectional view of the semiconductor device according to the present embodiment. FIG. 11 is a diagram showing a top layout and a bottom layout of the semiconductor device of FIG. As shown in these drawings, in the semiconductor device of this embodiment, a capacitive field plate 40 is formed on a PN diode via a LOCOS oxide film 7. Capacitive field plate 40, for example, a high resistance layer which is formed by a non-doped Poly-Si, between the n ⁺ -type cathode region 5 of the p ⁺ -type anode region 6 faces the n ⁺ -type cathode region 5 A plurality of ring-shaped high resistance layers are arranged concentrically at regular intervals with the position at the center.

In such a capacitive field plate 40, a voltage drop corresponding to the capacitance formed between the high resistance layers in the period from the high potential n ⁺ type cathode region 5 to the p ⁺ type anode region 6. Can occur. Therefore, in the radial direction around the n ⁺ -type cathode region 5, evenly voltage can be as gradually drops in accordance with the distance from the n ⁺ -type cathode region 5 up to the p ⁺ -type anode region 6.

  Therefore, by providing the capacitive field plate 40 not only below but also above the active layer 3, a high voltage is applied to the cathode electrode 8 of the PN diode, and the anode electrode 9 and the support substrate 2 are fixed to GND. In this case, the equipotential lines extending in the vertical direction from the surface of the active layer 3 toward the n-type region 11 are more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

The manufacturing method of the semiconductor device having such a structure is almost the same as that of the first embodiment, and it is only necessary to add a process for forming the capacitive field plate 40. For example, as the formation process of the capacitive field plate 40, after the formation process of the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6 is finished, a high resistance layer is formed on the surface of the LOCOS oxide film 7 and the like. A process of patterning the resistance layer to form the capacitive field plate 40 is performed. Thereafter, the semiconductor device according to the present embodiment can be manufactured by performing an interlayer insulating film forming process, an electrode forming process, a protective film forming process, and the like.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The semiconductor device according to the present embodiment is also a part of the first embodiment and the other configuration is the same as that of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, a structure in which a SIPOS (Semi-Insulating Polycrystalline Silicon) film 50 is provided between the buried insulating film 4 and the active layer 3 in the SOI substrate 1 is employed. The SIPOS film 50 functions as a semi-insulating layer (high resistance layer). Due to the internal resistance of the SIPOS film 50, the n ⁺ type cathode region 5 on the high voltage side and the p ⁺ on the low voltage side below the active layer 3. ^A voltage drop can be generated evenly with respect to the ⁺ type anode region 6 according to the distance. For this reason, when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to GND, they extend in the vertical direction from the surface of the active layer 3 toward the n-type region 11. The equipotential lines are more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

When such a SIPOS film 50 is provided, it is feared that a leak current is generated. However, providing such a SIPOS film 50, if the amount of voltage drop to the site 50a just below the ^{n +} -type cathode region 5 of the SIPOS film 50 of ^{n +} -type cathode region 5 is not formed SIPOS film 50 comparison with and larger, as compared with the case where the voltage drop amount from site 50b to ^{p +} -type anode region 6 directly below the ^{p +} -type anode region 6 of the SIPOS film 50 is not formed SIPOS film 50 and growing. For this reason, the potential difference between the portion 50 a located immediately below the n ⁺ -type cathode region 5 and the portion 50 b located directly below the p ⁺ -type anode region 6 in the SIPOS film 50 is reduced. Thereby, the effect that generation | occurrence | production of the leakage current between these can be suppressed can also be acquired.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. The semiconductor device according to the present embodiment is also a part of the first embodiment and the other configuration is the same as that of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in the present embodiment, the charge storage layer 60 is provided in the buried insulating film 4. The charge storage layer 60 is a layer in which + charges are stored, and is formed below the n-type region 11 so as to face the n-type region 11. That is, the charge storage layer 60 has a structure in which a plurality of ring-shaped layers are arranged concentrically like the n-type region 11.

  By providing such a charge storage layer 60, −charges can be induced below the n-type region 11 by + charges stored by the charge storage layer 60. For this reason, it is possible to more reliably prevent + charges from being induced below the n-type region 11, and a state in which + charges are induced only in the p-type region 10 can be achieved. Thereby, when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to GND, the surface extends from the surface of the active layer 3 toward the n-type region 11 in the vertical direction. The equipotential lines are more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

The semiconductor device manufacturing method having such a structure differs from the first embodiment in the process of forming the buried insulating film 4 and the charge storage layer 60 and the process of storing charges in the charge storage layer 60. Others are the same. In the step of forming the buried insulating film 4 and the charge storage layer 60, a step of forming a part of the buried insulating film 4 on the surface of the silicon substrate 12 on which the p-type region 10 and the n-type region 11 are formed, Next, a process of forming the charge storage layer 60 by patterning after depositing Poly-Si and a process of forming the remaining part of the buried insulating film 4 so as to cover the surface of the charge storage layer 60 and the like are performed. In the step of forming the remaining portion of the buried insulating film 4, a planarization step is performed as necessary. Then, after the silicon substrate 12 is bonded to the support substrate 2 through the buried insulating film 4, the silicon substrate 12 is thinned to form the n ⁺ -type cathode region 5, the p ⁺ -type anode region 6 and the like, and then the charge. The accumulation process is performed. In the charge accumulation process, an avalanche breakdown is generated by applying a high voltage to the n ⁺ -type cathode region 5 so as to be reverse biased, and a hot carrier formed in the n-type region 11 is formed as a thin film. The insulating film 4 is injected into the charge storage layer 60 through a portion between the charge storage layer 60 and the active layer 3. Thereby, + charges can be accumulated in the charge accumulation layer 60. In this way, the semiconductor device according to the present embodiment can be manufactured.

(Seventh embodiment)
A seventh embodiment of the present invention will be described. The semiconductor device according to the present embodiment is also a part of the first embodiment and the other configuration is the same as that of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  FIG. 14 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in the present embodiment, the surface of the embedded insulating film 4 on the support substrate 2 side has an uneven shape. Specifically, a recess is formed in the support substrate 2 by photoetching, and the embedded insulating film 4 is formed so as to be embedded in the recess, so that a portion of the support substrate 2 where the recess is not formed is formed. A concave portion 4 a of the buried insulating film 4 is formed, and a convex portion 4 b of the buried insulating film 4 is formed by a portion where the concave portion of the support substrate 2 is formed. At this time, the position of the concave portion 4 a is a position facing the p-type region 10, and the position of the convex portion 4 b is a position facing the n-type region 11. Then, after planarizing the buried insulating film 4 as necessary, the silicon substrate 12 on which the p-type region 10 and the n-type region 11 are formed is pasted, so that the concave-convex shaped buried insulating film 4 is provided. The SOI substrate 1 is formed.

  In the semiconductor device having such a structure, the thickness of the buried insulating film 4 is increased in the portion of the buried insulating film 4 that is the convex portion 4b. Therefore, when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to the GND, a portion of the support substrate 2 corresponding to the recessed portion 4a of the embedded insulating film 4 is used. Since the thickness of the buried insulating film 4 is reduced, the charge is easily induced. However, the thickness of the buried insulating film 4 in the portion of the support substrate 2 corresponding to the convex portion 4b of the buried insulating film 4 is increased. Is thicker—charges are less likely to be induced. In other words, it becomes possible to localize −charges at locations adjacent to the buried insulating film 4 in the support substrate 2 to portions corresponding to the recesses 4 a of the buried insulating film 4 in the support substrate 2.

  For this reason, it is possible to make it difficult for + charges to be induced in the n-type region 11 at a position facing the convex portion 4b of the buried insulating film 4, and a high voltage is applied to the cathode electrode 8 of the PN diode and the anode When the electrode 9 and the support substrate 2 are fixed to GND, the width of equipotential lines extending in the vertical direction from the surface of the active layer 3 toward the n-type region 11 is more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  Note that, when the buried insulating film 4 is formed in a concavo-convex shape as in the present embodiment, a process for that is required, but it is assumed that a PN junction portion between the p-type region 10 and the n-type region 11 is used. Due to the withstand voltage structure, the unevenness formed in the buried insulating film 4 may be smaller than the conventional one. For this reason, even if the buried insulating film 4 has a concavo-convex shape, it is possible to prevent the manufacturing process from becoming complicated and becoming difficult.

(Eighth embodiment)
An eighth embodiment of the present invention will be described. The semiconductor device according to the present embodiment is also a part of the first embodiment and the other configuration is the same as that of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  FIG. 15 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, in the present embodiment, the surface of the embedded insulating film 4 on the active layer 3 side has an uneven shape. Specifically, the concave and convex portions 4a that are recessed with respect to the surface side of the active layer 3 with respect to the buried insulating film 4 and the convex portions 4b that protrude toward the surface side of the active layer 3 are provided. The shape is configured. The p-type region 10 is arranged in the concave portion 4a, and the n-type region 11 is arranged on the convex portion 4b.

  With such a structure, the thickness between the support substrate 2 and the n-type region 11 is greater than the thickness between the support substrate 2 and the p-type region 10 with respect to the thickness of the buried insulating film 4. . For this reason, when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to GND, the n-type region 11 is further adjacent to the buried insulating film 4. + It becomes difficult to induce charge. Thereby, when a high voltage is applied to the cathode electrode 8 of the PN diode and the anode electrode 9 and the support substrate 2 are fixed to GND, the surface extends from the surface of the active layer 3 toward the n-type region 11 in the vertical direction. The equipotential lines are more uniformly distributed. Therefore, the interval between equipotential lines is further corrected, and the breakdown voltage can be further improved.

  Regarding the method for manufacturing the semiconductor device of this embodiment, the step of forming irregularities on the buried insulating film 4 is performed, and the junction depth of the n-type region 11 is increased corresponding to the height of the convex portions 4b. For example, energy adjustment at the time of ion implantation is different from that of the first embodiment, but other steps may be the same as those of the first embodiment. For example, the process of forming irregularities on the buried insulating film 4 is performed as follows. First, the p-type region 10 and the n-type region 11 are formed on the silicon substrate 12 constituting the active layer 3. Subsequently, a recess is formed on the surface by photoetching, and an embedded insulating film 4 is formed so as to fill the recess. By such a process, the concave portion 4a of the buried insulating film 4 is formed by the portion where the concave portion of the silicon substrate 12 is not formed, and the convex portion of the buried insulating film 4 is formed by the portion where the concave portion of the silicon substrate 12 is formed. 4b can be formed.

  In the present embodiment as well, as in the seventh embodiment described above, the buried insulating film 4 is formed in a concavo-convex shape, and therefore a process for that is required. However, a PN junction formed by the p-type region 10 and the n-type region 11 Therefore, the unevenness formed in the buried insulating film 4 may be smaller than that of the conventional structure. For this reason, even if the buried insulating film 4 has a concavo-convex shape, it is possible to prevent the manufacturing process from becoming complicated and becoming difficult.

(Other embodiments)
(1) In the above embodiments, the case where each p-type region 10 has the same height and each n-type region 11 has the same height has been described as an example. However, each p-type region 10 and each n-type region 11 need not have the same height. For example, as shown in the cross-sectional view of the semiconductor device in FIG. 16, the heights of the p-type regions 10 and the n-type regions 11 may be uneven. A semiconductor device having such a structure can be manufactured by performing ion implantation a plurality of times using a plurality of masks.

  (2) Similarly, in each of the above embodiments, each p-type region 10 has the same width and each n-type region 11 has the same width as an example. However, each p-type region 10 and each n-type region 11 need not have the same width. For example, as shown in the cross-sectional view of the semiconductor device in FIG. 17, the widths of the p-type regions 10 and the n-type regions 11 may be uneven. For the semiconductor device having such a structure, the width of the opening of the mask when forming the p-type region 10 and the mask when forming the n-type region 11 with respect to the manufacturing method shown in the first embodiment or the like. It can manufacture by making the width | variety of an opening part uneven.

  (3) In the above embodiments, the case where each p-type region 10 has the same impurity concentration and each n-type region 11 has the same impurity concentration has been described as an example. However, each p-type region 10 and each n-type region 11 need not have the same impurity concentration. A semiconductor device having such a structure can also be manufactured by performing ion implantation at a plurality of different concentrations using a plurality of masks.

(4) In each of the above embodiments, the case where the p-type region 10 and the n-type region 11 are arranged in the entire region from the n ⁺ -type cathode region 5 to the p ⁺ -type anode region 6 has been described. There is no need for the p-type region 10 and the n-type region 11 to be disposed over the entire area. For example, as shown in the cross-sectional view of the semiconductor device in FIG. 18, the p-type region 10 and the n-type region 11 are not arranged in a part between the n ⁺ -type cathode region 5 and the p ⁺ -type anode region 6. There may be areas.

  (5) In the first embodiment, the case where both the p-type region 10 and the n-type region 11 are formed by ion implantation using different masks has been described. However, either one is formed without a mask. It is also possible. For example, the n-type region 11 is formed by ion implantation on the surface of the silicon substrate 12 without a mask, and the p-type region 10 is formed on the surface of the silicon substrate 12 using a mask. Then, at the time of thermal diffusion, the p-type region 10 is formed by inverting the conductivity type at the location where the p-type impurity is implanted, and the n-type region 11 is formed where the p-type region 10 is not formed. Can be.

  Similarly, a silicon substrate 12 having an impurity concentration gradient from the beginning and having a higher n-type impurity concentration on the side to be bonded to the buried insulating film 4 than the other portions is used. In this case, the ion implantation process itself for forming the n-type region 10 can be omitted.

  (6) Furthermore, in each of the above embodiments, the semiconductor device in which the PN diode is formed as the semiconductor element has been described. However, the present invention can also be applied to a semiconductor device in which another semiconductor element is formed. That is, a PN junction composed of a p-type region 10 and an n-type region 11 having a bottom surface layout that is concentric as described in the above embodiments is arranged for a semiconductor element having a top surface layout in a circular shape. It can be set as such a structure.

FIG. 19 is a cross-sectional view of a semiconductor device including an LDMOS as a semiconductor element. As shown in this figure, the surface layer portion of the active layer 3, p ^- -type with the channel layer 70 is formed, the p ^- the p in the mold channel layer 70 ^- the surface portion of the mold channel layer 70 n ^{A +} type source region (second impurity layer) 71 and a p ⁺ type contact region (first impurity layer) 72 are formed. A portion of the surface of the p ⁻ -type channel layer 70 located between the n ⁺ -type source region 71 and the active layer 3 is defined as a channel region 73, and a gate is formed on the channel region 73 via a gate insulating film 74. An electrode 75 is disposed. Further, on the n ⁺ -type source region 71 and p ⁺ -type contact region 72 is connected is disposed the source electrode 76, n ⁺ -type source region 71 and p ⁺ -type contact region 72 electrically .

On the other hand, an n ⁺ type drain region 77 laid out in a circular shape is formed in the surface layer portion of the active layer 3 so as to be separated from the p ⁻ type channel layer 70 via the LOCOS oxide film 7. And the drain electrode 78 is formed on the n ⁺ -type drain region 77 are an n ⁺ -type drain region 77 and electrically connected to the structure. Each configuration of the p ⁻ type channel layer 70, the n ⁺ type source region 71, the p ⁺ type contact region 72, and the like is laid out in a ring shape so as to surround the n ⁺ type drain region 77 and the drain electrode 78. Although not shown, an LDMOS is configured by providing an interlayer insulating film and a protective film.

Also in the semiconductor device in which such an LDMOS is configured, the central region 10a corresponding to the n ⁺ -type drain region 77 is surrounded at a position adjacent to the buried insulating film 4 in the active layer 3 as in the above embodiments. Thus, by configuring a PN junction composed of the p-type region 10 and the n-type region 11, the same effects as those of the above embodiments can be obtained. FIG. 19 illustrates the case where the structure of the first embodiment is applied to a semiconductor device provided with an LDMOS. Of course, the structure can also be applied to the structures of the second to eighth embodiments.

FIG. 20 is a cross-sectional view of a semiconductor device including an IGBT as a semiconductor element. As shown in this figure, the surface layer portion of the active layer 3, p ^- with type base region 80 is formed, the p ^- the p in the mold base region 80 ^- in the surface of the mold base region 80 n ^{A +} type emitter region (second impurity layer) 81 and a p ⁺ type contact region (first impurity layer) 82 are formed. A portion of the surface of the p ⁻ -type base region 80 located between the n ⁺ -type emitter region 81 and the active layer 3 is defined as a channel region 83, and a gate is formed on the channel region 83 via a gate insulating film 84. An electrode 85 is disposed. Further, on the n ⁺ -type emitter region 81 and p ⁺ -type contact region 82 is the emitter electrode 86 is disposed, is connected n ⁺ -type emitter region 81 and p ⁺ -type contact region 82 electrically .

On the other hand, a circularly laid out n ⁺ type buffer layer 87 is formed on the surface layer portion of the active layer 3 so as to be separated from the p ⁻ type base region 80 via the LOCOS oxide film 7, and n ⁺ A p ⁺ type collector region 88 is formed in the surface layer portion of the n ⁺ type buffer layer 87 in the type buffer layer 87. The p ⁺ -type on the collector region 88 is formed with a collector electrode 89, there is a p ⁺ -type collector region 88 and electrically connected to the structure. Each configuration of the p ⁻ type base region 80, the n ⁺ type emitter region 81, the p ⁺ type contact region 82, and the like surrounds the n ⁺ type buffer layer 87, the p ⁺ type collector region 88 and the collector electrode 89. Is laid out. And although not shown in figure, IGBT is comprised by providing an interlayer insulation film and a protective film.

Also in the semiconductor device in which such an IGBT is configured, the central region 10a corresponding to the p ⁺ -type collector region 88 is surrounded at a position adjacent to the buried insulating film 4 in the active layer 3 in the same manner as in the above embodiments. Thus, by configuring the PN junction portion composed of the p-type region 10 and the n-type region 11, the same effects as those of the above embodiments can be obtained. 20 illustrates the case where the structure of the first embodiment is applied to a semiconductor device provided with an IGBT, but of course, the structure can also be applied to the structures of the second to eighth embodiments.

(7) In each of the embodiments described above, from the p-type region 10 and the n-type region 11 in which the bottom surface layout as described in each of the above embodiments is concentric with respect to the semiconductor element whose top surface layout is laid out in a circular shape. The case where the structure is such that the PN junction portion is arranged has been described. However, circular shapes and concentric circles are merely examples. That is, the n ⁺ type cathode region 5 corresponding to the first impurity layer, the n ⁺ type drain region 77 or the p ⁺ type collector region 88 is the center, and the p ⁺ corresponding to the second impurity layer is formed radially outside the periphery. Any structure provided with the type anode region 6, the n ⁺ type source region 71, or the n ⁺ type emitter region 81 may be used.

  For example, the first impurity layer at the center is the above-described circular shape or concentric circle shape, and is a regular polygon (including a rounded corner), for example, a regular hexagonal shape, an elliptical shape, or a rectangular shape, For a semiconductor element laid out so that two impurity layers radially surround it, a PN junction composed of the p-type region 10 and the n-type region 11 as described in the above embodiments is a radial corresponding to the semiconductor element. It is also possible to adopt a structure having a bottom layout. That is, a plurality of p-type regions 10 and n-type regions 11 are alternately formed in a ring shape, regular polygon frame shape, elliptical frame shape, rectangular frame shape, etc. from the center of a circle, regular polygon, ellipse, rectangle, etc. By doing so, it is possible to obtain the same effects as in the above embodiments.

(8) In each of the above embodiments, an example of the cross-sectional configuration of the PN diode has been shown, but other configurations may be included. For example, as shown in the cross-sectional view of the semiconductor device shown in FIG. 21, the periphery of the n ⁺ type cathode region 5 is surrounded by the n type electric field relaxation layer 13 to alleviate the high electric field applied to the n ⁺ type cathode region 5 at the time of breakdown. Is also possible. Such an n-type electric field relaxation layer 13 has a depth of 1 to 10 μm and a surface concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , for example.

  (9) It should be noted that the above embodiments can be appropriately combined with each other. For example, the trench isolation structure 20 shown in the second embodiment can also be applied to various configurations shown in the third to eighth embodiments and other embodiments. Further, the resistive field plate 30 or the capacitive field plate 40 shown in the third and fourth embodiments can be applied to various configurations shown in the fifth to eighth embodiments and other embodiments. In addition, the SIPOS film 50 shown in the fifth embodiment can be applied to various configurations shown in the seventh, eighth, and other embodiments. In addition, the semiconductor element in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but the structure in which each conductivity type is inverted, that is, the first conductivity type is p-type, The present invention can also be applied to a semiconductor element whose second conductivity type is n-type.

(10) Further, for example, before the bonding step, an alignment mark is formed on the surface of the silicon substrate 12 opposite to the side on which the pseudo field plate is formed, and the alignment is performed using the mark. And a pseudo field plate composed of p-type regions 10 and n-type regions 11 that are alternately repeated can be formed. In this way, the first impurity layer (n ⁺ type cathode region 5, n ⁺ type drain region 77, p ⁺ type collector region 88) and the second impurity layer (p ⁺ type anode region 6, n ⁺ type source region). , N ⁺ -type emitter region 81) and a pseudo-upper surface layout in a step of forming a semiconductor element having a top surface layout in which the second impurity layer radially surrounds the periphery around the first impurity layer. It is fully possible to align the field plates.

  (11) Also, the case where the layout structure of the lead wiring shown in FIG. 5 is applied to the first embodiment has been described. Is possible.

  (12) In each of the above embodiments, silicon has been described as an example. However, the present invention can be applied not only to silicon but also to other semiconductors such as SiC.

DESCRIPTION OF SYMBOLS 1 SOI substrate 2 Support substrate 3 Active layer 4 Embedded insulating film 4a Concave part 4b Convex part 5 n ⁺ type | mold cathode area | region 6 p ⁺ type | mold anode area | region 7 LOCOS oxide film 8 Cathode electrode 9 Anode electrode 10 P-type area | region 10a Central area | region 11 n Type region 12 Silicon substrate 20 Trench isolation structure 21 Groove 22 Insulating film 30 Resistance type field plate 40 Capacitive type field plate 50 SIPOS film 60 Charge storage layer

Claims (14)

The support substrate (2) and the active layer (3) made of silicon of the first conductivity type are formed on the SOI substrate (1) formed on both sides of the buried insulating film (4), and the active layer (3) A semiconductor having a top layout in which a second impurity layer (6, 71, 81) is formed around the first impurity layer (5, 77, 88) formed in the surface layer portion of the active layer (3) on the surface side In a semiconductor device provided with an element,
From the first impurity layer (5, 77, 88) formed on the surface layer portion of the active layer (3) on the buried insulating film (4) side, the layout corresponds to the semiconductor element. The second conductivity type regions (10) alternately and repeatedly formed in the direction toward the two impurity layers (6, 71, 81) and the first conductivity type regions (11 having a higher concentration than the active layer (3)) ) Is provided in one element isolation region surrounded by the element isolation structure in the active layer (3).
The support substrate (2) and the active layer (3) made of silicon of the first conductivity type are formed on the SOI substrate (1) formed on both sides of the buried insulating film (4), and the active layer (3) The second impurity layer (6, 71, 81) is centered on the first impurity layer (5, 77, 88) formed in the surface layer portion of the active layer (3) on the surface side, and the first impurity layer (5, 77, 88) in a semiconductor device provided with a semiconductor element having a top surface layout that radially surrounds
The second conductive type having the radial layout corresponding to the semiconductor element and repeatedly formed alternately on the surface of the active layer (3) that is bonded to the buried insulating film (4) A semiconductor device comprising a region (10) and a first conductivity type region (11).   A trench isolation structure (20) extending from the surface of the active layer (3) to the buried insulating film (4) is provided, and the semiconductor element and the second conductivity type region are provided by the trench isolation structure (20). 3. The semiconductor device according to claim 1, wherein (10) and the first conductivity type region (11) are surrounded.   A spiral resistance field plate (30) corresponding to the semiconductor element or a capacitive field plate (40) in the vicinity thereof is provided on the semiconductor element in the active layer (3). 4. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that:   Between the active layer (3) and the buried insulating film (4), a SIPOS layer (50) made of Poly-Si having a higher resistance than the active layer (3) is provided. The semiconductor device according to claim 1, wherein:   5. The charge storage layer according to claim 1, further comprising: a charge storage layer having a layout corresponding to the first conductivity type region in the buried insulating film. The semiconductor device according to any one of the above.   The semiconductor device according to claim 6, wherein the first conductivity type region (11) is an n-type region, and the charge storage layer (60) stores + charges.   8. A concave-convex shape including a concave portion (4a) and a convex portion (4b) is formed on a surface of the buried insulating film (4) on the side of the support substrate (2). The semiconductor device according to any one of the above.   A concave / convex shape including a concave portion (4a) and a convex portion (4b) is formed on the surface of the embedded insulating film (4) on the active layer (3) side, and the second conductive type region (10). Is disposed in the recess (4a), and the first conductivity type region (11) is disposed on the protrusion (4b). The semiconductor device described.   The said 2nd conductivity type area | region (10) and the said 1st conductivity type area | region (11) are formed in the whole region corresponding to the said semiconductor element, The one of Claim 1 thru | or 9 characterized by the above-mentioned. The semiconductor device described. The semiconductor element is
A first conductivity type cathode region (5) corresponding to the first impurity layer and a second conductivity type anode region (6) corresponding to the second impurity layer formed in the surface layer portion of the active layer (3). When,
A cathode electrode (8) electrically connected to the cathode region (5);
An anode electrode (9) electrically connected to the anode region (6), and a PN diode having a layout surrounding the cathode region (5) in the anode region (6),
The second conductivity type region (10) and the first conductivity type region (11) also have a layout surrounding the central region (10a) with a position corresponding to the cathode region (5) as a central region (10a). The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. The semiconductor element is
A channel layer (70) of a second conductivity type formed in the surface layer portion of the active layer (3);
A source region (71) of a first conductivity type corresponding to the second impurity layer formed in a surface layer portion of the channel layer (70) in the channel layer (70);
A drain region (77) of a first conductivity type corresponding to the first impurity layer formed at a surface layer portion of the active layer (3) and spaced from the channel layer (70);
A portion of the surface of the channel layer (70) located between the active layer (3) and the source region (71) is defined as a channel region (73), and a gate insulating film (on the channel region (73)). 74) via a gate electrode (75) provided via
A source electrode (76) electrically connected to the source region (71) and the channel layer (70);
The drain region (77) is electrically connected to the drain region (77), and the drain region (77) is surrounded by the source region (71) and the channel region (70). LDMOS,
The second conductivity type region (10) and the first conductivity type region (11) also have a layout surrounding the central region (10a) with the position corresponding to the drain region (77) as the central region (10a). The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. The semiconductor element is
A second conductivity type base region (80) formed in a surface layer portion of the active layer (3);
A first conductivity type emitter region (81) corresponding to the second impurity layer formed in a surface layer portion of the base region (80) in the base region (80);
A collector region (88) of a second conductivity type corresponding to the first impurity layer formed at a surface layer portion of the active layer (3) and spaced from the base region (80);
A portion of the surface of the base region (80) located between the active layer (3) and the emitter region (81) is defined as a channel region (83), and a gate insulating film ( 84) via a gate electrode (85),
An emitter electrode (86) electrically connected to the emitter region (81) and the base region (80);
The collector region (88) is electrically connected to the collector region (88), and the emitter region (81) and the base region (80) surround the collector region (88). IGBT,
The second conductivity type region (10) and the first conductivity type region (11) also have a layout surrounding the central region (10a) with the position corresponding to the collector region (88) as the central region (10a). The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. Preparing a first conductivity type silicon substrate (12);
A second conductive type region (10) and a first conductive type region (11) are formed on the surface of the silicon substrate (12) to have a radial layout centered on a predetermined location (10a) and to be alternately repeated. And a process of
The silicon substrate (12) on which the second conductivity type regions (10) and the first conductivity type regions (11) that are alternately repeated and the support substrate (2) are formed are connected to the silicon substrate (12). Embedded insulating film (4) so that the surface on which the second conductivity type region (10) and the first conductivity type region (11) are alternately repeated is directed to the support substrate (2) side. A step of bonding via,
Of the silicon substrate (12) bonded to the support substrate (2), the second conductive type region (10) and the first conductive type region (11), which are alternately repeated, are opposite to the surface on which the second conductive type region (11) is formed. Forming an active layer (3) made of silicon by removing the surface to form a thin film;
The second conductive type region (10) and the first conductive type region (11) in which the top surface layout is alternately repeated with respect to the surface of the active layer (3) opposite to the buried insulating film (4). ), And the first impurity layer (5, 77, 88) and the second impurity layer (6, 71, 81) have a periphery around the first impurity layer (5, 77, 88). And a step of forming a semiconductor element having a top surface layout in which two impurity layers (6, 71, 81) are radially enclosed, and a method for manufacturing a semiconductor device.

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