JP2007227949A - Manufacturing method of semiconductor device comprising horizontal high breakdown voltage element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device comprising a horizontal high breakdown voltage element having an extremely high breakdown voltage which is not restricted by electric field concentration of an SOI layer surface. <P>SOLUTION: In the method for manufacturing the semiconductor device comprising the horizontal high breakdown voltage element, an SiC thin film layer 20 made of a material which has a wide band gap wider than that of a material of a semiconductor layer 2 by introducing impurities into the semiconductor layer 2 is formed. A buried insulating layer 3 and a silicon substrate 1 are laminated to the semiconductor layer 2 having the SiC thin film layer 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a lateral high breakdown voltage element, and more specifically, a semiconductor device having a lateral high breakdown voltage element having an SOI (Semiconductor on Insulator) structure and capable of maintaining a high breakdown voltage. It is related with the manufacturing method.

First, the conventional technique will be described.
FIG. 36 is a schematic cross-sectional view showing a first example of a conventional semiconductor device. Referring to FIG. 36, the semiconductor device includes an insulating substrate 103. An n ⁻ semiconductor layer 102 (referred to as an SOI layer) is provided over the insulating substrate 103. A low resistance n ⁺ semiconductor region 104 is provided on the surface of the n ⁻ semiconductor layer 102. A p ⁺ semiconductor region 105 is provided so as to surround the n ⁻ semiconductor layer 102. A cathode electrode 106 is electrically connected to the n ⁺ semiconductor region 104. An anode electrode 107 is electrically connected to the p ⁺ semiconductor region 105. A back electrode 108 is provided on the back surface of the insulating substrate 103. n ^- insulating film 109 provided in the semiconductor layer 102, n ^- is for electrically separated from each other of the semiconductor layer 102 into a plurality of portions. The insulating layer 111 provided on the n ⁻ semiconductor layer 102 is for electrically separating the cathode electrode 106 and the anode electrode 107 from other portions.

Next, the operation will be described.
Referring to FIG. 37, when anode electrode 107 and back electrode 108 are set to 0 V and a positive voltage is applied to cathode electrode 106, depletion occurs from the pn junction between n ⁻ semiconductor layer 102 and p ⁺ semiconductor region 105. Layer 133 extends. The depletion layer 133 stops extending when it reaches the n ⁺ semiconductor region 104. The depletion layer 133 is a kind of insulator, and no current flows between the cathode electrode 106 and the anode electrode 107. Such a semiconductor device is called a diode.

  Furthermore, by adding an insulated gate structure to this structure, a self-extinguishing device such as a MOS (Metal Oxide Semiconductor) transistor or an IGBT (Insulated Gate Bipolar Transistor) can be manufactured. Note that in the above structure, the insulating layer 103 does not share voltage.

In order to achieve a high breakdown voltage in the semiconductor device having the above structure, it is necessary to widen the n ⁻ semiconductor layer 102 that holds most of the electric field. Although it is relatively easy to take a horizontal direction (perpendicular to the drawing sheet), it is necessary to increase the thickness t _{soi of the} SOI layer in the vertical direction (vertical direction in the figure). There is a problem of enlargement, and there is a problem that separation and embedding techniques become difficult.

FIG. 38 is a schematic cross-sectional view showing a second example of a conventional semiconductor device. Referring to FIG. 38, n ⁻ semiconductor layer 102 is provided on semiconductor substrate 101 with a buried insulating layer 103 made of an oxide film interposed. In the figure, other members are substantially the same as those of the conventional semiconductor device shown in FIG. 36, and therefore, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

Next, the operation will be described.
Referring to FIG. 39, when anode electrode 107 and back electrode 108 are set to 0 V and a positive voltage is applied to cathode electrode 106, depletion occurs from the pn junction between n ⁻ semiconductor layer 102 and p ⁺ semiconductor region 105. Layer A extends. At this time, the entire semiconductor substrate 101 is at 0 V and functions as a field plate through the buried insulating layer 103. Therefore, in addition to the depletion layer A, the n ⁻ semiconductor layer 102 and the buried insulating layer A depletion layer B extends from the interface with the semiconductor layer 103 toward the surface of the n ⁻ semiconductor layer 102. On the other hand, the electric field at the pn junction between the n ⁻ semiconductor layer 102 and the p ⁺ semiconductor region 105 is relaxed by the fact that the depletion layer A grows easily due to the influence of the depletion layer B.

  This effect is generally referred to as a RESURF (Reduced Surface Field) effect, and a similar effect can be expected by extending the pn junction to a position along this interface instead of the buried insulating layer 103. JA Appear et al., IEBM Tech. Dig., 1979, pp.238-241.

In the above-described structure, the voltage burden ratio per unit thickness between the oxide film and silicon is a reciprocal ratio of the dielectric constant (ε _OXi = 3.9, ε _Si = 11.7), and thus is approximately 3 : 1. For this reason, the breakdown voltage can be improved by increasing the thickness of the buried oxide film 3 that holds a considerable portion of the voltage.

  This is shown in FIG. In FIG. 40, the region changing to the right indicates the effective range of the RESURF effect. When the film thickness is simply increased, the withstand voltage (BV) decreases conversely at a certain value. This is because as the ground potential of the semiconductor substrate 101 that assists the extension of the depletion layer B increases, the extension of the depletion layer B becomes weaker and the electric field relaxation effect of the depletion layer A becomes ineffective. Therefore, in order to realize a high breakdown voltage such as 600 V, it is necessary to control the buried oxide film to be formed in the vicinity of 7 μm. However, in the film forming method, in order to form a buried oxide film in the vicinity of 7 μm, a considerably long process time is required as shown in FIG.

  As a conventional example in which the buried oxide film can be made as thin as possible while maintaining a high breakdown voltage, a technique disclosed in Japanese Patent Laid-Open No. 7-183522 is introduced.

  FIG. 42 is a schematic cross-sectional view showing the configuration of the semiconductor device disclosed in the above publication. Referring to FIG. 42, a semiconductor layer 102 is formed on a semiconductor substrate 101 with a buried insulating layer 103 interposed. On the surface of the semiconductor layer 102, a field oxide film layer 111b and an LDMOS transistor are formed.

  This LDMOS transistor has a channel region 105a, a source region 105b, a drain region 104, a drift region 120, a gate oxide insulating layer 111a, and a gate electrode layer 112. The channel region 105a is formed on one side of the field oxide film layer 111b, and the source region 105b is located on the surface in the channel region 105a. The drain region 104 is located on the opposite surface across the source region 105b and the field oxide insulating layer 111a.

  Gate electrode layer 112 is formed on channel region 105a via gate oxide insulating layer 111a, and extends on field oxide film layer 111b.

  Drift region 120 is formed from the bottom surface of field oxide insulating layer 111a to the bottom surface of semiconductor layer 102 and from the source region 105b side to the drain region 104 side, and is made of, for example, SiC (silicon carbide). .

  A source electrode 107 is formed so as to be electrically connected to the source region 105 b and the channel region 105 a, and a drain electrode 106 is formed so as to be electrically connected to the drain region 104.

  Here, the SiC layer used in the drift region 120 does not have any influence peculiar to SiC on the chemical treatment of the SOI layer surface portion, the photoengraving, and the implantation diffusion process. Is possible.

SiC has a wider band gap than Si (silicon) which is a material constituting the semiconductor layer. For this reason, by replacing Si with SiC, the avalanche generation electric field strength can be improved, whereby the breakdown voltage can be improved without increasing the thickness of the buried insulating layer 103.
JA Appear et al., IEBM Tech. Dig., 1979, pp.238-241 JP-A-7-183522

However, in this structure, since the gate is offset, the voltage V applied in the lateral direction is concentrated on a short distance W ₁ between the gate electrode layer 112 and the drain electrode 106 to increase the electric field strength. This state is shown by the equipotential line distribution of FIG. 43A and the electric field intensity distribution of FIG. FIG. 43B shows the electric field intensity distribution at the surface portion of the SOI layer 102 along the line AA in FIG.

  Referring to FIGS. 43A and 43B, when the electric field strength E is pushed up, the avalanche electric field strength is easily reached. If the avalanche electric field strength is reached at the surface portion of the SOI layer 102, the effect of improving the breakdown voltage cannot be expected even if the bottom surface portion of the SOI layer is the SiC layer. For this reason, the effect of the offset can be expected only in a relatively low breakdown voltage region where the electric field concentration on the surface can be held by the field oxide film.

Further, in order to prevent voltage concentration in the lateral direction, the distance W ₁ between the gate electrode layer 112 and the drain electrode 106 may be increased. In this case, the electric field strength decreases as a whole as shown in FIG. Nevertheless, a high electric field region is likely to be formed locally at both ends R, and an electric field strength peak P occurs in this high electric field region. For this reason, the electric field strength E easily reaches the avalanche electric field strength at the peak portion P. If the electric field strength E reaches the avalanche electric field strength, the effect of improving the breakdown voltage cannot be expected as described above.

  In order to reduce this peak value, it is conceivable to optimize the combination of substrate condition parameters (SOI layer thickness, SOI layer resistance value, buried insulating layer thickness, etc.). The factor will be introduced.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device having a lateral high breakdown voltage element having a remarkably high breakdown voltage without being restricted by electric field concentration on the surface of the SOI layer.

  A method of manufacturing a semiconductor device having a lateral high voltage element according to the present invention includes a semiconductor layer having a semiconductor layer formed on a semiconductor substrate with a buried insulating layer interposed therebetween, and the semiconductor device having the high voltage element formed in the semiconductor layer. The manufacturing method includes the following steps.

  First, by introducing impurities into the semiconductor layer, a wide band gap layer made of a material having a wider wide band gap than the material of the semiconductor layer is formed. Then, the buried insulating layer and the semiconductor substrate are bonded to the semiconductor layer having the wide band gap layer.

  Preferably, in the above aspect, the impurity is introduced into the semiconductor layer through a coating layer formed on the surface of the semiconductor layer.

  Preferably, the above aspect further includes a step of forming an amorphous layer in the semiconductor layer by introducing the same element as the element constituting the semiconductor layer into the semiconductor layer. The growth direction of the wide band gap layer is specified by forming the wide band gap layer by introducing impurities after forming the amorphous layer.

  A semiconductor device having a lateral high breakdown voltage element according to one aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulating layer interposed therebetween, and the high breakdown voltage element is formed in the semiconductor layer. In this case, a wide band gap layer and a field plate conductive layer are provided. The high breakdown voltage element has first and second impurity regions of opposite conductivity type formed in the semiconductor layer. The wide band gap layer is made of a material that is located at least in a region where the electric field strength is highest in the semiconductor layer when a breakdown voltage is applied to the high breakdown voltage element and has a wider band gap than the material of the semiconductor layer. . The field plate conductive layer is formed in a floating state with an insulating layer interposed between the semiconductor layer region sandwiched between the first and second impurity regions, and is electrically connected to the first impurity region. And a second electrode electrically connected to the second impurity region can be stored.

  Preferably in the above aspect, the wide band gap layer has a SiC layer. Preferably, the above aspect further includes a drift region located in the semiconductor layer between the first and second impurity regions and having the same conductivity type as the first impurity region and having an impurity concentration lower than that of the first impurity region. ing.

  Preferably, in the above aspect, the first impurity region is formed on the surface of the semiconductor layer, and the wide band gap layer is disposed near the surface of the semiconductor layer on which the first impurity region is formed.

  Preferably, in the above aspect, the wide band gap layer is disposed immediately below the first impurity region.

  Preferably, in the above aspect, the wide band gap layer is disposed on the bottom surface of the semiconductor layer on the buried insulating layer side.

  Preferably, in the above aspect, the wide band gap layer is disposed at a distance from the bottom surface of the semiconductor layer on the insulating layer side.

  Preferably, in the above aspect, the wide band gap layer has impurities of the same conductivity type as the drift region, and the impurity concentration of the wide band gap layer is not less than 2 times and not more than 10 times the impurity concentration of the drift region.

  A semiconductor device having a lateral high breakdown voltage element according to another aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulating layer interposed therebetween, and the high breakdown voltage element is formed in the semiconductor layer. And it has a wide band gap layer. The high breakdown voltage element is formed between the first and second impurity regions of opposite conductivity type formed in the semiconductor layer, and between the first and second impurity regions and has the same conductivity type as the first impurity region. And a drift region having an impurity concentration lower than that of the region. The wide band gap layer is made of a material that is located at least in a region where the electric field strength is highest in the semiconductor layer when a breakdown voltage is applied to the high breakdown voltage element and has a wider band gap than the material of the semiconductor layer. . The wide band gap layer has impurities of the same conductivity type as the second impurity region and is electrically short-circuited to the second impurity region.

  Preferably, in the above aspect, the wide band gap layer and the third impurity region are formed adjacent to each other on the bottom surface of the semiconductor layer on the buried insulating layer side, and the third impurity region has the same conductivity as the second impurity region. And is electrically shorted to the second impurity region.

  Preferably, in the above aspect, fourth and fifth impurity regions having mutually opposite conductivity types arranged alternately along the direction in which the bottom surface of the semiconductor layer extends are further provided. The wide band gap layer is disposed so as to sandwich the fourth and fifth impurity regions with the second impurity region, and is electrically short-circuited with the second impurity region by the fifth impurity region.

  Preferably, in the above aspect, a first electrode formed in a floating state with an insulating layer interposed between the semiconductor layer region sandwiched between the first and second impurity regions and electrically connected to the first impurity region; And a field plate conductive layer capable of storing a capacitance between the first electrode and the second electrode electrically connected to the second impurity region.

  A semiconductor device having a lateral high breakdown voltage element according to still another aspect of the present invention has a semiconductor layer formed on a semiconductor substrate with a buried insulating layer interposed, and the semiconductor layer has a high breakdown voltage element formed thereon. A device comprising a wide band gap layer. The high breakdown voltage element has first and second impurity regions of opposite conductivity type formed in the semiconductor layer. The wide band gap layer is made of a material that is located at least in a region where the electric field strength is highest in the semiconductor layer when a breakdown voltage is applied to the high breakdown voltage element and has a wider band gap than the material of the semiconductor layer. . The wide band gap layer is porous.

  Preferably in the above aspect, the wide band gap layer has the same conductivity type as the first impurity region.

  Preferably in the above aspect, the wide band gap layer has the same conductivity type as the second impurity region.

  Preferably, in the above aspect, the wide band gap layer and the third impurity region are formed adjacent to each other on the bottom surface of the semiconductor layer on the buried insulating layer side. The third impurity region has the same conductivity type as the second impurity region and is porous.

  Preferably, in the above aspect, a first electrode formed in a floating state with an insulating layer interposed between the semiconductor layer region sandwiched between the first and second impurity regions and electrically connected to the first impurity region; And a field plate conductive layer capable of storing a capacitance between the first electrode and the second electrode electrically connected to the second impurity region.

  In the method for manufacturing a semiconductor device having a lateral high voltage element according to the present invention, it is possible to improve the yield and manufacture an SOI substrate having stable bonded interface characteristics.

  Preferably, in the above aspect, the impurity is introduced into the semiconductor layer through a coating layer formed on the surface of the semiconductor layer. As a result, it is possible to suppress mixing of different kinds of impurities typified by a knock-on phenomenon when introducing impurities.

  Preferably, the above aspect further includes a step of forming an amorphous layer in the semiconductor layer by introducing the same element as the element constituting the semiconductor layer into the semiconductor layer. The growth direction of the wide band gap layer can be specified by forming the wide band gap layer by introducing impurities after forming the amorphous layer. Thereby, the growth direction of the wide band gap can be specified, and the wide band gap layer can be formed with good controllability.

  In the semiconductor device having a lateral high breakdown voltage element according to one aspect of the present invention, since the field plate conductive layer is provided, the electric field distribution on the surface of the semiconductor layer can be made uniform. Thereby, it is suppressed that the electric field strength on the surface of the semiconductor layer reaches the avalanche electric field strength. Therefore, a remarkably high breakdown voltage can be realized by a synergistic effect of the breakdown voltage improvement effect by the field plate conductive layer and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field strength is highest.

  Preferably in the above aspect, the wide band gap layer has a SiC layer. If this SiC layer is used, a device can be manufactured using a standard Si process as it is.

  Preferably, in the above aspect, the second impurity is located in the semiconductor layer between the first and second impurity regions, has the same conductivity type as the first impurity region, and has a lower impurity concentration than the first impurity region. A drift region forming a pn junction with the region is further provided. By providing this drift region, a high breakdown voltage can be obtained.

  Preferably, in the above aspect, the first impurity region is formed on the surface of the semiconductor layer, and the wide band gap layer is disposed near the surface of the semiconductor layer on which the first impurity region is formed. Thereby, even when the electric field strength becomes the highest in the vicinity of the formation region of the first impurity region, the electric field strength can be prevented from reaching the avalanche electric field strength in that portion.

  Preferably, in the above aspect, the wide band gap layer is disposed immediately below the first impurity region. Thereby, even when the electric field strength becomes the highest directly below the first impurity region, the electric field strength can be prevented from reaching the avalanche electric field strength at that portion.

  Preferably, in the above aspect, the wide band gap layer is disposed on the bottom surface of the semiconductor layer on the buried insulating layer side. Thereby, even when the electric field strength is highest at the bottom surface of the semiconductor layer, the electric field strength can be prevented from reaching the avalanche electric field strength at that portion.

  Preferably, in the above aspect, the wide band gap layer is disposed at a distance from the bottom surface of the semiconductor layer on the insulating layer side. Thereby, the increase from the bottom surface of the semiconductor layer to the avalanche region is suppressed by the wide band gap layer, and a high breakdown voltage can be obtained. In addition, since the wide band gap layer and the buried insulating layer are not in direct contact with each other, it is easy to secure the adhesive strength between the semiconductor layer and the buried insulating layer, and also suppresses plastic deformation from stress due to the difference in thermal expansion coefficient. it can.

  Preferably, in the above aspect, the wide band gap layer has impurities of the same conductivity type as the drift region, and the impurity concentration of the wide band gap layer is not less than 2 times and not more than 10 times the impurity concentration of the drift region. As a result, the critical electric field strength can be further increased, so that a higher breakdown voltage improvement effect can be expected.

  In a semiconductor device having a lateral high breakdown voltage element according to another aspect of the present invention, the wide band gap layer has impurities of the same conductivity type as the second impurity region and is electrically short-circuited with the second impurity region. For this reason, a much higher breakdown voltage is realized by a synergistic effect of the breakdown voltage improvement effect by forming the wide band gap layer in this way and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field strength is highest. can do.

  Preferably, in the above aspect, the wide band gap layer and the third impurity region are formed adjacent to each other on the bottom surface of the semiconductor layer on the buried insulating layer side, and the third impurity region has the same conductivity as the second impurity region. And is electrically shorted to the second impurity region. This makes it possible to obtain a higher breakdown voltage.

  Preferably, in the above aspect, fourth and fifth impurity regions having mutually opposite conductivity types arranged alternately along the direction in which the bottom surface of the semiconductor layer extends are further provided. The wide band gap layer is disposed so as to sandwich the fourth and fifth impurity regions with the second impurity region, and is electrically short-circuited with the second impurity region by the fifth impurity region. As a result, carriers can be prevented from being injected from the collector region to the wide band gap layer during the on-operation when the lateral high-voltage element is an IGBT, so that the number of carriers that can contribute to conductivity modulation can be increased, and the on-voltage Can be avoided.

  Preferably, in the above aspect, a first electrode formed in a floating state with an insulating layer interposed between the semiconductor layer region sandwiched between the first and second impurity regions and electrically connected to the first impurity region; And a field plate conductive layer capable of storing a capacitance between the first electrode and the second electrode electrically connected to the second impurity region. Since the field plate conductive layer is provided, the electric field distribution on the surface of the semiconductor layer can be made uniform. Thereby, it is suppressed that the electric field strength on the surface of the semiconductor layer reaches the avalanche electric field strength. Therefore, a remarkably high breakdown voltage can be realized by a synergistic effect of the breakdown voltage improvement effect by the field plate conductive layer and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field strength is highest.

  In a semiconductor device having a lateral high breakdown voltage element according to still another aspect of the present invention, the wide band gap layer is porous, so that the diffusion and proliferation of the avalanche current is suppressed by the presence of the holes. For this reason, a remarkably high breakdown voltage can be realized by a synergistic effect between the effect of the hole and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field strength is highest.

  Preferably in the above aspect, the wide band gap layer has the same conductivity type as the first impurity region. This makes it possible to obtain a higher breakdown voltage.

  Preferably, in the above aspect, the wide band gap layer has impurities of the same conductivity type as the second impurity region and is electrically short-circuited with the second impurity region. As a result, a significantly higher breakdown voltage is obtained by a synergistic effect of the breakdown voltage improvement effect obtained by providing the wide band gap layer in this manner and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field region is highest. It becomes possible.

  Preferably, in the above aspect, the wide band gap layer and the third impurity region are formed adjacent to each other on the surface of the semiconductor layer on the buried insulating layer side. The third impurity region has the same conductivity type as the second impurity region and is porous. Thereby, also in the third impurity region, diffusion and proliferation of the avalanche current are suppressed by the holes.

  Preferably, in the above aspect, a first electrode formed in a floating state with an insulating layer interposed between the semiconductor layer region sandwiched between the first and second impurity regions and electrically connected to the first impurity region; And a field plate conductive layer capable of storing a capacitance between the first electrode and the second electrode electrically connected to the second impurity region. Since the field plate conductive layer is provided, the electric field distribution on the surface of the semiconductor layer can be made uniform. Thereby, it is suppressed that the electric field strength on the surface of the semiconductor layer reaches the avalanche electric field strength. For this reason, a significantly higher breakdown voltage can be obtained by a synergistic effect of the breakdown voltage improvement effect by the field plate conductive layer and the breakdown voltage improvement effect of the wide band gap layer provided in the region where the electric field strength is highest.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element according to the first embodiment of the present invention. Referring to FIG. 1, an n ⁻ semiconductor layer (SOI layer) 2 is formed on a semiconductor substrate 1 with a buried insulating layer 3 interposed. A diode is formed in the n ⁻ semiconductor layer 2.

This diode has an n ⁺ semiconductor region 4 and a p ⁺ semiconductor region 5. Here, the region of the n ⁻ semiconductor layer 2 is used as it is as an n ⁻ drift region, and forms a pn junction with the p ⁺ semiconductor region 5. The n ⁺ semiconductor region 4 is formed in the region of the n ⁻ drift region 2 and on the surface of the semiconductor layer 2.

A cathode electrode 6 is formed so as to be electrically connected to the n ⁺ semiconductor region 4, and an anode electrode 7 is formed so as to be electrically connected to the p ⁺ semiconductor region 5. The insulating layer 11 provided on the n ⁻ semiconductor layer 2 is for electrically separating the cathode electrode 6 and the anode electrode 7 from other portions.

In a lateral type high withstand voltage element such as a diode, a region where the electric field strength is highest in the n ⁻ semiconductor layer 2 when a withstand voltage is applied (for example, when a 0 V is applied to the anode electrode 7 and a + voltage is applied to the cathode electrode). The wide band gap layer 20 is formed so as to be positioned at least in the above. The wide band gap layer 20 is made of a material having a wider band gap than Si forming the semiconductor layer 2, for example, SiC.

  On the insulating layer 11 between the cathode electrode 6 and the anode electrode 7, a capacitively coupled multiple field plate composed of a plurality of conductive layers 31 and 32 is formed. The plurality of conductive layers 31 and 32 are each insulated by an insulating layer 33 and are formed in a floating state (island state).

A back electrode 8 is formed on the back surface of the semiconductor substrate 1.
In a semiconductor device having such a lateral high withstand voltage element, a local high electric field region due to electric field concentration is formed on the bottom surface of the SOI layer 2 when a reverse blocking voltage is applied (when a withstand voltage is applied). This is well known, for example, in “Akiyama et al., Electronic Device / Semiconductor Power Conversion Joint Study Group Material, EDD-92-106 (SPC-92-72), 1992”. Therefore, it is noted that the avalanche electric field strength of SiC is 4.0 × 10 ⁶ V / cm, which is about an order of magnitude higher than that of Si of 3.7 × 10 ⁵ V / cm. By adding the SiC thin film layer 20 having a thickness of about 0.4 to 0.6 μm to a portion where the strength is often increased, the avalanche resistance can be essentially enhanced and the breakdown voltage can be improved.

  Therefore, the degree of withstand voltage improvement effect obtained by comparing this example with the conventional example was calculated by device simulation. The conditions and results are shown below.

  First, as shown in FIG. 1, the present invention is a device in which an SiC layer 20 is formed, and the conventional example is a device in which no SiC layer is formed. As common conditions for the SOI substrate, the thickness of the SOI layer was 15 μm, the thickness of the buried oxide film was 5 μm, and the distance between A (anode) and K (cathode) of the device was 88 μm. Based on this common condition, the breakdown voltage was compared between the inventive example and the conventional example using the Si-SOI specific resistance as a parameter. The result is shown in FIG.

  Referring to FIG. 2, although the RESURF effect is manifested at 6 Ω · cm or more in the conventional example and 10 Ω · cm in the example of the present invention, the maximum withstand voltages are 661 V and 1226 V, respectively. The breakdown voltage improvement effect about twice that of the example was obtained. From this, it was confirmed that the breakdown voltage can be improved by providing the SiC thin film layer in the region where the local high electric field region is formed.

  However, if the SiC layer 20 is simply provided, the effect of improving the breakdown voltage is very limited due to the non-uniformity of the electric field strength distribution as in the conventional example shown in FIG. Therefore, in the present embodiment, capacitively coupled multiple field plates 31 and 32 are provided between the cathode electrode 6 and the anode electrode 7.

  As shown in FIG. 3, the capacitively coupled multi-field plates 31 and 32 are formed between the conductive layers 31 between the cathode electrode 6 and the anode electrode 7 when a potential is applied to the cathode electrode 6 and the anode electrode 7. , 32 constitute a capacitor. In this state, as shown in FIG. 4, a plurality of capacitors are connected in series between the cathode electrode 6 and the anode electrode 7.

  Since such a capacitance is formed between the cathode electrode 6 and the anode electrode 7, the electric lines of force on the surface of the semiconductor layer 2 are almost uniform as shown in FIG. For this reason, as shown in FIG. 5B, the electric field strength distribution on the surface side of the semiconductor layer 2 becomes substantially uniform, and the non-uniformity of the electric field strength distribution is eliminated.

  As a result, as shown in FIG. 5C, the relatively high electric field strength in the semiconductor layer 2 is limited to the bottom surface portion, but the SiC thin film layer 20 is formed on the bottom surface portion. Therefore, the effect of improving the breakdown voltage increases. In other words, in the present embodiment, the avalanche generation region is replaced with the SiC thin film layer 20 to increase the avalanche generation electric field strength, and at the same time, the capacitively coupled multiple field plate is formed on the surface portion of the semiconductor layer 2. The electric field strength distribution in 2 is flattened. Only when these two effects are in synergy, a lateral high voltage element having a much higher breakdown voltage than before can be obtained.

  5B and 5C show the distribution of each electric field intensity E along the CC line and the DD line in FIG. 5A.

(Embodiment 2)
FIG. 6 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element according to the second embodiment of the present invention. Referring to FIG. 6, in the present embodiment, SiC thin film layer 20 is formed on the surface of semiconductor layer 2.

  Since the configuration other than the above is substantially the same as that of the above-described first embodiment (FIG. 1), the same members are denoted by the same reference numerals and the description thereof is omitted.

  The configuration of the present embodiment is particularly suitable for maintaining a high breakdown voltage due to the RESURF effect of the power device because of the necessity of design, such as a one-chip inverter integrated with a power device and a logic IC (Integrated Circuit). This is effective when the SOI active layer substrate 2 must be manufactured with a specific resistance higher than that of the SOI active layer substrate 2. This will be described in detail below.

FIGS. 7 to 10 are diagrams showing potential distributions with respect to various impurity concentrations in the SOI layer. Reference literature “Akiyama et al., Electronic Device / Semiconductor Power Conversion Joint Study Group Material, EDD-92-106 (SPC- 92-72), 1992 ". Here the impurity concentration N _soi of each SOI layer 7 in 5.0 × 10 ¹⁴ cm ^-3, Figure 8, 1.0 × 10 ¹⁵ cm ^-3, in FIG. 9 2.0 × 10 ¹⁵ cm ^-3 In FIG. 10, it is 4.0 × 10 ¹⁵ cm ⁻³ .

Referring to FIGS. 7 to 10, SOI activity is increased at 10 Ω · cm (5 × 10 ¹⁴ cm ⁻³ : FIG. 7) and 5 Ω · cm (1 × 10 ¹⁵ cm ⁻³ : FIG. 8) with high specific resistance. Electric field concentration occurs on the surface side of the layer, and when the specific resistance is 3 Ω · cm (2 × 10 ¹⁵ cm ⁻³ : FIG. 9), it is generated on the bottom side of the SOI active layer, and the specific resistance is 1 Ω · cm. (4 × 10 ¹⁵ cm ⁻³ : FIG. 10) shows that the RESURF effect is lost. FIG. 11 shows changes in breakpoint positions due to electric field concentration with respect to these impurity concentration changes.

Referring to FIG. 11, the position of the break point due to electric field concentration is the surface (a, b) of the SOI layer when the concentration of the SOI layer is relatively low, and the SOI layer increases when the impurity concentration of the SOI layer increases. After the transition to the bottom surface portion (c), the transition is made to the junction surface (d) between the p ⁺ semiconductor region and the n ⁻ semiconductor region. In the figure, symbol a corresponds to the conditions in FIG. 7, symbol b corresponds to FIG. 8, symbol c corresponds to FIG. 9, and symbol d corresponds to the conditions in FIG.

  In the present embodiment, as shown in FIG. 6, since SiC layer 20 is disposed on the surface of SOI layer 2, the specific resistance of the SOI active layer corresponding to a and b in FIG. A remarkably excellent pressure resistance improving effect can be obtained.

(Embodiment 3)
FIG. 12 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the third embodiment of the present invention. Referring to FIG. 12, in the present embodiment, SiC thin film layer 20 is located on the bottom surface of semiconductor layer 2 and directly below cathode electrode 6. Since the configuration other than this is almost the same as the configuration of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, as shown in FIG. 11 c, the breakdown voltage determined by the RESURF effect is significantly superior when the breakdown voltage is directly below the cathode electrode 6 and causes an avalanche phenomenon at the bottom surface of the SOI layer 2. A breakdown voltage improving effect can be obtained.

(Embodiment 4)
FIG. 13 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the fourth embodiment of the present invention. Referring to FIG. 13, in the present embodiment, SiC thin film layer 20 is selectively formed in the vicinity of n ⁺ semiconductor region 4 on the surface of semiconductor layer 2. Since the configuration other than this is almost the same as the configuration of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, as shown in FIGS. 11A and 11B, when the breakdown voltage determined by the RESURF effect causes an avalanche phenomenon at the surface portion of the semiconductor layer 2 directly under the cathode electrode 6, the breakdown voltage is significantly improved. An effect can be obtained.

(Embodiment 5)
FIG. 14 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the fifth embodiment of the present invention. Referring to FIG. 14, in the present embodiment, SiC thin film layer 20 is arranged at a distance d from the bottom surface of semiconductor layer 2. This distance d is a maximum of 0.5 μm. Since the configuration other than this is almost the same as the configuration of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals and the description thereof is omitted.

  In the present embodiment, as shown in FIG. 11C, when the breakdown voltage determined by the RESURF effect causes an avalanche phenomenon at the bottom surface of the semiconductor layer 2 immediately below the cathode electrode 6, the breakdown voltage improvement effect is remarkably excellent. Can be obtained.

When the withstand voltage is applied, the avalanche phenomenon increases from the start point of the avalanche phenomenon indicated by the point C ₁ in FIG. 14, but when the SiC thin film layer 20 separated by the distance d is reached, the increase of the avalanche region is suppressed. In addition, since the distance d is as short as 0.5 μm or less, the step of limiting the breakdown voltage characteristics is not reached, and the breakdown voltage is finally determined only after the avalanche phenomenon progresses in the SiC thin film layer 20. High breakdown voltage can be obtained.

  In the configuration of the present embodiment, the SiC thin film layer 20 is formed away from the interface, so that it is better not to form an interface in which the SiC thin film layer 20 and the buried insulating layer 3 are directly adjacent to each other in the device process. It is an effective structure. For example, this structure is particularly effective when it is difficult to ensure the adhesive strength, or when there is a concern that plastic deformation may occur in the SOI substrate due to the stress given by the difference in thermal expansion coefficient.

(Embodiment 6)
15 is a cross-sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element according to the sixth embodiment of the present invention, and FIG. 16 shows an impurity concentration distribution in the depth direction along the line EE in FIG. FIG.

  Referring to FIGS. 15 and 16, in the present embodiment, SiC thin film layer 20 is arranged at the same position as in the first embodiment shown in FIG. 1, but the impurity concentration in SiC thin film layer 20 is the same. The distribution is different from that of the first embodiment. In the present embodiment, the SiC thin film layer 20 contains impurities having the same conductivity type (n-type) as that of the semiconductor layer 2 so as to have a concentration of 2 to 10 times the impurity concentration of the semiconductor layer 2. . In addition, since it is as substantially the same as Embodiment 1 shown in FIG. 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

  The solid line showing the impurity concentration distribution in the SiC thin film layer in FIG. 16 shows a conventional example, and the dotted line shows the impurity concentration generally recognized when the SiC thin film layer 20 is formed in the semiconductor layer by C (carbon) ion implantation. The distribution (Invention Example 1) is shown, and the alternate long and short dash line shows the impurity concentration distribution of the present embodiment (Invention Example 2).

  Although the invention example 1 in FIG. 16 has an effect of improving the breakdown voltage as compared with the conventional example, the invention example 2 can be expected to further improve the breakdown voltage compared to the invention example 1. . This is because if the SiC thin film layer 20 where the avalanche phenomenon starts has a higher impurity concentration, the critical electric field strength becomes higher as long as it satisfies the depletion condition that is the premise of the RESURF effect when the reverse blocking voltage is applied. Because it can be done.

(Embodiment 7)
FIG. 17 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the seventh embodiment of the present invention. Referring to FIG. 17, in the present embodiment, SiC thin film layer 20 is formed on the bottom surface of SOI layer 2 and is of the opposite conductivity type (p-type) to n ⁻ semiconductor layer 2. A p ⁻ semiconductor region 5 a formed adjacent to SiC thin film layer 20 is formed on SiC thin film layer 20 so as to be electrically short-circuited with p ⁺ semiconductor region 5. The impurity concentration of p ⁻ semiconductor region 5 a and SiC thin film layer 20 is set lower than the impurity concentration of p ⁺ semiconductor region 5.

  In addition, since it is substantially the same as the structure of Embodiment 1 shown in FIG. 1 about a structure other than this, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

Next, the operation will be described.
Referring to FIG. 17, when a reverse bias is applied, the depletion layer starts to extend from the junction interface between n ⁻ semiconductor layer 2 and p ⁺ semiconductor region 5, but at the same time, the junction between p ⁻ semiconductor region 5 a and n ⁻ semiconductor layer 2. A depletion layer also extends from the interface. Both depletion layers extending from both are promoted by the RESURF effect. Here, by reducing the p-type impurity concentration of the p ⁻ semiconductor region 5 a and the SiC thin film layer 20 to substantially the same level as that of the n ⁻ semiconductor region 2, both the thin film layers 20 with a relatively low reverse bias voltage, 5a is completely depleted, and the buried insulating layer 3 bears more voltage than this.

  In the present embodiment, since the SiC thin film layer 20 is provided, the avalanche starting electric field strength can be set one digit higher in a place where the electric field strength is concentrated. Therefore, as described in the first embodiment, the high breakdown voltage can be increased. Can be planned.

(Embodiment 8)
FIG. 18 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the eighth embodiment of the present invention. Referring to FIG. 18, in the present embodiment, SiC thin film layer 20 has a reverse conductivity type (p-type) with n ⁻ semiconductor layer 2 and is directly electrically shorted with p ⁺ semiconductor region 5. . Further, SiC thin film layer 20 is set to an impurity concentration lower than that of p ⁺ semiconductor region 5. Since the structure other than this is almost the same as the configuration of the first embodiment shown in FIG. 1, the same members are denoted by the same reference numerals and the description thereof is omitted.

The present embodiment shows almost the same operation as that of the seventh embodiment shown in FIG.
Further, in the present embodiment, since the SiC thin film layer 20 is provided, the avalanche starting electric field strength can be set higher by one digit at a place where the electric field strength is concentrated. Therefore, as described in the first embodiment, the high breakdown voltage is increased. Can be achieved.

(Embodiment 9)
19 is a cross-sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element according to the ninth embodiment of the present invention, and FIG. 20 is a schematic cross-sectional view taken along line FF in FIG. . Note that FIG. 19 corresponds to a cross section taken along line GG in FIG. In FIG. 19, the semiconductor substrate located below the buried insulating layer 3 is omitted for convenience of explanation.

Referring to FIGS. 19 and 20, the lateral high breakdown voltage element in the present embodiment is an IGBT, which includes p ⁺ semiconductor region 5a, n ⁺ emitter region 5b, n type semiconductor region 4a, p ⁺ collector region 4b and gate electrode layer 12 are provided.

Here, the region of the n ⁻ semiconductor layer 2 is used as it is as an n ⁻ drift region, and forms a pn junction with the p ⁺ semiconductor region 5a. The n ⁺ emitter region 5b is disposed on the surface in the p ⁺ semiconductor region 5a. The n-type semiconductor region 4a is disposed on the surface in the n ⁻ drift region 2, and the p ⁺ collector region 4b is disposed on the surface in the n-type semiconductor region 4a. Gate electrode layer 12 is formed to face the surface region of p ⁺ semiconductor region 5a sandwiched between n ⁺ emitter region 5b and n ⁻ drift region 2 with a gate insulating layer (not shown) interposed therebetween. Yes.

A p ⁻ SiC thin film layer 20a is formed on the bottom surface of the semiconductor layer 2 so as to be located immediately below the n-type semiconductor region 4a. Between the p ⁻ SiC thin film layer 20 and the p ⁺ semiconductor region 5 a, n ⁻ drift regions 2 and p ⁻ semiconductor regions 5 c are alternately arranged along the bottom surface of the semiconductor layer 2. The p ⁻ SiC thin film layer 20 is electrically short-circuited to the p ⁺ semiconductor region 5a through the p ⁻ semiconductor region 5c.

In the plan view shown in FIG. 20, it is desirable that the area ratio between the n ⁻ drift region 2 and the p ⁻ semiconductor region 5c is 20% or less for the p ⁻ semiconductor region 5c and 80% or more for the n ⁻ drift region 2.

  In the present embodiment, the state in which the depletion layer extends when the reverse bias is applied and the state in which the high breakdown voltage is realized are basically the same as those in the seventh and eighth embodiments described above. In the present embodiment, in addition to this, a new merit can be obtained even when the IGBT is turned on. This will be described below.

In FIG. 19, the hole current (h ⁺ ) injected from the p ⁺ collector region 4b during the on-operation of the IGBT is easily re-injected into the p ⁻ SiC thin film layer 20 that is close in distance. In the IGBT, when sufficient current carriers are accumulated in the n ⁻ drift region 2 in the turn-on process, a low resistance state called conductivity modulation by electron-hole pairs appears, and the turn-on is completed. However, when the hole current (h ⁺ ) is reinjected into the p ⁻ SiC thin film layer 20, the number of holes accumulated in the n ⁻ drift region 2 decreases and the ratio contributing to the conductivity modulation decreases. There is a concern of increasing the on-voltage.

Therefore, in the present embodiment, the resistance Rh ⁺ of p ⁻ semiconductor region 5c is increased by adopting an alternately arranged structure of p ⁻ semiconductor region 5c and n ⁻ drift region 2 as shown in FIG. . Due to the high resistance Rh ⁺ , the hole current injected into the p ⁻ SiC thin film layer 20 is less likely to flow into the p ⁺ semiconductor region, and consequently the hole current is less likely to be injected into the p ⁻ SiC thin film layer 20. As a result, a decrease in the number of holes accumulated in the n ⁻ drift region can be suppressed, and an increase in on-voltage can be avoided.

Note that a capacitively coupled multiple field plate may also be provided in this embodiment.
(Embodiment 10)
FIG. 21 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the tenth embodiment of the present invention. Referring to FIG. 21, in the present embodiment, porous (porous) n ⁻ SiC thin film layer 20 is formed over the entire bottom surface of semiconductor layer 2, and n ⁻ drift region 2 and buried insulation are formed. Adjacent to each of the layers 3. In addition, since it is as substantially the same as Embodiment 1 shown in FIG. 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

A means for making the SiC thin film layer 20 porous is, for example, Liang-Sheng Liao et al., “Intense blue emission from porous β-SiC formed on C ⁺ -implanted silicon, Appl. Phys. Lett. 66 (18), pp. 2382-2384, 1 May 1995. According to this disclosed method, the porous structure can be realized by a relatively simple electric field wet treatment, and the thickness, the porous diameter, and the porous density of the porous forming layer can be realized. Is sufficiently controllable.

When a reverse bias is applied to the device configured as described above, the entire RESURF effect is basically maintained and the entire semiconductor layer 2 is quickly depleted, and the portion of the porous n ⁻ SiC thin film layer 20 near the cathode is depleted. This is the region with the highest electric field strength. As the avalanche electric field intensity approaches, an avalanche current starts to be generated from within the SiC thin film layer 20, but the diffusion and proliferation are suppressed by the presence of the porous material. Thereby, in addition to the effects described in the seventh to ninth embodiments, it is possible to further increase the breakdown voltage.

(Embodiment 11)
FIG. 22 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the eleventh embodiment of the present invention. Referring to FIG. 22, in this embodiment, p is pore formation on the bottom surface of the semiconductor layer 2 ^- SiC thin film layer 20 is formed, the p ^- this p on SiC thin film layer 20 ^- SiC thin film layer A p ⁻ semiconductor region 30 is formed adjacent to 20. The p ⁻ SiC thin film layer 20 and the p ⁻ semiconductor region 30 are electrically short-circuited to the p ⁺ semiconductor region 5 and are both porous. In addition, since it is as substantially the same as Embodiment 1 shown in FIG. 1 about another structure, the same code | symbol is attached | subjected about the same member and the description is abbreviate | omitted.

In addition, since the anodizing current flows only in the p ⁻ SiC thin film layer 20 and the p ⁻ semiconductor region 30 which are p-type semiconductor regions when porous is performed, these layers 20 and 30 are porous with good controllability. Can be

  In the present embodiment, the high breakdown voltage at the time of reverse bias application can be realized for the same reason as in the tenth embodiment.

(Embodiment 12)
FIG. 23 is a cross sectional view schematically showing a configuration of a semiconductor device having a lateral high breakdown voltage element in the twelfth embodiment of the present invention, and FIG. 24 is a schematic cross sectional view taken along the line HH in FIG. . FIG. 23 corresponds to a cross section taken along the line II of FIG.

Referring to FIGS. 23 and 24, in the present embodiment, p ⁻ SiC thin film layer 20 located on the bottom surface of semiconductor layer 2 is made porous. The p ⁻ semiconductor region 5c located between the p ⁻ SiC thin film layer 20 and the p ⁺ semiconductor region 5a is also porous.

  Since the configuration other than this is substantially the same as that of the ninth embodiment shown in FIGS. 19 and 20, the same members are denoted by the same reference numerals, and the description thereof is omitted.

  The merit of increasing the withstand voltage at the time of reverse bias application and the effect of suppressing the increase of the on voltage at the on operation in the present embodiment are the same as those described in the ninth embodiment.

In addition, since the p ⁻ SiC thin film layer 20 and the p ⁻ semiconductor region 5c are made porous, the diffusion and proliferation of the avalanche current are suppressed by this porous as described in the tenth and eleventh embodiments. Therefore, it is possible to further increase the breakdown voltage.

  In this embodiment, a capacitively coupled multiple field plate may be provided.

(Embodiment 13)
Next, a method for manufacturing an SOI substrate of the semiconductor device according to the above-described first, third, and fourth embodiments will be described as a thirteenth embodiment.

  25 to 28 are schematic cross-sectional views showing a method of manufacturing a semiconductor device having a lateral high breakdown voltage element according to the thirteenth embodiment of the present invention in the order of steps.

First, referring to FIG. 25, C (carbon) ions are implanted into the bonding side surface of semiconductor layer 2 made of silicon. The temperature at the time of this injection is 800 ° C. or more, and the injection amount is 1 × 10 ¹⁶ cm ⁻² or more.

  Referring to FIG. 26, after the C ion implantation, SiC crystallization is performed by performing heat treatment at 1100 ° C. or more for 3 hours or more, and SiC thin film layer 20 is formed in semiconductor layer 2.

  Referring to FIG. 27, the bonding side surface of semiconductor layer 2 is precisely polished by a CMP (Chemical Mechanical Polishing) method or the like, and part or all of thin film Si layer 2 remaining on the bonding side of SiC thin film layer 20 is removed. Removed. Thereby, the bonding side surface of the semiconductor layer 2 is planarized.

  Referring to FIG. 28, the buried oxide film 3 and the silicon substrate 1 are bonded to the bonding side surface of the semiconductor layer 2 to form an SOI substrate.

  By bonding with the manufacturing method of this embodiment mode, the yield can be improved and an SOI substrate having stable bonding interface characteristics can be manufactured.

(Embodiment 14)
29 to 31 are schematic cross-sectional views showing a method of manufacturing a semiconductor device having a lateral high breakdown voltage element in Embodiment 14 of the present invention in the order of steps.

Referring to FIG. 29, an implanted thick film made of a silicon oxide film (SiO ₂ film) or silicon nitride film (Si ₃ N ₄ film) having a thickness of 2000 mm or more is formed on the bonding side surface of semiconductor layer 2 made of silicon. A mask 40 is formed.

Referring to FIG. 30, C ions are implanted into semiconductor layer 2 through this implanted thick film mask 40. The temperature at the time of this injection is 800 ° C. or more, and the injection amount is 1 × 10 ¹⁶ cm ⁻² or more.

  Referring to FIG. 31, after this C ion implantation, heat treatment is performed at 1100 ° C. or more for 3 hours or more to perform SiC crystallization, and SiC thin film layer 20 is formed in semiconductor layer 2. At this time, SiC crystallization proceeds with the flatness of the bonding side surface of the semiconductor layer 2 maintained due to the presence of the implantation thick film mask 40.

  Thereafter, after removal of implantation thick film mask 40, an SOI substrate is formed by performing the same process as in the thirteenth embodiment shown in FIGS.

  By bonding by the manufacturing method of this embodiment mode, the yield can be improved and an SOI substrate having stable bonding interface characteristics can be manufactured.

  It is also conceivable to form the implantation thick film mask 40 by sputtering of SiC or plasma CVD. This is particularly effective when there is a concern that the device characteristics may be affected by the incorporation of different types of impurities typified by the knock-on phenomenon when C ions are implanted.

(Embodiment 15)
32 to 35 are schematic cross-sectional views showing a method of manufacturing a semiconductor device having a lateral high breakdown voltage element in Embodiment 15 of the present invention in the order of steps.

  Referring to FIG. 32, an implantation thick film mask 61 is formed on the bonding side surface of silicon substrate 2.

  Referring to FIG. 33, Si ions are implanted into silicon layer 2 through this implantation thick film mask 40. Thereby, an amorphous silicon layer 2 a is formed at a predetermined position of the semiconductor layer 2.

  Referring to FIG. 34, thereafter, C ions are implanted into silicon layer 2 through implantation thick film mask 40 in a range shallower than Si ion implantation (FIG. 33).

  Referring to FIG. 35, after C ion implantation, SiC crystallization is performed by heat treatment at 1100 ° C. or more for 3 hours or more, and SiC thin film layer 20 is formed in semiconductor layer 2. At this time, the presence of the amorphous layer 2a causes SiC crystallization to proceed in one direction toward the back surface side, thereby facilitating the controllability of SiC crystals. At this time, SiC crystallization proceeds while maintaining the crystallinity and flatness on the surface side by the implanted thick film mask 40.

In the thirteenth to fifteenth embodiments described above, all are developed on the basis of C ion implantation. As a result, a similar structure can be obtained. For example, Japanese Patent Laid-Open No. 1-135070 or European Patent There is also a method based on a manufacturing method of forming SiC by film formation such as CVD as shown in (EP-0317-445-B1). For these conventional examples, the present Embodiments 13 to 15 can basically maintain the flatness at the time of bonding, and the combinations at the time of bonding are Si / SiO ₂ , SiC / SiO ₂ , SiC / Si, Effectiveness can be exhibited in that it can be selected according to the purpose such as SiO ₂ / SiO ₂ .

  In the first to fifteenth embodiments described above, the SiC thin film layer has been described as the wide band gap layer 20. However, any material having a wider band gap than the semiconductor layer 2 can be used. Good. The material of the wide band gap layer 20 is more preferably a material that can be used to fabricate a device using a standard Si process as it is.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a method of manufacturing a semiconductor device having a lateral high breakdown voltage element having an SOI structure and capable of maintaining a high breakdown voltage.

It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 1 of this invention. It is the graph which compared the pressure | voltage resistance of the structure of Embodiment 1 of this invention and the structure which does not have a SiC layer of a prior art example. FIG. 2 is a partial cross-sectional view showing an enlarged part of the capacitively coupled multiple field plate of FIG. 1. It is a figure for demonstrating the role of a capacitive coupling type | mold multiple field plate. It is a figure for demonstrating that the nonuniformity of an electric field distribution is eliminated in the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 1 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 2 of this invention. It is a 1st figure which shows the mode of electric field concentration. It is a 2nd figure which shows the mode of electric field concentration. It is a 3rd figure which shows the mode of electric field concentration. It is a 4th figure which shows the mode of electric field concentration. It is a figure for demonstrating how a breakpoint changes with the increase in the impurity concentration of a SOI layer. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 3 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 4 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 5 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 6 of this invention. It is a graph which shows the impurity concentration distribution along the EE line | wire of FIG. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 7 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 8 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 9 of this invention. It is a schematic sectional drawing in alignment with the FF line of FIG. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 10 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 11 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 12 of this invention. It is a schematic sectional drawing in alignment with the HH line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 13 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 13 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 13 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 13 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 14 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 14 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 14 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 15 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 15 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 15 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device which has a horizontal type high voltage | pressure-resistant element in Embodiment 15 of this invention. It is a schematic sectional drawing which shows the 1st example of the semiconductor device which has the conventional horizontal type high voltage | pressure-resistant element. It is a figure for demonstrating operation | movement of the high voltage | pressure-resistant element shown in FIG. It is a schematic sectional drawing which shows the 2nd example of the semiconductor device which has the conventional horizontal type high voltage | pressure-resistant element. It is a figure for demonstrating operation | movement of the horizontal type high voltage | pressure-resistant element shown in FIG. It is a graph which shows the change of a proof pressure when the film thickness of a buried oxide film is changed. It is a graph which shows the relationship between the oxidation time at the time of forming a buried oxide film by the film-forming method, and an oxide film thickness. It is sectional drawing which shows schematically the structure of the semiconductor device disclosed by the gazette. FIG. 43 is a diagram for explaining that the electric field distribution is unevenly generated in the configuration shown in FIG. 42.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 n ⁻ semiconductor layer, 3 buried insulating layer, 4 n ⁺ semiconductor region, 5 p ⁺ semiconductor region, 6 cathode electrode, 7 anode electrode, 8 back electrode, 11 insulating layer, 20 SiC thin film layer, 31 , 32 Field plate conductive layer.

Claims (3)

A method for manufacturing a semiconductor device, comprising: a semiconductor layer formed on a semiconductor substrate with a buried insulating layer interposed therebetween, wherein a high breakdown voltage element is formed in the semiconductor layer;
Forming a wide band gap layer made of a material having a wider wide band gap than a material of the semiconductor layer by introducing impurities into the semiconductor layer;
A method of manufacturing a semiconductor device having a lateral high breakdown voltage element, comprising a step of bonding a buried insulating layer and a semiconductor substrate to the semiconductor layer having the wide band gap layer.   2. The method of manufacturing a semiconductor device having a lateral high breakdown voltage element according to claim 1, wherein the impurity is introduced into the semiconductor layer through a coating layer formed on the surface of the semiconductor layer. Further comprising the step of forming an amorphous layer in the semiconductor layer by introducing the same element as the element constituting the semiconductor layer into the semiconductor layer,
2. The semiconductor having a lateral high breakdown voltage element according to claim 1, wherein the growth direction of the wide band gap layer is specified by introducing the impurities after forming the amorphous layer to form the wide band gap layer. Device manufacturing method.

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