JP2011091567A - Differential decoding circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential decoding circuit capable of saving circuit scale of a reception processing circuit in a digital communication device corresponding to a plurality of modulation methods. <P>SOLUTION: This differential decoding circuit (55) is applied to a reception processing circuit of a communication device corresponding to a plurality of modulation methods including a differential encoding modulation method, distributes a reception signal to signals of a plurality of systems in accordance with a modulation method designated from among the plurality of modulation methods for performing a decoding process using a signal after the distribution as an input signal. The differential decoding circuit includes: a delay module (55a) to execute delay processing to the input signal to obtain a signal required for differential decoding in accordance with the designated modulation method; a selection module (55b) to select a signal required for the differential decoding from the input signal before the delay and the input signal after the delay in accordance with the designated modulation method; and a calculation module (55c) to perform calculation of the differential decoding to the input signal before the delay and the input signal after the selection by the selection module in accordance with the designated modulation method. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a differential decoding circuit applied to a digital communication apparatus that supports a plurality of modulation schemes.

  As a conventional digital communication apparatus corresponding to a plurality of modulation systems, there is the following one provided with a mapping unit and an amplitude correction unit (for example, see Patent Document 1). The mapping unit converts the transmission signal into a symbol belonging to a part of a set of symbols of the modulation scheme having the maximum multi-level number when the designated modulation scheme does not have the maximum multi-level number in the set of modulation schemes to which the mapping scheme belongs. The amplitude correction unit corrects the amplitude. By providing such a configuration, the same circuit can be shared for processing performed in each modulation method, and the circuit scale is saved.

JP 2006-115393 A

However, the prior art has the following problems.
In the conventional digital communication apparatus corresponding to a plurality of modulation systems, the transmission processing circuit is shared, but the reception processing circuit is not shared. For this reason, there is a problem that the circuit scale of the reception processing circuit increases due to an increase in the corresponding modulation scheme.

  The present invention has been made to solve the above-described problems, and provides a differential decoding circuit capable of saving the circuit scale of a reception processing circuit in a digital communication apparatus corresponding to a plurality of modulation methods. The purpose is to obtain.

  The differential decoding circuit according to the present invention is applied to a reception processing circuit of a communication apparatus corresponding to a plurality of modulation schemes including a differential encoding modulation scheme, and corresponds to a modulation scheme designated from the plurality of modulation schemes. A differential decoding circuit that distributes a received signal to a plurality of signals and performs decoding using the distributed signal as an input signal, and obtains a signal necessary for differential decoding according to a specified modulation method Therefore, a delay unit that performs delay processing on the input signal and a signal necessary for differential decoding are selected from the input signal before the delay and the input signal after the delay according to the designated modulation method. The selection means and an operation means for performing a differential decoding operation on the input signal before the delay and the input signal selected by the selection means in accordance with the designated modulation method.

  The differential decoding circuit according to the present invention has a configuration including a delay circuit, a selector, and an arithmetic circuit, and realizes a plurality of differential decoding processes according to a modulation scheme by using a shared configuration. It is possible to obtain a differential decoding circuit capable of saving the circuit scale of the reception processing circuit in the digital communication apparatus corresponding to the modulation method.

It is a block diagram which shows the detail of the optical transmission / reception circuit containing the differential decoding circuit based on Embodiment 1 of this invention. It is a block diagram of the differential decoding / soft decision which concerns on Embodiment 1 of this invention. FIG. 6 is a diagram showing a signal flow when the modulation scheme is DP-DQPSK in the differential decoding / soft decision of FIG. 2 according to Embodiment 1 of the present invention. FIG. 6 is a diagram showing a signal flow when the modulation scheme is DP-DBPSK in the differential decoding / soft decision of FIG. 2 according to Embodiment 1 of the present invention. It is a block diagram which shows the detail of the optical transmission / reception circuit containing the differential decoding circuit based on Embodiment 2 of this invention. It is a block diagram of the differential decoding / soft decision which concerns on Embodiment 2 of this invention. FIG. 7 is a diagram showing a signal flow when the modulation scheme is DP-DQPSK in the differential decoding / soft decision of FIG. 6 according to Embodiment 2 of the present invention. FIG. 7 is a diagram showing a signal flow when the modulation scheme is SP-DQPSK in the differential decoding / soft decision of FIG. 6 according to Embodiment 2 of the present invention.

  Hereinafter, preferred embodiments of a differential decoding circuit of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing details of an optical transmission / reception circuit including a differential decoding circuit according to Embodiment 1 of the present invention. The optical transmission / reception circuit in FIG. 1 includes an OTUk (k = 0, 1, 2, 3, 4...) (Optical channel Transport Unit-k) framer 10 and a digital signal processing optical transceiver 20. The OTUk framer 10 includes a transmission unit including an OTUk frame generation 11 and a multilane distribution 12, and a reception unit including a multilane synchronization 13 and an OTUk frame termination 14.

  On the other hand, the digital signal processing optical transceiver 20 includes a multi-lane synchronization 21, a soft decision error correction code 22, a multi-lane distribution 23, a differential code 24, a multiplexing 25, a D / A conversion 26, and an E / O conversion 27. And an optical receiving unit including a reception front end 30, an A / D converter 40, and a digital signal processing unit 50.

  Here, the reception front end 30 includes a polarization beam splitter 31 (PBS 31), a local oscillator 32 (LO 32), a polarization beam splitter 33 (PBS 33), a 90 ° optical hybrid 34, an O / E conversion 35, and an AMP 36. ing. Also, the digital signal processing unit 50 includes a demultiplexing & adaptive equalization filter 51, 1: 2 DEMUX 52a, 52b, selectors 53a, 53b (SEL 53a, 53b), multi-lane synchronization 54, differential decoding / soft decision 55, soft decision error. A correction decoding 56 and a multi-lane distribution 57 are provided.

  Next, the operation of the optical transmission / reception circuit shown in FIG. 1 will be described. First, the operation of the OTUk framer 10 will be described. The OTUk frame generator 11 maps the input client transmission signal to the OTUk frame, and adds information necessary for frame synchronization and maintenance control.

  The multi-lane distribution unit 12 distributes the OTUk frame to which the information necessary for the OTUk frame generation 11 is added to a plurality of lanes, and outputs the OTUk frame to the digital signal processing optical transceiver 20 as an SFI (Serdes Framer Interface) transmission signal.

  On the other hand, the multi-lane synchronization 13 synchronizes a plurality of lanes with the SFI transmission signal from the digital signal processing optical transceiver 20 and outputs an OTUk frame to the OTUk frame end 14.

  The OTUk frame termination 14 terminates information necessary for frame synchronization and maintenance control with respect to the OTUk frame synchronized by the multi-lane synchronization 13, demaps the client reception signal from the OTUk frame, and transmits the client reception signal. Output.

  Next, the operation of the digital signal processing optical transceiver 20 will be described. The multi-lane synchronization 21 outputs an SFI transmission signal synchronized between a plurality of lanes to the SFI transmission signal from the OTUk framer 10 to the soft decision error correction code 22.

  The soft decision error correction code 22 is an encoding unit, and performs an encoding process on the SFI transmission signal synchronized by the multilane synchronization 21 with an error correction code for soft decision. The multi-lane distribution 23 distributes the signal after error correction coding to a plurality of lanes. The differential code 24 performs differential encoding on the output of the multilane distribution 23.

  The multiplexing 25 multiplexes the output of the differential code 24. A D / A (digital / analog) converter 26 converts the multiplexed digital signal into an analog signal. The E / O (electric / optical) converter 27 converts the analog electric signal output from the D / A converter 26 into an optical signal and transmits the optical transmission signal to the communication path.

  On the other hand, the reception front end 30 converts an optical reception signal from the communication path into an electrical analog signal. Specifically, the reception front end 30 includes a PBS 31 that separates the X polarization and the Y polarization of the optical signal received from the communication path, a LO 32 for performing coherent reception, and a PBS 33 that performs polarization separation of the LO. The 90 ° optical hybrid 34 that mixes the polarization-separated optical signal and the LO signal, the O / E conversion 35 that converts the received optical signal into an electrical signal, and the AMP 36 that amplifies the O / E converted signal It consists of and. Further, the A / D (analog / digital) converter 40 converts the analog signal received via the AMP 36 into a digital signal.

  Next, the digital signal processing unit 50 performs digital signal processing on the signal after A / D conversion, generates an SFI reception signal, and outputs it to the OTUk framer 10. Specifically, the demultiplexing & adaptive equalization filter 51 in the digital signal processing unit 50 demultiplexes the output of the A / D conversion 40, detects the demultiplexed signal, and receives it on the communication path. Equalize signal distortion.

  The 1: 2 DEMUXs 52a and 52b each distribute the output of the demultiplexing & adaptive equalization filter 51 into two. The SELs 53a and 53b are respectively a signal distributed in two by the 1: 2 DEMUXs 52a and 52b (a signal after the two distributions) and an output signal from the demultiplexing & adaptive equalization filter 51 that is not distributed (a signal before the two distributions). Select either one.

  The multi-lane synchronization 54 synchronizes a plurality of lanes. The differential decoding / soft decision 55 performs differential code decoding and soft decision processing on the output of the multi-lane synchronization 54, and outputs a soft decision value. The soft decision error correction decoder 56 performs a decoding process of an error correction code for soft decision. Further, the multilane distribution 57 outputs the output of the soft decision error correction decoding 56 to the OTUk framer as an SFI reception signal.

  Based on these functions, the reception operation in the digital signal processing optical transceiver 20 of the first embodiment will be described. The digital signal processing optical transceiver 20 according to the first embodiment includes DP (Dual Polarization) -DQPSK (Differential Quadrature Phase Shift Keying) and DP-DBPSK (Differential Quadrature Phase Shift Modulation). To do.

  The received optical signal received from the communication path is separated into a total of four channels, i.e., an X-polarized component and a Y-polarized component, respectively, in the reception front end 30, and detected by the demultiplexing & adaptive equalization filter 51. Is done. When the modulation method is DP-DQPSK, each two information bits are mapped to a set of I channel and Q channel of the X polarization component and the Y polarization component. Therefore, a total of 4 channels of significant signals are output from the demultiplexing & adaptive equalization filter 51.

  On the other hand, when the modulation method is DP-DBPSK, each 1-bit information bit is mapped only to the I channel of each of the X polarization component and the Y polarization component. Therefore, a total of two channels of significant signals are output from the demultiplexing & adaptive equalization filter 51.

  Therefore, the output of the demultiplexing & adaptive equalization filter 51 is distributed to two systems by 1: 2 DEMUXs 52a and 52b. Then, the SELs 53a and 53b select a signal before two distributions when the modulation method is DP-DQPSK, and select a signal after two distributions when the modulation method is DP-DBPSK. As a result, signals for four lanes of lanes 1 to 4 are configured.

  Thus, according to the modulation method, the circuit portion of the previous stage of the digital signal processing unit 50 (that is, the circuit unit including the demultiplexing & adaptive equalization filter 51, 1: 2 DEMUX 52a, 52b, SEL 53a, 53b) Received signals are distributed to 4 lanes.

  Further, the circuit section following the digital signal processing section 50 (that is, the circuit section after the multi-lane synchronization 54) has a common circuit configuration that operates in four lanes regardless of the modulation method. The four lanes are processed by multi-lane synchronization 54, differential decoding / soft decision 55, soft decision error correction decoding 56, and multi-lane distribution 57, so that an SFI reception signal is generated and output to OTUk framer 10 Is done. In particular, the present invention has a technical feature in that the circuit configuration of the differential decoding / soft decision 55 is devised to achieve sharing that can cope with different modulation schemes. The circuit configuration and operation of this differential decoding / soft decision 55 will be described below with reference to FIGS.

  FIG. 2 is a configuration diagram of differential decoding / soft decision 55 according to Embodiment 1 of the present invention. The differential decoding / soft decision 55 (corresponding to the differential decoding circuit) selects four signals from two delay circuits 55a (corresponding to delay means) for delaying the input signals of the lanes 1 to 4 by one clock. Four SELs 55b (corresponding to selecting means) and two arithmetic circuits 55c (computing means) for outputting a soft decision value of two lanes by performing differential code decoding and soft decision processing of the signal of two lanes Equivalent).

  FIG. 3 is a diagram showing a signal flow when the modulation scheme is DP-DQPSK in the differential decoding / soft decision 55 of FIG. 2 according to Embodiment 1 of the present invention. The operation of differential decoding / soft decision 55 when the modulation method is DP-DQPSK will be described in detail with reference to FIG. Signals corresponding to the X polarization component I channel, the X polarization component Q channel, the Y polarization component I channel, and the Y polarization component Q channel of the received signal at time k (k is an integer) on the optical communication path are respectively XI. (K), XQ (k), YI (k), YQ (k) are set.

  When the modulation method is DP-DQPSK, signals that have not been distributed to the two systems by the above-described 1: 2 DEMUXs 52a and 52b (signals before the two distributions) are input to the differential decoding / soft decision 55. Therefore, lane 1 has XI (k), XI (k + 1), XI (k + 2),..., And lane 2 has XQ (k), XQ (k + 1), XQ (k + 2),. Lane 3 has YI (k), YI (k + 1), YI (k + 2),..., And lane 4 has YQ (k), YQ (k + 1), YQ (k + 2),. Input every clock.

  Here, processing of XI (k) and XQ (k) will be described. XI (k-1) and XQ (k-1) are signals one clock before XI (k) and XQ (k), respectively, and are obtained by the delay circuit 55a. In SEL 55b, XI (k-1) and XQ (k-1) are selected and input to the arithmetic circuit 55c together with XI (k) and XQ (k).

  In DQPSK modulation, two information bits are mapped to the difference between XI (k) and XQ (k) based on XI (k-1) and XQ (k-1). Therefore, the two soft decision values obtained by demapping them by the arithmetic circuit 55c are output to lane 1 and lane 2, respectively. For YI (k) and YQ (k), the same processing as XI (k) and XQ (k) is performed, and the obtained soft decision values are output to Lane 3 and Lane 4, respectively. The above process is the same regardless of the value of time k.

  On the other hand, FIG. 4 is a diagram showing a signal flow when the modulation scheme is DP-DBPSK in the differential decoding / soft decision 55 of FIG. 2 according to Embodiment 1 of the present invention. The operation of differential decoding / soft decision 55 when the modulation method is DP-DBPSK will be described in detail with reference to FIG.

  When the modulation method is DP-DBPSK, I-channel signals distributed in two systems by the above-described 1: 2 DEMUXs 52a and 52b are input. Therefore, lane 1 has XI (k), XI (k + 2), XI (k + 4),..., Lane 2 has XI (k + 1), XI (k + 3), XI (k + 5),. Lane 3 has YI (k), YI (k + 2), YI (k + 4),..., Lane 4 has YI (k + 1), YI (k + 3), YI (k + 5),. Input every clock.

  Here, processing of XI (k) and XI (k + 1) will be described. XI (k−1) is a signal one clock before XI (k + 1), and is obtained by the delay circuit 55a. In SEL55b, XI (k-1) and XI (k) are selected and input together with XI (k) and XI (k + 1) to the arithmetic circuit 55c.

  In DBPSK modulation, each 1-bit information bit is mapped to a difference between XI (k) with XI (k−1) as a reference and a difference between XI (k + 1) with XI (k) as a reference. Therefore, two soft decision values obtained by demapping these by the arithmetic circuit 55c are output to lane 1 and lane 2, respectively. For YI (k) and YI (k + 1), the same processing as XI (k) and XI (k + 1) is performed, and the obtained soft decision values are output to Lane 3 and Lane 4, respectively. The above process is the same regardless of the value of time k.

  In the prior art, when performing decoding processing corresponding to two modulation schemes, DP-DQPSK and DP-DBPSK, it is necessary to provide individual differential decoding / soft decision 55. On the other hand, in the first embodiment, by providing the delay circuit 55a and the SEL 55b before the arithmetic circuit 55c, the differential decoding / soft decision 55 can be shared by two modulation schemes.

  As described above, according to the first embodiment, the differential decoding process corresponding to the modulation method is performed using the differential decoding / soft decision including the delay circuit, the SEL, and the arithmetic circuit. Thereby, differential decoding / soft decision can be shared for two modulation schemes, DP-DQPSK and DP-DBPSK. As a result, it is possible to save the circuit scale of the reception processing circuit in the digital communication apparatus corresponding to a plurality of modulation methods.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing details of an optical transmission / reception circuit including a differential decoding circuit according to Embodiment 2 of the present invention. The configuration of FIG. 5 in the optical transmission / reception circuit of the second embodiment is different from the configuration of FIG. 1 in the optical transmission / reception circuit of the first embodiment in that the demultiplexing & adaptive equalization filter 51 and the multilane synchronization 54 are different from each other. The connection of 1: 2 DEMUX 52a, 52b and SEL 53a, 53b is different. Other configurations are the same as those of the first embodiment. Therefore, this different configuration will be mainly described below.

  A reception operation in the digital signal processing optical transceiver 20 according to the second embodiment will be described. The digital signal processing optical transceiver 20 according to the second embodiment corresponds to two differential encoding modulation schemes of DP-DQPSK and SP (Single Polarization) -DQPSK.

  The received optical signal received from the communication path is separated into a total of four channels, i.e., an X-polarized component and a Y-polarized component, respectively, in the reception front end 30, and detected by the demultiplexing & adaptive equalization filter 51. Is done. When the modulation method is DP-DQPSK, each two information bits are mapped to a set of I channel and Q channel of the X polarization component and the Y polarization component. Therefore, a total of 4 channels of significant signals are output from the demultiplexing & adaptive equalization filter 51.

  On the other hand, when the modulation method is SP-DQPSK, 2 information bits are mapped only to the pair of the I channel and the Q channel of the X polarization component. Therefore, a total of two channels of significant signals are output from the demultiplexing & adaptive equalization filter 51.

  Therefore, the output of the demultiplexing & adaptive equalization filter 51 is distributed to two systems by 1: 2 DEMUXs 52a and 52b. Then, the SELs 53a and 53b select a signal before the two distributions when the modulation method is DP-DQPSK, and select a signal after the two distributions when the modulation method is SP-DQPSK. As a result, signals for four lanes of lanes 1 to 4 are configured.

  Thus, according to the modulation method, the circuit portion of the previous stage of the digital signal processing unit 50 (that is, the circuit unit including the demultiplexing & adaptive equalization filter 51, 1: 2 DEMUX 52a, 52b, SEL 53a, 53b) Received signals are distributed to 4 lanes.

  Further, the circuit section following the digital signal processing section 50 (that is, the circuit section after the multi-lane synchronization 54) has a common circuit configuration that operates in four lanes regardless of the modulation method. The four lanes are processed by multi-lane synchronization 54, differential decoding / soft decision 55, soft decision error correction decoding 56, and multi-lane distribution 57, so that an SFI reception signal is generated and output to OTUk framer 10 Is done. In particular, the present invention has a technical feature in that the circuit configuration of the differential decoding / soft decision 55 is devised to achieve sharing that can cope with different modulation schemes. The circuit configuration and operation of this differential decoding / soft decision 55 will be described below with reference to FIGS.

  FIG. 6 is a configuration diagram of the differential decoding / soft decision 55 according to Embodiment 2 of the present invention. The configuration in FIG. 6 differs from the configuration in FIG. 2 in the first embodiment in the connection between the delay circuit 55a and the SEL 55b. Other configurations are the same as those in the first embodiment.

  FIG. 7 is a diagram showing a signal flow when the modulation scheme is DP-DQPSK in the differential decoding / soft decision 55 of FIG. 6 according to Embodiment 2 of the present invention. The operation of differential decoding / soft decision 55 when the modulation method is DP-DQPSK is the same as the operation of FIG. 3 in the first embodiment.

  On the other hand, FIG. 8 is a diagram showing a signal flow when the modulation scheme is SP-DQPSK in the differential decoding / soft decision 55 of FIG. 6 according to Embodiment 2 of the present invention. The operation of differential decoding / soft decision 55 when the modulation method is SP-DQPSK will be described in detail with reference to FIG.

  When the modulation method is SP-DQPSK, the X-polarized component signal distributed to the two systems by the above-described 1: 2 DEMUXs 52a and 52b (the signal after the two distributions) is input. Therefore, lane 1 has XI (k), XI (k + 2), XI (k + 4),..., And lane 2 has XQ (k), XQ (k + 2), XQ (k + 4),. Lane 3 has XI (k + 1), XI (k + 3), XI (k + 5),... Lane 4 has XQ (k + 1), XQ (k + 3), XQ (k + 5),. Input every clock.

  Here, processing of XI (k) and XQ (k) will be described. XI (k-1) and XQ (k-1) are signals one clock before XI (k + 1) and XQ (k + 1), respectively, and are obtained by the delay circuit 55a. In SEL 55b, XI (k-1) and XQ (k-1) are selected and input to the arithmetic circuit 55c together with XI (k) and XQ (k).

  In SP-DQPSK modulation, two information bits are mapped to the difference between XI (k) and XQ (k) based on XI (k-1) and XQ (k-1). Therefore, two soft decision values obtained by demapping these by the arithmetic circuit 55c are output to lane 1 and lane 2, respectively.

  Next, processing of XI (k + 1) and XQ (k + 1) will be described. In SEL 55b, XI (k) and XQ (k) are selected and input to the arithmetic circuit 55c together with XI (k + 1) and XQ (k + 1).

  In SP-DQPSK modulation, two information bits are mapped to the difference between XI (k + 1) and XQ (k + 1) based on XI (k) and XQ (k). Therefore, two soft decision values obtained by demapping these by the arithmetic circuit 55c are output to lane 3 and lane 4, respectively.

  In the prior art, it is necessary to provide individual differential decoding / soft decision 55 when performing decoding processing corresponding to two modulation schemes, DP-DQPSK and SP-DQPSK. On the other hand, in the second embodiment, by providing the delay circuit 55a and the SEL 55b before the arithmetic circuit 55c, the differential decoding / soft decision 55 can be shared by two modulation schemes.

  As described above, according to the first embodiment, the differential decoding process corresponding to the modulation method is performed using the differential decoding / soft decision including the delay circuit, the SEL, and the arithmetic circuit. As a result, differential decoding / soft decision can be shared for two modulation schemes, DP-DQPSK and SP-DQPSK. As a result, it is possible to save the circuit scale of the reception processing circuit in the digital communication apparatus corresponding to a plurality of modulation methods.

  In the first and second embodiments described above, a case has been described in which a circuit for performing differential decoding and soft decision processing is shared. However, the differential decoding circuit of the present invention is not limited to this, and any circuit having a differential decoding function can be applied, and similar effects can be obtained.

  In the first and second embodiments, the case where two modulation schemes are used has been described. However, the present invention is not limited to this, and can also be applied to a plurality of modulation schemes including three or more differential encoding modulation schemes, and similar effects can be obtained.

  In the first and second embodiments described above, a case has been described in which four channels are each configured by one system of signals, and four lanes at the input of differential decoding / soft decision are each configured by one system of signals. However, the present invention is not limited to this, and is distributed to n systems of signals per channel in the previous stage, each of the m channels is composed of n systems of signals, and each i lane at the input of differential decoding / soft decision is The present invention can also be applied to the case of j signals (m, n, i, j are positive integers), and the same effect can be obtained.

  10 OTUk framer, 11 OTUk frame generation (OTUk frame generation circuit), 12 multilane distribution (multilane distribution circuit), 13 multilane synchronization (multilane synchronization circuit), 14 OTUk frame termination (OTUk frame termination circuit), 20 digital Signal processing optical transceiver, 21 Multilane synchronization (Multilane synchronization circuit), 22 Soft decision error correction code (Soft decision error correction code circuit), 23 Multilane distribution (Multilane distribution circuit), 24 Differential code (Differential code) Circuit), 25 multiplexing (multiplexing circuit), 26 D / A conversion (D / A conversion circuit), 27 E / O conversion (E / O conversion circuit), 30 reception front end (reception front end circuit), 31 Polarization beam splitter (polarization beam splitter circuit), 32 local off Oscillator (local oscillator circuit), 33 polarization beam splitter (polarization beam splitter circuit), 34 90 ° optical hybrid (90 ° optical hybrid circuit), 35 O / E conversion (O / E conversion circuit), 36 AMP (amplification) Circuit), 40 A / D conversion (A / D conversion circuit), 50 digital signal processing unit, 51 demultiplexing & adaptive equalization filter (demultiplexing & adaptive equalization filter circuit), 52a, 52b 1: 2 DEMUX (1: 2DEMUX circuit), 53a, 53b SEL (SEL circuit), 54 multilane synchronization (multilane synchronization circuit), 55 differential decoding / soft decision (differential decoding / soft decision circuit), 55a delay circuit, 55b SEL (SEL circuit) ), 55c arithmetic circuit, 56 soft decision error correction decoding (soft decision error correction decoding circuit), 57 multilane distribution (multi Chilane distribution circuit).

Claims (2)

Applied to a reception processing circuit of a communication apparatus corresponding to a plurality of modulation methods including a differential encoding modulation method, and a received signal is converted into a plurality of signals according to a modulation method designated from the plurality of modulation methods. A differential decoding circuit for performing a decoding process using the distributed signal as an input signal,
Delay means for performing a delay process on the input signal in order to obtain a signal necessary for differential decoding according to the designated modulation scheme;
Selecting means for selecting a signal necessary for the differential decoding from an input signal before delay and an input signal after delay according to the designated modulation method;
Differential decoding, comprising: an arithmetic means for performing differential decoding on the input signal before the delay and the input signal selected by the selection means in accordance with the designated modulation method circuit. The differential decoding circuit according to claim 1,
The communication device is a communication device that transmits a client transmission signal as an optical transmission signal and receives a client reception signal as an optical reception signal,
The differential decoding circuit, wherein the plurality of modulation schemes are any two or more of DP-DQPSK, DP-DBPSK, and SP-DQPSK.

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