JP2011082743A - Optical signal receiving circuit, and method for controlling the optical signal receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of an optical signal receiving circuit, while maintaining communication quality. <P>SOLUTION: The optical signal receiving circuit includes a light detection means for converting a received optical signal into an electrical signal to be output with receiving sensitivity, according to bias voltage applied by a control means; a comparison signal generation means for generating a signal with the same period as that of the electrical signal output by the optical detection means and at a voltage increase and decrease process with the timing of transition of the electrical signal as a comparison signal to be compared with the electric signal; and a control means for calculating the variation of the voltage of the comparison signal, when a result obtained by comparing the voltage of the electrical signal output by the light detection means with the voltage of the comparison signal generated by the comparison signal generation means changes as a jitter amount of the electrical signal, and controlling the bias voltage to the light detection means so that the jitter amount becomes equal to or more than an upper limit value and equal to or less than a lower limit value. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for detecting an optical signal in an optical signal receiving circuit.

  In recent years, as a response to global warming and energy problems, low power consumption of electronic devices is desired. In addition, the demand for optical fiber communication is increasing with the progress of IT (Information Technology) in the world, and optical fibers are often used for communication networks. Also in the optical receiver provided in this optical communication network, it is desirable to reduce power consumption.

  In an optical receiver, an APD (avalanche photo diode) having high reception sensitivity is often used.

  For example, as shown in FIG. 11, the optical receiver described in Patent Document 1 measures the relationship between the APD bias and the signal error rate in advance and stores it in a storage device. A bias voltage that minimizes the rate is applied to the APD. According to this method, the optical receiver can always keep the reception sensitivity at the maximum regardless of the ambient temperature.

  In addition, as shown in FIG. 12, the optical receiver described in Patent Document 2 is provided with a resistor between the bias voltage generation circuit and the APD, and applied to the APD using a voltage drop generated in the resistor. To control the bias voltage. When the power of the received optical signal is high, the voltage drop due to the resistor increases, and the bias voltage applied to the APD decreases. According to this method, since the optical receiver adjusts the bias voltage applied to the APD according to the received optical signal power, the load current flowing through the APD is limited and power consumption is ensured while ensuring the desired reception sensitivity. Can be reduced.

  The optical receiver described in Patent Document 3 incorporates a D-FF (Delay Flip Flop), and outputs a binarized equalized data signal and a clock signal whose phase is shifted by 90 degrees with respect to the signal. To enter. When the jitter width of the binarized equalized data signal exceeds the pulse width of the clock signal, the output of the D-FF changes from 1 to 0. For this reason, the optical receiver can detect the amount of jitter more than a predetermined value from the output of the D-FF. The optical receiver controls the bias voltage of the APD so that the detected jitter is minimized.

JP 2008-148068 A JP 2000-171295 A JP 2003-258924 A

  However, in the optical receivers (optical signal receiving circuits) described in Patent Documents 1 to 3, it is difficult to reduce power consumption while maintaining communication quality.

  The optical receiver described in Patent Document 1 controls the bias voltage so that the reception sensitivity is always maximized. Since it is necessary to increase the bias voltage in order to increase the receiving sensitivity, the optical receiver sets the bias voltage high. However, when the communication distance is relatively short, the reception sensitivity of the optical receiver is not necessarily high. This is because sufficient communication quality can be maintained if there is a certain level of reception sensitivity. If the bias voltage is increased more than necessary, power is wasted.

  The optical receiver described in Patent Document 2 uses the loss due to the resistor for bias voltage control, and thus there is a problem in that the power corresponding to that is wasted.

  The optical receiver described in Patent Document 3 controls the bias voltage so that the jitter amount is always minimized. In order to reduce the amount of jitter, the bias voltage must be increased. However, it may not be necessary to reduce the amount of jitter so much on a line with low required communication quality. Even in such a case, since this optical receiver applies a high bias voltage so as to minimize the amount of jitter, power is wasted due to the application of a bias voltage larger than necessary. There was a thing.

  In order to reduce the power consumption, the bias voltage may be lowered. However, in some cases, communication quality may not be maintained.

  As described above, in the optical signal receiving circuits described in Patent Documents 1 to 3, it is difficult to reduce power consumption while maintaining communication quality.

  An object of the present invention is to reduce power consumption of an optical signal receiving circuit while maintaining communication quality.

  In order to achieve the above object, the optical signal receiving circuit of the present invention converts the received optical signal into an electrical signal and outputs it with a receiving sensitivity corresponding to the bias voltage applied by the control means. And a signal for which the period is the same as that of the electric signal output by the light detecting means and whose voltage is increasing or decreasing at the timing of transition of the electric signal, for comparison with the electric signal. The result of comparing the voltage of the comparison signal generation means generated as a signal, the voltage of the electrical signal output by the light detection means, and the voltage of the comparison signal generated by the comparison signal generation means has changed. The amount of fluctuation of the voltage of the comparison signal at the time is calculated as the jitter amount of the electrical signal, and the bias to the light detection means is set so that the jitter amount is not less than the upper limit value and not more than the lower limit value. A control means for controlling the pressure, the.

  According to the control method of the optical signal receiving circuit of the present invention, the light detecting means converts the received optical signal into an electric signal with a receiving sensitivity according to the applied bias voltage and outputs the electric signal, and the cycle is the same as the electric signal. Then, a signal whose voltage is increasing or decreasing at the transition timing of the electrical signal is generated as a comparison signal for comparison with the electrical signal, and the voltage of the electrical signal is compared with the voltage of the comparison signal. The fluctuation amount of the voltage of the comparison signal at the time when the result is changed is calculated as the jitter amount of the electrical signal, and the jitter amount is not less than the upper limit value and not more than the lower limit value. This is a method for controlling an optical signal receiving circuit for controlling the bias voltage of the optical signal receiving circuit.

  According to the present invention, the optical signal receiving circuit generates a comparison signal whose period is the same as that of the received voltage signal and whose voltage is increasing or decreasing at the transition timing, and compares the voltage of the received voltage signal with the voltage of the comparison signal. A bias voltage is applied so that the amount of fluctuation of the voltage of the comparison signal, that is, the jitter amount at the time when the result changes, is not less than the lower limit and not more than the upper limit. Since a lower limit is provided for the jitter amount, a bias voltage higher than necessary is not applied. Further, since the upper limit value is set for the jitter amount, the communication quality is maintained. As a result, the optical signal receiving circuit can reduce power consumption while maintaining communication quality.

It is a circuit diagram which shows one structural example of the optical signal receiving circuit of this invention. It is a circuit diagram which shows one structural example of the jitter detection circuit of this invention. It is an example of the graph which shows the relationship between the multiplication factor and bias voltage of this invention. It is an example of the graph which shows the relationship between SNR and multiplication factor of this invention. It is an example of the graph which shows the relationship between the jitter amount of this invention, and SNR. (A) It is a figure which shows an example of the output jitter waveform of this invention. (B) It is a figure which shows an example of the output jitter waveform of this invention. It is an example of the graph which shows the relationship between the signal error rate of this invention, and SNR. (A) It is a figure which shows the waveform of the received data signal of this invention. (B) It is a figure which shows the waveform of the clock signal of this invention. (C) It is a figure which shows an example of the waveform of the received data signal of this invention. (D) It is a figure which shows an example of the waveform of the ramp signal of this invention. (E) It is a figure which shows an example of the waveform of the hold signal of this invention. (A) It is a figure which shows the waveform of the received data signal of this invention. (B) It is a figure which shows the waveform of the clock signal of this invention. (C) It is a figure which shows an example of the waveform of the received data signal of this invention. (D) It is a figure which shows an example of the waveform of the ramp signal of this invention. (E) It is a figure which shows an example of the waveform of the hold signal of this invention. It is a flowchart which shows an example of operation | movement of the arithmetic circuit of this invention. It is a circuit diagram which shows one structural example of a general optical signal receiving circuit. It is a circuit diagram which shows one structural example of a general optical signal receiving circuit.

  DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of an optical signal receiving circuit 1 of the present invention. The optical signal receiving circuit 1 is a circuit that receives an optical signal and converts the optical signal into an electric signal for processing. Referring to the figure, the optical signal receiving circuit 1 includes a bias voltage generation circuit 10, an APD 11, a preamplifier 12, a limit amplifier 13, a clock detection circuit 14, a jitter detection circuit 15, and a bias voltage control circuit. 16.

  The bias voltage generation circuit 10 applies a bias voltage generated by receiving power from a low voltage power supply to the APD 11. The bias voltage generation circuit 10 changes the bias voltage to be applied under the control of the bias voltage control circuit 16. For example, a switching regulator is used as the bias voltage generation circuit 10.

  The APD 11 receives the optical signal and converts it into an electrical signal. The APD 11 outputs a received current signal corresponding to the optical power of the received optical signal to the preamplifier 12. Further, when a bias voltage equal to or higher than the breakdown voltage is applied, the APD 11 internally amplifies the received current signal with a multiplication factor corresponding to the bias voltage due to the avalanche effect. The higher the bias voltage, the higher the multiplication factor.

  The higher the bias voltage, the higher the multiplication factor and the higher the light receiving sensitivity, but the power consumption of the optical signal receiving circuit 1 increases. Conversely, the lower the bias voltage, the lower the power consumption. For example, consider the case where the power conversion efficiency of the bias voltage generation circuit 10 is 50% and the voltage of the low voltage power supply is 3.3V.

  When the bias voltage generation circuit 10 applies a bias voltage of 50 V and the APD 11 generates a current of 1 mA, the current consumption on the secondary side of the bias voltage generation circuit 10, that is, the low voltage power supply side is about 30 mA. When the bias voltage generation circuit 10 reduces the bias voltage to 25 V, the multiplication factor is reduced as described above, and thus the current generated by the APD 11 is 100 μA. At this time, the current consumption on the secondary side of the bias voltage generation circuit 10 is about 1.5 mA. Thus, the power consumption is reduced by lowering the bias voltage.

  The preamplifier 12 converts the received current signal from the APD 11 into a received voltage signal and outputs it to the limit amplifier 13. The signal error rate of the optical signal receiving circuit 1 is determined by the SNR of the received voltage signal.

  The limit amplifier 13 amplifies the received voltage signal from the preamplifier 12 and converts it to a binary digital signal by limiting it with a predetermined voltage value. At this time, jitter corresponding to the SNR of the received voltage signal is superimposed on the binary digital signal. The limit amplifier 13 outputs the binary digital signal to the outside of the clock detection circuit 14, the jitter detection circuit 15, and the optical signal reception circuit 1.

  The clock detection circuit 14 extracts a clock signal from the binary digital signal and outputs it to the jitter detection circuit 15.

  The jitter detection circuit 15 uses the clock signal from the clock detection circuit 14 to detect the jitter of the binary data signal. Then, the jitter detection circuit 15 outputs a control signal for controlling the bias voltage to the bias voltage control circuit 16 according to the jitter amount of the detected jitter. Details of the jitter detection method will be described later with reference to FIG.

  The bias voltage control circuit 16 changes the bias voltage applied to the bias voltage generation circuit 10 based on a control signal from the jitter detection circuit 15.

  The configuration of the jitter detection circuit 15 will be described in detail. FIG. 2 is a block diagram illustrating a configuration example of the jitter detection circuit 15. Referring to the figure, the jitter detection circuit 15 includes a ramp waveform generation circuit 151, a comparator 152, a sample hold circuit 153, and an arithmetic circuit 154.

  The ramp waveform generation circuit 151 receives the clock signal from the clock detection circuit 14. The ramp waveform generation circuit 151 generates a sawtooth ramp signal synchronized with the clock signal and outputs the ramp signal to the comparator 152 and the sample hold circuit 153.

  A binary digital signal from the limit amplifier 13 is input to one input terminal of the comparator 152, and a ramp signal from the ramp waveform generation circuit 151 is input to the other input terminal. The comparator 152 compares the voltage of the binary digital signal with the voltage of the ramp signal, and outputs a comparator output signal indicating the comparison result to the sample hold circuit 153.

  The sample hold circuit 153 samples the ramp signal at the rising or falling timing of the comparator output signal from the comparator 152, or both, and holds it for a predetermined time. Then, the sample hold circuit 153 outputs the held signal to the arithmetic circuit 154 as a hold signal.

  The arithmetic circuit 154 statistically processes the fluctuation of the voltage of the hold signal and measures the jitter amount of the binary digital signal.

  If the amount of jitter is large in the binary digital signal, the difference between the transition timing such as the rise of the binary digital signal and the transition timing of the clock signal is statistically large. For this reason, the deviation between the transition timing of the comparator output signal indicating the comparison result of the binary digital signal and the ramp signal and the transition timing of the clock signal is also statistically large.

  As a result, the fluctuation of the voltage of the ramp signal sampled at the transition timing of the comparator output signal, that is, the voltage of the hold signal increases. Conversely, if the amount of jitter is small, the variation in the voltage of the hold signal is small.

  Therefore, the arithmetic circuit 154 can measure the jitter amount of the binary digital signal from the statistical amount of the voltage of the hold signal. The statistic is, for example, a variance value.

  The arithmetic circuit 154 outputs a control signal for controlling the bias voltage to the bias voltage control circuit 16 so that the jitter amount falls within a predetermined range. For example, in the arithmetic circuit 154, a lower limit value and an upper limit value of the jitter amount are set in advance according to the signal error rate required for the communication line. Then, the arithmetic circuit 154 controls the bias voltage so that the jitter amount is not less than the lower limit value and not more than the upper limit value.

  More specifically, when the jitter amount is larger than the upper limit value, the arithmetic circuit 154 gradually increases the bias voltage by a predetermined value until the jitter amount becomes smaller than the lower limit value. When the jitter amount is smaller than the lower limit value, the arithmetic circuit 154 gradually decreases the bias voltage by a predetermined value until the jitter amount becomes larger than the upper limit value.

  Here, the grounds for increasing or decreasing the bias voltage as described above will be described with reference to FIGS.

  FIG. 3 is an example of a graph showing the relationship between the bias voltage and the multiplication factor. The vertical axis in the figure is the multiplication factor M of the APD 11. The horizontal axis represents the bias voltage Vh (V) applied to the APD 11. Referring to the figure, when the bias voltage Vh is 50V, the multiplication factor M is 20, and when the bias voltage Vh is 25V, the multiplication factor M is 2. Thus, as the bias voltage increases, the multiplication factor of the APD 11 increases.

  For example, consider a case where the APD 11 generates a current of 1 mA when the bias voltage Vh is 50V. When the bias voltage is lowered to 25 V, the multiplication factor M decreases from 20 to 2 to 1/10. As a result, the current generated in the APD 11 is 1/10, 100 μA.

  FIG. 4 is an example of a graph showing the relationship between the SNR (Signal to Noise Ratio) of the received voltage signal and the multiplication factor M of the APD 11. In the figure, “◯” is a plot of the calculated values when the optical power Pr based on 1 mW is −35 (dB). “Δ” is a plot of the calculated values when the optical power Pr based on 1 mW is −32 (dB). “□” is a plot of the calculated values when the optical power Pr based on 1 mW is −29 (dB).

  This graph plots the SNR calculated for each M by the following equation.

In the above (Formula 1), “reception signal power” is the optical power of the optical signal received by the APD 11. “M” is the multiplication factor of the APD 11, and “Ip” is the peak value [A] of the received current signal of the APD 11. “Ir” is the average value [A] of the received current signal of the APD 11. “Id” is a dark current [A] that flows when an optical signal is not input to the APD 11. “E” is the elementary charge [C]. “B” is the frequency band [Hz] of the optical signal receiving circuit 1. “X” is the excess noise figure. “K” is the Boltzmann constant [J / K]. “T” is the temperature [K]. “N” is the noise figure of the preamplifier 12. “R” is the feedback resistance value [Ω] of the preamplifier 12.

  From the above (Equation 1), as the multiplication factor M is increased, the received signal power is increased and the SNR is increased. However, if the multiplication factor M is larger than a certain value, the shot noise power increases, so the SNR decreases. Further, as the received signal power increases, the SNR increases even at the same multiplication factor M.

  For example, when the received signal power, that is, the optical power is −35 dB, the SNR is a maximum value of 23 (dB) when M is 20. When the received signal power is -29 dB, the SNR when M is 20 is 26 (dB). In order to obtain an SNR of 23 (dB) or more when the received signal power is -29 dB, M may be 2 or more.

  That is, when the received signal power is large, the value of the multiplication factor M does not have to be so high as compared with the case where the received signal power is low.

  FIG. 5 is an example of a graph showing the relationship between the jitter amount of the binary digital signal and the SNR. As shown in the figure, the larger the SNR, the smaller the jitter amount.

  FIG. 6A is an example of a binary digital signal waveform when the SNR is 23 (dB). The jitter amount at this time is 150 (Ulpp). FIG. 6B is an example of a binary digital signal waveform when the SNR is 20 (dB). The jitter amount at this time is 200 (Ulpp). The widths of the arrows in FIGS. 9A and 9B correspond to the amount of waveform fluctuation, that is, the amount of jitter. As shown in FIGS. 9A and 9B, the amount of jitter decreases as the SNR increases.

  In summary, from FIG. 3, the multiplication factor M increases as the bias voltage increases. From FIG. 4, the SNR increases as the multiplication factor M increases. From FIG. 5 and FIG. 6, the larger the SNR, the smaller the jitter amount.

  Accordingly, as the bias voltage is increased, the multiplication factor M is increased, the SNR is increased, and the amount of jitter is reduced. Conversely, as the bias voltage is decreased, the multiplication factor M is decreased, the SNR is decreased, and the jitter amount is increased.

  For this reason, the arithmetic circuit 154 may increase the bias voltage when it is desired to reduce the jitter amount, and lower the bias voltage when it is desired to increase the jitter amount.

  Next, how to determine the upper limit value and the lower limit value of the jitter amount will be described with reference to FIG.

  FIG. 7 is an example of a graph showing the relationship between the signal error rate and the SNR of the binary digital signal. In the figure, the vertical axis represents the signal error rate, and the horizontal axis represents the SNR. As shown in the figure, there is a unique relationship between the signal error rate and the SNR, and the signal error rate decreases as the SNR increases.

For example, in order to reduce the signal error rate to e ^-12 or less, it is necessary to keep the SNR at 25 (dB) or more.

  From FIG. 7, the lower limit value of the SNR necessary for maintaining the signal error rate necessary for the communication line is obtained. From FIG. 5, the upper limit value of the jitter amount corresponding to the lower limit value of the SNR is obtained.

  The lower limit value of the jitter amount will be described. From FIG. 4, the maximum value of SNR corresponding to the received signal power is obtained. From FIG. 5, the value of the jitter amount corresponding to the maximum value of the SNR is obtained, and a value that is not less than the obtained value and less than the upper limit value of the jitter amount may be set as the lower limit value of the jitter amount.

  Next, the relationship between the fluctuation of the hold signal voltage and the jitter amount will be described with reference to FIGS.

  A case where the amount of jitter is small will be described. FIG. 8A is a waveform diagram of the binary digital signal S when the jitter amount is small. FIG. 4B is a waveform diagram of the clock signal extracted from the binary digital signal. FIG. 2C is an example of a waveform diagram at a certain time of the binary digital signal of FIG. FIG. 4D is a waveform diagram of the ramp signal synchronized with the clock signal. FIG. 4E is an example of a waveform diagram of a comparator output signal showing a comparison result between the binary digital signal of FIG. 4C and the ramp signal of FIG. In FIGS. 4A to 4E, the vertical axis represents the signal voltage, and the horizontal axis represents time.

  As shown in FIG. 8C, consider a case where a binary digital signal that is at a high level is input at the rising timing of the clock signal.

  As shown in FIGS. 8A and 8B, when the amount of jitter is small, the deviation between the rising or falling timing of the binary digital signal and the rising timing of the clock signal is statistically ,Few.

  For this reason, as shown in FIG. 8E, the comparator output signal becomes high level almost at the rising timing of the clock signal. As shown in FIG. 4D, the voltage Ra of the ramp signal at the rising timing of the comparator output signal is held and output as a hold signal. As described above, when the amount of jitter is small, the shift between the clock signal transition timing and the binary digital signal transition timing is small, so that the hold signal voltage (Ra and the like) is less varied.

  A case where the amount of jitter is large will be described. FIG. 9A is a waveform diagram of the binary digital signal S when the amount of jitter is large. FIG. 4B is a waveform diagram of the clock signal extracted from the binary digital signal. FIG. 2C is an example of a waveform diagram at a certain time of the binary digital signal of FIG. FIG. 4D is a waveform diagram of the ramp signal synchronized with the clock signal. FIG. 4E is an example of a waveform diagram of a comparator output signal showing a comparison result between the binary digital signal of FIG. 4C and the ramp signal of FIG. In FIGS. 4A to 4E, the vertical axis represents the signal voltage, and the horizontal axis represents time.

  As shown in FIG. 9C, consider a case where a binary digital signal that should be at a high level is input several times at the rising timing of the clock signal.

  As shown in FIGS. 9A and 9B, when the amount of jitter is large, the deviation between the rising or falling timing of the binary digital signal and the rising timing of the clock signal is statistically And more.

  For this reason, as shown in FIG. 9E, the comparator output signal does not always become high level at the rising timing of the clock signal. As shown in FIG. 4D, the ramp signal voltage at the rising edge of the comparator output signal has a large variation such as Ra, Rb, and Rc because the sampling timing is different.

  As shown in FIG. 8, the smaller the jitter amount, the smaller the variation in the hold signal voltage. As shown in FIG. 9, the hold signal voltage variation is proportional to the jitter amount. Therefore, the arithmetic circuit 154 can estimate the jitter amount by calculating a statistic such as the dispersion of the voltage of the hold signal.

  The operation of the arithmetic circuit 154 will be described with reference to FIG. This figure is a flowchart showing the operation of the arithmetic circuit 154. This operation starts when the optical signal receiving circuit 1 is turned on.

  The arithmetic circuit 154 outputs a control signal for increasing the bias voltage by a predetermined value ΔV (step S1). As a result, the multiplication factor M is high, the SNR is increased, and the jitter amount is reduced.

  The arithmetic circuit 154 measures the jitter amount from the fluctuation of the voltage of the hold signal (step S2). The arithmetic circuit 154 determines whether or not the jitter amount is smaller than the lower limit value (step S3).

  If the jitter amount is greater than or equal to the lower limit (step S3: NO), the arithmetic circuit 154 returns to step S1.

  If the jitter amount is smaller than the lower limit (step S3: YES), the arithmetic circuit 154 outputs a control signal for reducing the bias voltage by a predetermined value ΔV (step S4). As a result, the multiplication factor M is low, the SNR becomes small, and the jitter amount increases.

  The arithmetic circuit 154 measures the jitter amount from the fluctuation of the voltage of the hold signal (step S5). The arithmetic circuit 154 determines whether or not the jitter amount is larger than the upper limit value (step S6).

  If the jitter amount is less than or equal to the upper limit value (step S6: NO), the arithmetic circuit 154 returns to step S4. If the jitter amount is larger than the upper limit value (step S6: YES), the arithmetic circuit 154 returns to step S1.

  In this embodiment, the optical signal receiving circuit receives an optical signal by APD. However, a device other than the APD may be used for receiving an optical signal as long as the device can control the optical signal reception sensitivity. it can.

  For example, the optical signal receiving circuit may receive an optical signal with a photomultiplier tube instead of the APD. Also, instead of APD, an amplification device such as an optical amplifier is placed in the previous stage, and a photodiode without a multiplication effect such as a PIN photodiode is placed in the subsequent stage, and the optical signal receiving circuit changes the multiplication factor of this optical amplifier. It is good also as composition to do.

  In the present embodiment, the comparator 152 and the sample hold circuit 153 obtain the voltage of the ramp signal at the timing when the comparison result of the binary digital signal and the ramp signal changes. However, it is needless to say that a circuit other than the comparator 152 and the sample hold circuit 153 may be used as long as the voltage of the ramp signal at the timing can be detected.

  In the present embodiment, the optical signal receiving circuit 1 generates the ramp signal and compares the voltage with the binary voltage signal. However, the signal to be compared with the binary voltage signal is not limited to the ramp signal. Any signal may be used as long as it has the same period as the binary digital signal and is in an increasing / decreasing process while the voltage is increasing or decreasing at the transition timing of rising or falling of the binary digital signal. For example, instead of the ramp signal, a triangular or sine wave signal may be used as a comparison target.

  The APD 11, the preamplifier 12, and the limit amplifier 13 of this embodiment correspond to the light detection means of the present invention. The received voltage signal of this embodiment corresponds to the electrical signal of the present invention. The ramp signal of this embodiment is an example of the comparison signal of the present invention. The clock detection circuit 14 and the ramp waveform generation circuit 151 of the present embodiment correspond to the comparison signal generation means of the present invention. The comparator 152, sample hold circuit 153, arithmetic circuit 154, bias voltage control circuit 16, and bias voltage generation circuit 10 of this embodiment correspond to the control means of the present invention.

  As described above, according to the present embodiment, the optical signal reception circuit 1 generates a comparison signal having the same period as the reception voltage signal but having a different voltage at the transition timing, and the voltage of the reception voltage signal and the comparison signal The bias voltage is applied so that the amount of fluctuation of the voltage of the comparison signal, that is, the jitter amount is not less than the lower limit value and not more than the upper limit value at the time when the comparison result with this voltage changes. Since a lower limit is provided for the jitter amount, a bias voltage higher than necessary is not applied. Further, since the upper limit value is set for the jitter amount, the communication quality is maintained. As a result, the optical signal receiving circuit 1 can reduce power consumption while maintaining communication quality.

  Also, since the bias voltage is automatically adjusted according to the communication quality required for the actual optical communication line, it is not necessary to manually adjust the bias voltage.

1 Optical signal reception circuit 10 Bias voltage generation circuit 11 APD
12 Preamplifier 13 Limit amplifier 14 Clock detection circuit 15 Jitter detection circuit 16 Bias voltage control circuit 151 Ramp waveform generation circuit 152 Comparator 153 Sample hold circuit 154 Arithmetic circuit

Claims (8)

Photodetection means for converting the received optical signal into an electrical signal and outputting it with a reception sensitivity corresponding to the bias voltage applied by the control means;
A comparison signal for generating a signal having the same cycle as that of the electrical signal output by the light detection means and having a voltage increasing or decreasing process at the transition timing of the electrical signal as a comparison signal for comparison with the electrical signal. Signal generating means;
Fluctuation of the voltage of the comparison signal at the time when the result of comparing the voltage of the electrical signal output by the light detection means and the voltage of the comparison signal generated by the comparison signal generation means changes A control unit that calculates a quantity as a jitter amount of the electrical signal, and controls a bias voltage to the light detection unit so that the jitter amount is not less than an upper limit value and not more than a lower limit value;
An optical signal receiving circuit. A clock signal is superimposed on the electrical signal,
The comparison signal generating means includes
A clock signal extraction circuit for extracting the clock signal superimposed on the electrical signal output by the light detection means;
A comparison signal generation circuit that generates, as the comparison signal, a signal that has the same period as the clock signal extracted by the clock signal extraction circuit and whose voltage is increasing or decreasing at the transition timing of the clock signal;
The optical signal receiving circuit according to claim 1, comprising: The control means includes
A comparator that compares the voltage of the electrical signal output by the light detection means with the voltage of the comparison signal generated by the comparison signal generation means and outputs a comparator output signal indicating the result of the comparison; ,
A fluctuation amount of the voltage of the comparison signal at the time when the comparator output signal output by the comparator makes a transition is calculated as a jitter amount of the electrical signal, the jitter amount is equal to or greater than a lower limit value, and the jitter amount is A control circuit for applying a bias voltage to the light detection means so as to be equal to or lower than an upper limit value;
The optical signal receiving circuit according to claim 1, comprising: The control means includes
When the comparator output signal is output by the comparator, the comparator further includes a sample hold circuit that holds the comparison signal and outputs the comparison signal as a hold signal;
The optical signal receiving circuit according to claim 3, wherein the control circuit calculates a fluctuation amount of a voltage of the hold signal output by the sample and hold circuit. The variation amount decreases as the bias voltage increases, and the variation amount increases as the bias voltage increases.
The control means reduces the bias voltage by a predetermined value when the jitter amount is less than the lower limit value, and increases the bias voltage by a predetermined value when the jitter amount is larger than the upper limit value. 5. The optical signal receiving circuit according to any one of items 1 to 4.   The optical signal receiving circuit according to claim 1, wherein the comparison signal is a ramp signal.   The optical signal receiving circuit according to claim 1, wherein the light detection unit includes an APD. The light detection means converts the received optical signal into an electrical signal and outputs it with a reception sensitivity corresponding to the applied bias voltage,
A signal having the same period as that of the electric signal and having a voltage increasing / decreasing process at the transition timing of the electric signal is generated as a comparison signal for comparison with the electric signal,
The fluctuation amount of the voltage of the comparison signal at the time when the result of comparing the voltage of the electrical signal and the voltage of the comparison signal changes is calculated as the jitter amount of the electrical signal, and the jitter amount is an upper limit value. A method for controlling an optical signal receiving circuit, wherein the bias voltage to the photodetecting means is controlled so as to be above and below the lower limit value.