JP2011082252A - Three-dimensional semiconductor device and method for cooling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor device efficiently cooling a hot spot in a three-dimensional circuit by reducing or removing a limitation to a circuit design. <P>SOLUTION: The three-dimensional semiconductor device is formed by laminating a plurality of semiconductor chips 1 each having through-electrodes penetrating through chips. The three-dimensional semiconductor device includes first and second through-electrodes (4 and 5) composed of first and second materials of different kinds as the through-electrodes. The three-dimensional semiconductor device includes first and second surface wiring being electrically connected to the first and second through-electrodes respectively, consisting of the materials of the same kinds as the first and second through-electrodes respectively, being arranged on the circuit surfaces of the chips and being connected on the circuit surfaces. In the semiconductor device, a Peltier endothermic phenomenon is conducted on junctions (2) among the first surface wiring and the second surface wiring on the circuit surfaces by letting a current flow along the first through-electrodes, the first surface wiring, the second surface wiring, and the second through-electrodes. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a method and apparatus suitable for cooling a three-dimensional semiconductor device configured by stacking a plurality of semiconductor integrated circuits (semiconductor chips).

  There are many attempts to improve the degree of integration and high speed by stacking multiple LSI chips amidst the impediments to advanced functions and integration of semiconductor integrated circuits (LSIs) due to process miniaturization. It has been done.

  For example, Patent Document 1 (Japanese Patent Laid-Open No. 11-261001), Patent Document 2 (Japanese Patent Laid-Open No. 2001-189419), Patent Document 3 (Japanese Patent Laid-Open No. 2001-250913), etc. For electrical connection, a three-dimensional integrated circuit using a wiring that penetrates a semiconductor chip and is insulated from the semiconductor substrate itself, a so-called through-silicon via (TSV) is disclosed. . The through electrode (TSV) is formed by forming a through hole in a semiconductor substrate such as a silicon wafer, filling the through hole with a metal such as Cu, and connecting it to a wiring pattern on the chip circuit surface. The chip through electrode and the lower through electrode are connected by a bump so that they can be stacked vertically. In Patent Documents 1 to 3, how to provide a through electrode to a semiconductor chip, how to make a reliable electrical connection when stacking chips, and how to stack stacked chips Solutions have been proposed for how to fix them.

Japanese Patent Laid-Open No. 11-261001 JP 2001-189419 A JP 2001-250913 A Japanese Patent Laid-Open No. 03-214653 Japanese Patent Laid-Open No. 09-064255 JP 2008-244370 A JP 2005-259810 A JP 2006-108631 A

  The following is an analysis of the related art according to the present invention. One of the problems for putting a three-dimensional integrated circuit into practical use is a problem of heat generation from stacked semiconductor chips. In particular, in high-end LSIs where high-speed operation by multiple buses and short-distance connections is considered to be the greatest merit of three-dimensionalization, the establishment of an effective heat dissipation technique is an essential requirement for three-dimensional integrated circuit integration. Yes. At present, it is considered to secure required heat dissipation performance by arranging a large number of TSVs (heat dissipation vias) for heat dissipation. However, since there is no guarantee that such heat radiation vias can be disposed in the vicinity of the heat generation maximum point (hot spot) of the device, a complicated device design in which a heat radiation design is added to the circuit design must be performed. For this reason, the design freedom of the three-dimensional integrated circuit element is significantly reduced.

  Accordingly, it is an object of the present invention to provide an apparatus and method that can efficiently cool hot spots in a three-dimensional circuit without greatly restricting circuit design.

  In order to solve the above problems, the invention disclosed in the present application is generally configured as follows.

  According to the present invention, there is provided a three-dimensional semiconductor device in which a plurality of semiconductor chips each having a through electrode penetrating a chip are stacked, wherein the semiconductor chip is used as the first through second electrodes as the through electrodes. First and second through electrodes each made of the same material, and electrically connected to the first and second through electrodes, respectively, and the same or the same kind as the first and second through electrodes, respectively. Made of a material, disposed on the circuit surface of the semiconductor chip, and having first and second surface wirings connected on the circuit surface, the first surface wiring from the first through electrode side; Peltier heat absorption is performed at the junction between the first surface wiring and the second surface wiring on the circuit surface by passing a current along the second through electrode through the second surface wiring. A three-dimensional semiconductor device is provided.

According to the present invention, there is provided a cooling method for a three-dimensional semiconductor device in which a plurality of semiconductor chips having through electrodes penetrating a chip are stacked,
As the through electrode, there are provided first and second through electrodes made of different first and second materials,
The first and second through electrodes are electrically connected to each other, are made of the same or the same material as the first and second through electrodes, and are disposed on the circuit surface of the semiconductor chip. 2 surface wirings are connected on the circuit surface,
The first surface wiring on the circuit surface is caused to flow along the second through electrode from the first through electrode side through the first surface wiring and the second surface wiring. And a method for cooling a three-dimensional semiconductor device, in which Peltier heat absorption is performed at the junction of the second surface wiring.

  According to the present invention, hot spots in a three-dimensional circuit can be efficiently cooled without greatly restricting circuit design.

It is a figure which shows the structure of one Embodiment of this invention. It is a figure which shows the chip | tip cooling effect of one Embodiment of this invention.

  An embodiment of the present invention will be described. The present invention provides a three-dimensional semiconductor device in which a plurality of semiconductor chips each having a through electrode penetrating a chip are stacked, and a set of a through electrode and a surface wiring on a chip circuit surface directly connected to the through electrode, A hot spot in a semiconductor chip can be directly cooled by Peltier heat absorption that occurs when two types of materials with large differences in thermoelectric power (Seebeck coefficient) are applied and current flows through the junction of the two types of surface wiring. It was created by finding Peltier heat absorption occurs only at the junction of dissimilar materials. For this reason, if this junction is arranged immediately above the hot spot in the semiconductor chip, the position of the TSV itself connected to the junction can be arranged away from the junction. As a result, it is possible to cool an arbitrary position in the surface of the semiconductor chip without greatly restricting the circuit design.

  Here, the difference between the present invention described above and the related art will be described. Attempts to use the Peltier effect or the Peltier element for cooling the semiconductor element are disclosed in, for example, Japanese Patent Application Laid-Open No. 03-214653, Japanese Patent Application Laid-Open No. 09-064255, and the like. However, the configurations described in Patent Documents 4 and 5 and the like cannot be applied to a three-dimensional LSI in which a plurality of semiconductor chips are stacked because a Peltier element is provided on the back surface of a semiconductor element substrate. In addition, unlike the present invention, it is not possible to cool by aiming at a hot spot in the chip.

  Further, Patent Document 6 (Japanese Patent Laid-Open No. 2008-244370) and Patent Document 7 (Japanese Patent Laid-Open No. 2005-259810) disclose a technique of using a semiconductor element substrate itself as a Peltier element. Since the thermoelectric performance of Si is low, the heat dissipation capability cannot be so high.

  Further, Patent Document 8 (Japanese Patent Laid-Open No. 2006-108631) discloses a configuration in which device cooling is performed by forming a CPP (Current Perpendicular to Plain) wiring portion having a columnar structure with a thermoelectric material having a heterogeneous material interface. However, due to the structure in which the junction (dissimilar material interface) where Peltier heat absorption occurs is provided inside the CPP wiring, it is not possible to cool any position in the device. Hereinafter, embodiments of the present invention will be specifically described.

  FIG. 1 is a diagram for explaining an embodiment of the present invention. A through-electrode (TSV) penetrating the semiconductor chip 1 is connected between the upper and lower chips, and a three-dimensional semiconductor device is configured in which a plurality of semiconductor chips 1 are laminated together. The through electrodes (TSV) 4 and 5 are made of p-type and n-type thermoelectric materials, respectively. The amount of heat absorbed at the junction of different types of thermoelectric materials is proportional to the difference between the Seebeck coefficients of the two types of thermoelectric materials to be joined, so that the n-type (negative Seebeck coefficient) thermoelectric material and the p-type ( It is effective to combine with a thermoelectric material having a positive Seebeck coefficient. When current flows from the n-type thermoelectric material to the p-type thermoelectric material, heat is absorbed at the junction 2, so the junction 2 is placed at a desired position on the stacked chip surface (circuit surface). By disposing, heat generated locally within the laminate can be absorbed.

  Unlike the case where through electrodes (TSV) 4 and 5 made of p-type and n-type thermoelectric materials are connected by wiring such as copper on the circuit surface of the chip to form a Peltier element having a π-type structure, this embodiment According to the present invention, it is possible to provide surface wiring made of p-type and n-type thermoelectric materials electrically connected to the through-electrodes (TSV) 4 and 5, respectively, and connect them on the circuit surface of the chip. Even if the through-electrodes (TSV) 4 and 5 are arranged at a considerable distance, Peltier heat absorption is performed locally at the joint 2 on the chip circuit surface, and locally inside the laminate. The generated heat can be absorbed. When the through electrodes (TSV) 4 and 5 are connected to each other by wiring such as copper on the circuit surface of the chip to form a π-type structure, the heat absorption is spread over the entire wiring such as copper and the interval between the through electrodes (TSV) 4 and 5. In the case of spreading, heat cannot be absorbed locally.

  In addition, as shown in FIG. 1, a combination of an n-type thermoelectric material constituting the through electrode (TSV) 5, a junction portion 2, and a p-type thermoelectric material constituting the through electrode (TSV) 4 may be connected in series. Is possible. In this case, the current flows from the p-type thermoelectric material to the n-type thermoelectric material at the junction 3 on the back surface of the chip, so that Peltier heat generation occurs. However, since this heat generation is heat generation in the outermost layer of the stacked chips, heat dissipation is easier than heat generation in the stacked body.

  In the present embodiment, it is made of p-type and n-type thermoelectric materials electrically connected to the through-electrodes (TSV) 4 and 5 on the chip back surface of the lowermost semiconductor chip 1 of the plurality of stacked semiconductor chips 1. Although front surface wiring is provided and these are connected on the back surface of the chip, through electrodes (TSV) 4 and 5 on the back surface side of the chip may be connected by wiring such as copper to form a Peltier element having a π-type structure.

  In FIG. 1, the n-type thermoelectric material through electrode (TSV) 4, the junction 2, the p-type thermoelectric material through electrode (TSV) 5, and the junction 3 of the plurality of semiconductor chips 1 constituting the three-dimensional semiconductor device. , N-type thermoelectric material penetrating electrodes (TSV) 4..., All penetrating electrodes and junctions are connected in series (connected together), and current is supplied from the penetrating electrodes (TSV) 4 on the back side of the chip. Is shown, but a part of the n-type thermoelectric material penetration electrode (TSV) 4, the junction 2, and the p-type thermoelectric material penetration electrode (TSV) 5 of the plurality of semiconductor chips 1 constituting the three-dimensional semiconductor device. A series circuit may be configured with one set, and another series circuit may be configured with another set.

  As an index indicating the performance of the thermoelectric material, a thermoelectric performance index Z is generally used. Z is represented by the following formula (1).

・・・（１）

... (1)

  Where S is the Seebeck coefficient (V / K), σ is the conductivity (1 / Ω / m), and κ is the thermal conductivity (W / mK) (in the dimensions in parentheses, V is voltage, K is Kelvin) (Temperature), Ω is resistance, m is meter, and W is Watt).

  When the thermoelectric material is used in a thermoelectric conversion system that extracts power from a temperature difference or in a thermoelectric cooling system that transports heat from a low temperature part to a high temperature part, the figure of merit Z and the operating temperature T (absolute temperature) The product, the dimensionless quantity ZT, determines the efficiency of the system. For this reason, the use of a material having a high ZT is the key to constructing a highly efficient system.

  In the case of a thermoelectric conversion system, heat is extracted from a high temperature part, a part of the energy is converted into electricity, and the rest is discarded to a low temperature part. The ratio η between the amount of heat Q extracted from the high temperature unit per unit time and the electric power P extracted is given by the following equation (2).

・・・（２）

... (2)

However, the _{T H} the temperature of the high temperature portion, the _{T C} temperature of the low temperature portion, [Delta] T is the temperature difference _T H -T _C of low temperature part and the high-temperature portion.

  It can also be seen from equation (2) that the system efficiency η depends on the material properties of the thermoelectric material only through the factor ZT.

  On the other hand, in the case of a normal thermoelectric cooling system, electric power is input from the outside, heat is extracted from the low temperature portion, and heat is released at the high temperature portion.

  Here, the ratio φ between the amount of heat Q taken out from the low temperature unit per unit time and the electric power P to be input is given by the following equation (3).

・・・（３）

... (3)

  Again, the efficiency φ depends on the material properties of the thermoelectric material only through ZT.

  From Equations (2) and (3), in either case of thermoelectric conversion or thermoelectric cooling, the efficiency is equal to the efficiency of the Carnot engine at the limit where the ZT is infinite.

  On the other hand, in the case of the present invention, desirable properties for thermoelectric materials are different from those that are best for conventional thermoelectric materials for thermoelectric conversion and thermoelectric cooling systems.

Specifically, the output factor (S ² σ) corresponding to the numerator of Z in the formula (2) is preferably as large as possible in both normal and related art applications and the present invention.

  As for the thermal conductivity of the denominator of Z in the formula (2), it is desired to be as small as possible in normal or related art applications, whereas in the application of the present invention, the larger one is desirable. . That is, ZT is not always a good performance index for the application of the present invention.

Table 1 shows output factors S ² σ, thermal conductivity κ, ZT, and operating temperature of typical thermoelectric materials. The dimension of the output factor (S ² σ) is W / K ² m.

As a thermoelectric material used near room temperature, only Bi ₂ Te ₃ having a ZT exceeding 1 has been put into practical use. For the use of the present invention, a Whistler alloy (Fe _1-x X _x ) ₂ (V _{1 -y Y y) (Al 1-} z Z z)
(X = Co, Pt, Y = Ti, Zr, Mo, W, Z = Si, Ge, 0 ≦ x ≦ 0.1, 0 ≦ y ≦ 0.2, 0 ≦ z ≦ 0.1) are also suitable. ing.

While the Whistler alloy has an output factor equivalent to that of Bi ₂ Te ₃ , the thermal conductivity κ is about 10 times higher than Bi ₂ Te ₃ (the thermal conductivity of the Whistler alloy is 10 to 15 W / mK). Due to the high thermal conductivity, the value of ZT of the Whistler alloy was as small as 0.2, and the practicality was low.

From this point, a preferable physical property for the thermoelectric material used in the present invention is not that ZT is large, but that both output factor S ² σ and thermal conductivity κ are large. Any material having this property can be used as a TSV material (filling material for a through silicon via TSV) in the present invention, in addition to a Whistler alloy.

In the present invention, as a set of different materials constituting the TSV, it is preferable to use a material having a large Seebeck coefficient and an opposite sign, such as a commonly used n-type and p-type Bi ₂ Te _3. It is not limited only to the conditions.

  One of the different materials can be made of copper (Cu) having a small Seebeck coefficient and the other can be made of an n-type Heusler alloy. In other combinations, if the difference in Seebeck coefficient of different materials is 50 μV / K or more, preferably 100 μV / K or more, the electrode material constituting the present invention (through electrode and surface wiring connected thereto) Can be used as

FIG. 2 is a diagram showing the cooling effect of one embodiment of the present invention. FIG. 2 shows a temperature measurement result in a test device in which a silicon chip in which a heating element and a temperature measuring element are formed is laminated on the chip surface. In FIG. 2, the horizontal axis represents the cooling current (mA), and the vertical axis represents the heat generation temperature (° C.). The cooling TSV and surface wiring pattern of the device are made of a set of Heusler alloy Fe ₂ (V _0.9 Mo _0.1 ) Al and copper so that the current at the cooling point is from Heusler alloy to copper. I made it.

  When power was supplied to the heating element and no current was supplied to the cooling TSV (cooling current = 0), the temperature around the heating point rose to 190 ° C. or higher and became a steady state. In this state, when a current was passed through the cooling TSV, the temperature around the heating point decreased as the current increased, and the temperature at the heating point could be reduced to 80 ° C. or less with a cooling current of about 50 mA.

  As described in the above embodiments, according to the present invention, a hot spot in a semiconductor integrated circuit can be locally and efficiently cooled, and a three-dimensional semiconductor integrated circuit of a high-spec LSI with high power consumption. Can be easily performed.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 Substrate (chip)
2 Junction (heat absorption part)
3 Junction (heat dissipation part)
4 Through electrode (TSV: n-type thermoelectric material)
5 Through electrode (TSV: p-type thermoelectric material)

Claims (16)

A three-dimensional semiconductor device formed by laminating a plurality of semiconductor chips each having a through electrode penetrating the chip,
The semiconductor chip includes first and second through electrodes made of different first and second materials as the through electrodes,
The circuit surface is electrically connected to the first and second through electrodes, is made of the same or the same material as the first and second through electrodes, and is disposed on the circuit surface of the semiconductor chip. Having first and second surface wirings connected above,
The first surface wiring on the circuit surface is caused to flow along the second through electrode from the first through electrode side through the first surface wiring and the second surface wiring. And a Peltier heat absorption at the junction of the second surface wiring.   The junction between the first surface wiring and the second surface wiring is disposed at a position corresponding to the hot spot in the semiconductor chip on the circuit surface of the semiconductor chip, and the first surface wiring and the 2. The three-dimensional semiconductor according to claim 1, wherein the first and second through electrodes connected to the joint portion of the second surface wiring can be disposed at a position separated from the joint portion. apparatus.   3. The three-dimensional semiconductor device according to claim 1, wherein an absolute value of a difference between Seebeck coefficients of the first and second materials is 50 μV / K or more.   4. The three-dimensional semiconductor device according to claim 3, wherein the thermal conductivity of at least one of the first and second materials is 10 W / mK or more. At least one of the first and second materials is a Whistler alloy,
_{(Fe 1-x X x)} 2 (V 1-y Y y) (Al 1-z Z z)
(X = Co, Pt, Y = Ti, Zr, Mo, W, Z = Si, Ge, 0 ≦ x ≦ 0.1, 0 ≦ y ≦ 0.2, 0 ≦ z ≦ 0.1) The three-dimensional semiconductor device according to claim 4.   A series formed by connecting a plurality of sets of the first through electrode, the first surface wiring, the second surface wiring, and the second through electrode in series across the plurality of semiconductor chips. The three-dimensional semiconductor device according to claim 1, further comprising a circuit, wherein current is supplied from one end of the series circuit.   The first through electrode and the second through electrode are connected by wiring on the chip back surface opposite to the circuit surface of the lowermost semiconductor chip among the plurality of stacked semiconductor chips. The three-dimensional semiconductor device according to claim 5.   The wiring is electrically connected to each of the first and second through electrodes, and is made of the same or the same material as each of the first and second through electrodes, and is disposed on the back surface of the chip. 8. The three-dimensional semiconductor device according to claim 7, wherein the three-dimensional semiconductor device has third and fourth surface wirings connected to each other, and Peltier heat generation is performed at a joint portion between the third and fourth surface wirings. . A cooling method for a three-dimensional semiconductor device, in which a plurality of semiconductor chips each having a through electrode penetrating the chip are stacked,
As the through electrode, there are provided first and second through electrodes made of different first and second materials,
The first and second through electrodes are electrically connected to each other, are made of the same or the same material as the first and second through electrodes, and are disposed on the circuit surface of the semiconductor chip. 2 surface wirings are connected on the circuit surface,
The first surface wiring on the circuit surface is caused to flow along the second through electrode from the first through electrode side through the first surface wiring and the second surface wiring. And a method of cooling a three-dimensional semiconductor device, wherein Peltier heat absorption is performed at a junction between the second surface wiring and the second surface wiring.   The junction between the first surface wiring and the second surface wiring is disposed at a position corresponding to the hot spot in the semiconductor chip on the circuit surface of the semiconductor chip, and the first surface wiring and the The three-dimensional semiconductor according to claim 9, wherein the first and second through electrodes connected to the joint portion of the second surface wiring can be arranged at a position spaced apart from the joint portion. How to cool the device.   The method for cooling a three-dimensional semiconductor device according to claim 9 or 10, wherein an absolute value of a difference between Seebeck coefficients of the first and second materials is 50 µV / K or more.   12. The method of cooling a three-dimensional semiconductor device according to claim 11, wherein the thermal conductivity of at least one of the first and second materials is 10 W / mK or more. The thermal conductivity of at least one of the first and second materials is a Whistler alloy,
_{(Fe 1-x X x)} 2 (V 1-y Y y) (Al 1-z Z z)
(X = Co, Pt, Y = Ti, Zr, Mo, W, Z = Si, Ge, 0 ≦ x ≦ 0.1, 0 ≦ y ≦ 0.2, 0 ≦ z ≦ 0.1) The method for cooling a three-dimensional semiconductor device according to claim 12.   A series circuit in which a plurality of sets of the first through electrode, the first surface wiring, the second surface wiring, and the second through electrode are connected in series across the plurality of semiconductor chips. The method for cooling a three-dimensional semiconductor device according to claim 9, wherein a current is supplied from one end of the series circuit.   The first through electrode and the second through electrode are connected by wiring on the chip back surface opposite to the circuit surface of the lowermost semiconductor chip among the plurality of stacked semiconductor chips. The method for cooling a three-dimensional semiconductor device according to claim 14.   The wiring is electrically connected to each of the first and second through electrodes, and is made of the same or the same material as each of the first and second through electrodes, and is disposed on the back surface of the chip. 16. The three-dimensional semiconductor device according to claim 15, wherein the Peltier heat is generated at a junction between the third and fourth surface wirings. Cooling method.

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