WO2011162726A1

WO2011162726A1 - Thermoelectric device and method for manufacturing a thermoelectric device

Info

Publication number: WO2011162726A1
Application number: PCT/SG2011/000223
Authority: WO
Inventors: Kavitha Buddharaju; Yida Li; Navab Singh; Guo Qiang Patrick Lo
Original assignee: Agency For Science, Technology And Research
Priority date: 2010-06-25
Filing date: 2011-06-23
Publication date: 2011-12-29

Abstract

According to embodiments of the present invention, a thermoelectric device is provided. The thermoelectric device may include a plurality of cells, where each cell includes a first electrode including a first electrode portion and a second electrode portion; a first nanowire, wherein a first end of the first nanowire is coupled to the first electrode portion of the first electrode, the first nanowire being doped with doping atoms of a first conductivity type; and a second nanowire, wherein a first end of the second nanowire is coupled to the second electrode portion of the first electrode, the second nanowire being doped with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type; and wherein a second end of the first nanowire is coupled to a second electrode, the second electrode coupled to an adjacent cell; wherein a second end of the second nanowire is coupled to a further second electrode, the further second electrode coupled to a further adjacent cell; and wherein at least one of the first electrode and a portion at the second end of the first nanowire and the second end of the second nanowire are silicided.

Description

THERMOELECTRIC DEVICE AND METHOD FOR MANUFACTURING A

THERMOELECTRIC DEVICE

Cross-Reference To Related Application

[0001] This application claims the benefit of priority of Singapore patent application No. 201004577-1, filed 25 June 2010, the content of it being hereby incorporated by reference in its entirety for all purposes.

Technical Field

[0002] Various embodiments relate to a thermoelectric device and a method for manufacturing the thermoelectric device.

Background

[0003] Typical integrated circuits (IC chips) have millions of transistors. These transistors carry different electrical loads. This variable electrical activity in different areas can lead to specific heated areas on the chips known as hot spots. These hot spots, which range from some nanometers to several thousand micrometers, can cause major thermal imbalance on the chip, resulting in some areas on the chip to be 10-40°C hotter than the rest of the chip. The sizes of these hot spots had been observed to be proportional to the thickness of the silicon substrate being used. Therefore, as technology advances and 3D chips and stacked chips gain prominence, these hot spots can cause serious interference to the performance of the ICs if the chips are not sufficiently cooled. In addition, there may also be uneven heat flux on the chip.

[0004] Some of the conventional techniques used for cooling the chips employ thermoelectric cooling to remove the waste heat. Thermoelectric cooling principle stems from the Peltier effect where all electric current is accompanied by a heat current and vice versa.. Depending on the direction of current, a device for thermoelectric cooling can alternate between being a heater and a cooler. This effect is harnessed in conventional thermoelectric coolers. The efficiency of cooling is a material property and is characterized by a dimensionless figure-of-merit, ZT, termed as ZT = S²Ta/k, where S, a, k and T, are the Seeback coefficient, electrical conductivity, thermal conductivity and absolute temperature, respectively. Based on the above, a good requirement for a thermoelectric material would be a high electrical conductivity coupled with a low thermal conductivity.

[0005] The cooling mechanisms, as provided in conventional thermoelectric coolers, function more as global coolers or heat sinks, and do not provide on-demand localized cooling of high heat flux regions. This results in over designed, inefficient, bulky (for example in mm² to cm² dimensions) and expensive thermal systems. In addition, there may be integration issues with conventional coolers for silicon-based electronics.

[0006] Thermoelectric materials in ID are promising due to the enhancement of thermopower. However, it has been a challenging task to scale down thermoelectric materials to be used at the micro level, particularly on microchip, as well as integration issues.

[0007] In addition, there is a lack of CMOS-compatible ZT materials. Nanostructure alloys of bismuth (Bi), antimony (Sb), and tellurium (Te), for example, are good candidate materials for thermoelectric as they exhibit ZT~1. However, they pose serious integration problems where it is difficult to scale and integrate them with standard CMOS processes which are required for on-chip coolers.

[0008] There have been many planar super lattice structures which have been demonstrated with high efficiency but none have been reported so far on 3D super lattice based thermoelectric coolers, which would be one more step ahead. In addition, while bottom-up materials are excellent from a fundamental lattice study point of view, they pose serious issues when a working and commercial prototype needs to be developed. Furthermore, it is difficult to integrate them with the regular CMOS/conventional circuitry, thereby nullifying the advantage that the material provides.

[0009] Therefore, there are issues related to the lack of efficient thermoelectric materials, integration scheme and efficient spot cooling. Summary

[0010] According to an embodiment, a thermoelectric device is provided. The thermoelectric device may include a plurality of cells, where each cell includes a first electrode including a first electrode portion and a second electrode portion; a first nanowire, wherein a first end of the first nanowire is coupled to the first electrode portion of the first electrode, the first nanowire being doped with doping atoms of a first conductivity type; and a second nanowire, wherein a first end of the second nanowire is coupled to the second electrode portion of the first electrode, the second nanowire being doped with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type; and wherein a second end of the first nanowire is coupled to a second electrode, the second electrode coupled to an adjacent cell; wherein a second end of the second nanowire is coupled to a further second electrode, the further second electrode coupled to a further adjacent cell; and wherein at least one of the first electrode and a portion at the second end of the first nanowire and the second end of the second nanowire are silicided.

[0011] According to an embodiment, a method for manufacturing a thermoelectric device including a plurality of cells is provided. The method may include forming a plurality of nanowires, wherein a first end of the nanowires is coupled to a substrate; doping a first nanowire of the plurality of nanowires, with doping atoms of a first conductivity type; doping a second nanowire of the plurality of nanowires, with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type; forming a cell including the first nanowire and the second nanowire; forming a second electrode such that the second electrode is coupled to a second end of the first nanowire and an adjacent cell, forming a further second electrode such that the further second electrode is coupled to a second end of the second nanowire and a further adjacent cell; and siliciding at least one of a portion at the second end of the first nanowire and the second end of the second nanowire, and a portion of the substrate to form a first electrode comprising a first electrode portion and a second electrode portion, wherein the first electrode portion is coupled to the first end of the first nanowire and wherein the second electrode portion is coupled to the first end of the second nanowire. Brief Description of the Drawings

[0012] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0013] FIG. 1A shows a schematic block diagram of a thermoelectric device, according to various embodiments.

[0014] FIG. IB shows a flow chart illustrating a method for manufacturing a thermoelectric device, according to various embodiments.

[0015] FIG. 2A shows a schematic cross-sectional view of a thermoelectric device, according to various embodiments.

[0016] FIG. 2B shows a schematic view of a thermoelectric equivalent of adjacent cells of the thermoelectric device of the embodiment of FIG. 2 A.

[0017] FIGS. 3A and 3B show a schematic cross-sectional view and a schematic perspective view respectively of a fabrication process for manufacturing a thermoelectric device, according to various embodiments.

[0018] FIG. 4A shows SEM images of silicon nanowires, according to various embodiments. The scale bars for the left and centre images represent 400 nm while the scale bar for the right image represents 200 nm.

[0019] FIG. 4B shows an SEM image of silicon-germanium heterojunction nanowires, according to various embodiments. The scale bar represents 400 nm.

[0020] FIG. 4C shows an SEM image of a nanowire array after formation of silicon islands, according to various embodiments. The scale bar represents 5 μπι.

[0021] FIG. 4D shows an SEM image of tips of a nanowire array exposed after contact oxide etch, according to various embodiments. The scale bar represents 200 nm.

[0022] FIG. 4E shows an SEM image of photoresist patterns for forming the top electrodes, according to various embodiments. The scale bar represents 5 μπι. [0023] FIG. 4F shows a schematic representation and a microscope image of a nanowire array after lithography patterning, ion implantation and formation of n-doped and p- doped nanowires, according to various embodiments. The scale bar for the bottom image represents 500 μπι.

[0024] FIG. 5 shows a schematic of a measurement set-up, according to various embodiments.

[0025] FIG. 6A shows a plot of current-voltage (I-V) characteristics of a thermoelectric device, according to various embodiments.

[0026] FIG. 6B shows a plot of resistance of a thermoelectric device, according to various embodiments.

[0027] FIG. 7 shows a thermal stack, according to various embodiments.

[0028] FIG. 8 shows a plot of current-voltage (I-V) characteristics of a thermoelectric device at different temperature gradients, according to various embodiments.

[0029] FIG. 9A shows a plot of open circuit voltage generated for different dT applied across the thermoelectric device, according to various embodiments.

[0030] FIG. 9B shows a plot of the extrapolated open circuit voltage for dT up to 2 K of the plot of FIG. 9A.

[0031] FIG. 10A shows a plot of power generated for different dT applied across the thermoelectric device at different currents, according to various embodiments.

[0032] FIG. 10B shows a plot of voltage and power generated at dT of 36.7 mK across the thermoelectric device at different currents, according to various embodiments.

[0033] FIG. 11 shows a plot of temperature against current for a thermoelectric device, according to various embodiments.

[0034] FIG. 12A shows a plot of simulated cooling performance with varying heat load, according to various embodiments.

[0035] FIG. 12B shows a plot of simulated cooling performance for different heat load power density, according to various embodiments.

[0036] FIG. 12C shows a plot of simulated cooling temperature with different thermal conductivities, according to various embodiments.

[0037] FIG. 12D shows simulated results for different dimensions of silicon nanowires, according to various embodiments. [0038] FIG. 13 shows a schematic of an integrated chip-level thermal management module, according to various embodiments.

Detailed Description

[0039] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0040] Various embodiments may provide technologies and systems that may provide cooling over all power levels. Various embodiments may be CMOS compatible and may be implemented with different thermoelectric materials.

[0041] Various embodiments may provide thermoelectric modules and devices that may provide site specific targeted cooling of hot spots (for example for spots with dimensions less than 100 x 100 μπι²), thereby reducing the energy or power consumption. These thermoelectric devices (e.g. thermoelectric coolers) may be integrated and may be used in various high flux applications, including the area of optoelectronics. Various embodiments may provide an integration scheme that provides monolithic integration with all silicon based electronics.

[0042] Various embodiments may provide thermoelectric devices, for example for thermoelectric cooling (e.g. thermoelectric cooler) and power generation (e.g. thermoelectric generator), by incorporating silicon-based nanostructures, for example silicon (Si) and silicon germanium (SiGe) nanostructures (e.g. nanowires). In various embodiments, highly efficient thermoelectric materials (e.g. with ZT of about 2- 5, e.g. about 2.5 to about 4.3) compared to conventional materials may be achieved by employing nanostructures. In addition, various embodiments provide a cooling power density approximately 2 orders larger than conventional thermoelectric device. Furthermore, the use of silicon-based nanostructures may enable monolithic integration with silicon based electronics and are compatible with standard complementary metal oxide semiconductor (CMOS) processes, while maintaining the required performance.

[0043] Quantum phenomenon and enhanced surface to volume ratios that is observed in nanoscale structures impart new properties or allow materials to deviate from their traditional formats. For example, there is a reduction in thermal conductivity (e.g. the thermal conductivity, k, is reduced by ~ lOOx, due to phonon scattering), with minimal change in electrical conductivity, which is achieved in nanoscale silicon compared to bulk silicon, thereby allowing a range of various applications. Therefore, in various embodiments, by exploiting the interfaces and boundaries of these low dimensional structures (e.g. nanowires and nanotubes), the values of ZT may be improved.

[0044] The thermal conductivity of a silicon (Si) nanowire is reduced by about 2 orders, resulting in an improvement in the ZT value (figure of merit) to about 1, from the bulk material of about 0.014. For example, a vapor-liquid-solid (VLS) Si nanowire of length of about 1 μπι and diameter of about 50 nm has a thermal conductivity value of about 25 W/mK, while the electrical conductivity and Seebeck coefficient remain substantially the same as bulk silicon. Based on analysis using thermoelectric equations, a single Si nanowire has the capability to remove about 0.4 μ\¥ heat load and generate about 2.205xl0^"12 W of power under a temperature gradient of IK. When an array of nanowires is used, the array of nanowires has a potential heat pumping capability of about 40 W for approximately 5 mm x 5 mm area, with a nanowire density of about 4 nanowires/μηι², assuming negligible power loss due to contact resistance.

[0045] Accordingly, various embodiments may provide thermoelectric devices and methods of fabricating thermoelectric devices using CMOS compatible processes, where the thermoelectric devices include an array of silicon-based nanowires. For example, various embodiments provide a silicon nanowire-based top down integrated thermoelectric device or generator. The silicon nanowire-based thermoelectric device is scalable, space efficient (i.e. requires small space) and appropriate for chip-level cooling and power generation, as it may be integrated into or with ICs. Various embodiments may provide nanoscale thermoelectric material with increased phonon scattering for enhanced performance. [0046] Various embodiments may provide a CMOS compatible top down Si-based (e.g. Si and SiGe) nanowire-based thermoelectric device, thermoelectric cooling modules and chip-level coolers that are low cost, scalable and of a small size. Various embodiments may also provide a CMOS compatible top down nanofabrication technology to fabricate the thermoelectric devices and coolers, including a top down CMOS integration scheme to provide thermoelectric devices incorporating Si and SiGe nanowires, for thermoelectric applications. The integration scheme may be used for a wide array of nanostructures (e.g. smooth or non-textured nanowires, rough or textured nanowires, silicon-based nanowires, heterojunction SiGe nanowires of different periodicity, nanotubes and nanospirals) for different applications. Various embodiments may provide an integration flow that is simple and low cost, with minimal parasitic. In addition, various embodiments may provide low-cost chip-level or computer thermoelectric-based thermal management systems, energy efficient refrigeration, site specific cooling including hot-spot cooling for micro processors.

[0047] In various embodiments, the nanowires may be textured or non-textured. In other words, the surface or sidewall of each of the nanowires may be textured (e.g. rough surface) or non-textured (e.g. smooth surface). In various embodiments, phonon back scattering increases with texturing, thereby reducing thermal conductivity further over non-textured silicon nanowires.

[0048] In various embodiments, each of the nanowires may include silicon nanowire, polysilicon nanowire (i.e. polycrystalline silicon nanowire), silicon-germanium nanowire and silicon-germanium heterojunction nanowire. However, it should be appreciated that any silicon-based nanowires may be provided.

[0049] In various embodiments, the Si-based (e.g. Si and SiGe) nanowire-based thermoelectric device may include a filling material between the nanowires and between the metal electrodes, for example an inter-metal dielectric such as parylene, polyimide or any electrical insulator, for example a silicon-based dielectric material. In further embodiments, the thermoelectric device may not include an inter-metal dielectric but air gaps or air pockets, which may reduce the thermal conductivity further over other inter- metal dielectrics. [0050] Various embodiments may also provide an integration scheme using metal- silicidation (e.g. nickel silicide) as a bottom metallic electrode to reduce the contact resistance.

[0051] Various embodiments may provide thermoelectric devices with an area of approximately 10 mm x 10 mm or less (e.g. 500 μπι x 500 um), with a form factor that is not limited and which may provide site-specific cooling of hot spots, that are compatible with CMOS and very-large-scale integration (VLSI) technologies, that exhibit ZT > 1, that exhibit cooling temperature of between about 20°C to about 50°C, and provide cooling for a heat flux of about 200 W/cm² or in a range of between about 1 W/cm² to about 200 W/cm². However, it should be appreciated that these parameters are not limited to the values indicated and therefore other values may be provided in various embodiments.

[0052] In the context of various embodiments, the term "top down" may mean an approach where an overview of a system is first formulated and one or more subsystems are specified. Each subsystem is then defined in further details, for example its specification, which may include further subsystems. This approach enables the entire specification of the system to be reduced to base elements. Such an approach is in contrast to a "bottom up" approach, which specifies the individual base elements in details, which are then linked together to form one or more subsystems, which in turn are linked to form a system.

[0053] In order that the invention may be readily understood and put into practical effect, particular embodiments will now be described by way of examples and not limitations, and with reference to the figures.

[0054] FIG. 1A shows a schematic block diagram of a thermoelectric device 100, according to various embodiments. The thermoelectric device 100 includes a plurality of cells where each cell 101 includes a first electrode 102 including a first electrode portion 114 and a second electrode portion 116, a first nanowire 104, wherein a first end of the first nanowire 104 is coupled to the first electrode portion 114 of the first electrode 102, the first nanowire 104 being doped with doping atoms of a first conductivity type 106, and a second nanowire 108, wherein a first end of the second nanowire 108 is coupled to the second electrode portion 116 of the first electrode 102, the second nanowire 108 being doped with doping atoms of a second conductivity type 110, the second conductivity type is different from the first conductivity type, and wherein a second end of the first nanowire 104 is coupled to a second electrode 112, the second electrode 112 coupled to an adjacent cell, wherein a second end of the second nanowire 108 is coupled to a further second electrode 118, the further second electrode 118 coupled to a further adjacent cell, and wherein at least one of the first electrode 102 and a portion at the second end of the first nanowire 104 and the second end of the second nanowire 108 are silicided.

[0055] In various embodiments, the first electrode 102 and/or a portion at the second end of the first nanowire 104 and the second nanowire 108 are silicided.

[0056] In various embodiments, the first end of the first nanowire 104 is coupled to the first electrode portion 114 of the first electrode 102 and the first end of the second nanowire 108 is coupled to the second electrode portion 116 of the first electrode 102. The second end of the first nanowire 104 and the second end of the second nanowire 108 are coupled to different (separate) second electrodes, for example the second end of the first nanowire 104 is coupled to the second electrode 112 while the second end of the second nanowire 108 is coupled to the further second electrode 118. In various embodiments, the second electrode 112 may be further coupled to an adjacent cell, for example to a second end of a second nanowire of the adjacent cell, while the further second electrode 118 may be further coupled to a further adjacent cell, for example to a second end of a first nanowire of the further adjacent cell.

[0057] In other words, a second electrode may be provided such that the second electrode is coupled to a second end of a first nanowire of a cell and a second end of a second nanowire of an adjacent cell, and a further second electrode may be provided such that the further electrode is coupled to a second end of a second nanowire of the cell and a second end of a first nanowire of a further adjacent cell.

[0058] In various embodiments, each of the first nanowire 104 and the second nanowire 108 comprises silicon (Si). For example, each of the first nanowire 104 and the second nanowire 108 may be a silicon-based nanowire such as a silicon nanowire (e.g. a polycrystalline silicon nanowire), a silicon-germanium nanowire, a silicon-germanium heterojunction nanowire (e.g. Si-SiGe nanowire) and a silicon-germanium epitaxy nanowire.

[0059] In various embodiments, the thermoelectric device 100 may further include insulating spacers surrounding the first nanowire 104 and the second nanowire 108.

[0060] In various embodiments, the thermoelectric device 100 may further include electrically insulating filling material disposed between the first nanowire 104 and the second nanowire 108. This may include the electrically insulating filling material being disposed between the first electrode 102, the second electrode 112 and the further second electrode 118, e.g. in the space between the first electrode 102, the second electrode 112 and the further second electrode 118 and between the first nanowire 104 and the second nanowire 108. In addition, the electrically insulating filling material may be disposed in the spaces between various nanowires and electrodes in the plurality of cells of the thermoelectric device 100.

[0061] In various embodiments, the plurality of cells are connected in series electrically and in parallel thermally.

[0062] FIG. IB shows a flow chart 140 illustrating a method for manufacturing a thermoelectric device, according to various embodiments. The thermoelectric device includes a plurality of cells.

[0063] At 142, a plurality of nanowires is formed, wherein a first end of the nanowires is coupled to a substrate.

[0064] At 144, a first nanowire of the plurality of nanowires is doped with doping atoms of a first conductivity type.

[0065] At 146, a second nanowire of the plurality of nanowires is doped with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type.

[0066] At 148, a cell comprising the first nanowire and the second nanowire is formed.

[0067] At 150, a second electrode is formed such that the second electrode is coupled to a second end of the first nanowire and an adjacent cell.

[0068] At 152, a further second electrode is formed such that the further second electrode is coupled to a second end of the second nanowire and a further adjacent cell. [0069] At 154, at least one of a portion at the second end of the first nanowire and the second end of the second nanowire are silicided, and a portion of the substrate is silicided to form a first electrode comprising a first electrode portion and a second electrode portion, wherein the first electrode portion is coupled to the first end of the first nanowire and wherein the second electrode portion is coupled to the first end of the second nanowire. In other words, a portion of the substrate and/or a portion at the second end of the first nanowire and the second nanowire are silicided.

[0070] In various embodiments, each of the first nanowire and the second nanowire comprises silicon (Si). In various embodiments, the plurality of nanowires comprise silicon. For example, each of the first nanowire and the second nanowire may be a silicon-based nanowire such as a silicon nanowire (e.g. a polycrystalline silicon nanowire), a silicon-germanium nanowire, a silicon-germanium heterojunction nanowire (e.g. Si-SiGe nanowire) and a silicon-germanium epitaxy nanowire.

[0071] In various embodiments, insulating spacers may be formed to surround the first nanowire and the second nanowire. The insulating spacers may be formed prior to silicidation.

[0072] In various embodiments, electrically insulating filling material may be disposed between the first nanowire and the second nanowire.

[0073] In various embodiments, the insulating spacers or dielectric spacers are formed prior to forming the first electrode and the second electrode so as to ensure metallic/ohmic contacts are formed (only) at the tips of the nanowires (e.g. the first end and the second end of each nanowire) whilst the remaining portion of each nanowire is covered with the insulating spacers.

[0074] As an example and not limitation, in forming the first electrode, a dielectric spacer is formed around the wires and etched to expose only the top tips of the nanowires (e.g. the first and second nanowires) such that these exposed tips may be silicided, whilst the rest of the sidewall of each nanowire remains covered with the dielectric spacer. Silicidation may then be performed on the exposed top tips and the bottom ends (i.e. the first and second ends) of the nanowires. Therefore, the first electrode (e.g. the bottom electrode) is coupled to the first nanowire and the second nanowire and may include a portion of the ends of the nanowires. [0075] In the context of various embodiments, each of the nanowires (e.g. including the first nanowire and the second nanowire) may be any one of a silicon (Si) nanowire, a silicon germanium (SiGe) nanowire or a silicon heterojunction nanowire (e.g. Si-SiGe nanowire). In the context of various embodiments, each of the nanowires may be textured (e.g. rough) or non-textured (e.g. smooth). In other words, the surface of the nanowires may be rough or smooth.

[0076] In the context of various embodiments, the term "first nanowire" may include one or more nanowires. In other words, there may be a number of nanowires or an array of nanowires, e.g. an array of hundreds or thousands of nanowires (i.e. first nanowires). This similarly applies to the term "second nanowire". In addition, a reference to a nanowire may include a reference to nanowires.

[0077] In the context of various embodiments, the doping atoms of either the first conductivity type or the second conductivity type are atoms which may be doped in the first nanowire or the second nanowire to provide p-doped nanowire while the other nanowire doped with the doping atoms of the other conductivity type are n-doped.

[0078] The term "p-doped" may mean a host material that is doped with doping atoms that may accept weakly-bound outer electrons from the host material, thereby creating vacancies left behind by the electrons, known as holes. Such doping atoms are also generally referred to as acceptors.

[0079] The term "n-doped" may mean a host material that is doped with doping atoms that may provide extra conduction electrons to the host material, thereby resulting in an electrically conductive n-doped host material with an excess number of mobile electrons (negatively charged carriers). Such doping atoms are also generally referred to as donors.

[0080] In various embodiments, where the host material is silicon (e.g. silicon nanowire), which is a Group IV, the nanowire may be doped or implanted with Group III doping atoms or elements, for example boron (B), aluminium (Al) or gallium (Ga), to form a p- doped nanowire, or doped or implanted with Group V doping atoms or elements, for example phosphorus (P), arsenic (As) or antimony (Sb), to form an n-doped nanowire. Subsequently, the doped material may be annealed. [0081] In the context of various embodiments, the insulating spacers formed to surround the first nanowire and the second nanowire may be silicon nitride (S13N4) or silicon dioxide (Si0₂) spacers.

[0082] In the context of various embodiments, the electrically insulating filling material disposed between the first nanowire and the second nanowire may also be thermally low conducting. In the context of various embodiments, the electrically insulating filling material may be a dielectric material. In the context of various embodiments, the electrically insulating filling material may be selected from the group consisting of polyamide, polyimide, parylene, silicon based dielectric, air and any combination thereof. In the context of various embodiments, the electrically insulating filling material may include a dielectric comprising silicon, for example silicon oxide or silicon nitride. In the context of various embodiments, any electrical insulator may be used as the electrically insulating filling material. For example, Polyamide may have an electrical conductivity of about 0.12W/mK.

[0083] In the context of various embodiments, air as used as the electrically insulating filling material may be air pockets or air gaps.

[0084] In the context of various embodiments, silicidation is performed to form metal silicides, for example for electrical contact. Silicidation may be performed, for example, using a rapid-thermal annealing (RTA) process, a laser annealing process or a furnace annealing process. In various embodiments, silicidation of the top and bottom electrodes facilitates forming of ohmic contacts and reduction of the parasitics, thereby improving the performance of the thermoelectric device. In various embodiments, a dielectric spacer is formed around the nanowires and then etched to expose only the top tips of the nanowires such that these exposed tips may be silicided, whilst the rest of the sidewall of each nanowire remains covered with the dielectric spacer. Silicidation may then be performed on the exposed top tips and the bottom ends (i.e. the first and second ends) of the nanowires, and including the bottom electrode.

[0085] In various embodiments, a portion of the substrate coupled to the first ends of nanowires (e.g. the first nanowire and the second nanowire) is silicided to form an electrode such that the electrode is coupled to the first nanowire and the second nanowire and also the electrode includes a portion of the first end of each of the first nanowire and the second nanowire. In various embodiments, where silicidation is carried out at a portion of the ends (e.g. the first end and/or the second end) of each nanowire, the portion of the ends of each nanowire silicided may form part of the electrode.

[0086] In the context of various embodiments, the term "nanowire" may mean a nanostructure extending, for example in a longitudinal direction, with dimensions in the order of nanometers, and may be used interchangeably with the terms "nanorod", "nanopillar", "nanocolumn", "nanotubes" and the likes.

[0087] FIG. 2A shows a schematic cross-sectional view of a thermoelectric device 200, according to various embodiments. The thermoelectric device 200 may be fabricated on a silicon-on-insulator (SOI) substrate, including a silicon substrate 202 and a buried oxide layer (BOX) 204, e.g. a layer of silicon oxide (Si0₂).

[0088] In various embodiments, any silicon on insulator substrates may be used, for example silicon on buried oxide or silicon on nitride.

[0089] The thermoelectric device 200 includes a plurality of silicon nanowires (e.g. 206) etched onto the SOI substrate. The thermoelectric device 200 further includes a plurality of cells (e.g. an individual cell is represented as 208). Each cell 208 includes an electrode (e.g. a bottom electrode) 209, one or more n-doped silicon nanowires (e.g. 210), one or more p-doped silicon nanowires (e.g. 212) and one or more undoped silicon nanowires (e.g. 214). An end of each of the n-doped silicon nanowires 210, p-doped silicon nanowires 212 and undoped silicon nanowires 214, is coupled to the electrode 209. In various embodiments, the bottom electrode 209 may include a first electrode portion and a second electrode portion, where the first electrode portion is coupled to an end of the n- doped silicon nanowires 210, and the second electrode portion is coupled to an end of a p-doped silicon nanowires 212.

[0090] The thermoelectric device 200 further includes one or more top electrodes (e.g. 216). Each top electrode 216 is coupled to another end of each of the n-doped silicon nanowires 210 of a cell 208 and also coupled to another end of each of the p-doped silicon nanowires of an adjacent cell. Therefore, the top electrode 216 may provide a bridging connection between nanowires of adjacent cells (e.g. 208).

[0091] The thermoelectric device 200 further includes a passivation layer 218, for example a layer of silicon nitride (S13N4) or silicon dioxide (Si0₂). [0092] In various embodiments, the n-doped silicon nanowires 210 and the p-doped silicon nanowires 212 may be formed by implantation of the respective type of doping atoms, followed by annealing.

[0093] In further embodiments, areas or regions of the substrate may be pre-doped (e.g. n-doped and pre-doped) by ion implantation prior to forming the nanowires through etching.

[0094] In various embodiments, the thermoelectric device 200 employs or applies the Peltier effect to the n-doped silicon nanowires 210 and the p-doped silicon nanowires 212 to cool, for example, the heat flux on the top electrode 216 (e.g. a hot spot). In various embodiments, conversely, the thermoelectric device 200 employs or applies the Seebeck effect to the n-doped silicon nanowires 210 and the p-doped silicon nanowires 212 to generate power based on an existing temperature gradient.

[0095] As an example and referrring to FIG. 2, heat (for example as represented by the arrow 220) applied or generated causes a hot spot or a heated surface 222. On the opposite side to the hot spot 222, the heat may be spread or dispersed (for example as represented by the arrows 224), which may be aided or facilitated by a material or a component (e.g. a heat spreader) 226 provided with the thermoelectric device 200.

[0096] FIG. 2B shows a schematic view of a thermoelectric equivalent of adjacent cells (e.g. 208) of the thermoelectric device 200 of the embodiment of FIG. 2A. As shown in FIG. 2B, a temperature difference between the top surface 228 (e.g. illustrated as a 'cold' surface) and the bottom surface 230 (e.g. illustrated as a 'hot' surface) is accompanied by an electric current 232. As an example and not limitation and as illustrated in FIG. 2B, where there is a temperature difference between the top surface 228 and the bottom surface 230, an electric current 232 may flow in a direction from the bottom electrode 209 of a cell 208, through the n-doped silicon nanowire 210, the top electrode 216, the p- doped silicon nanowire 212, to the bottom electrode 209 of an adjacent cell.

[0097] In various embodiments, conversely, an electric current 232 flowing through the cell 208 may result in a temperature difference between the top surface 228 and the bottom surface 230.

[0098] In various embodiments, each of the silicon nanowire may have a characteristic or performance as shown in Table 1. In various embodiments, the silicon nanowires may have a width of between about 2 nm to about 50 nm, for example between about 10 nm to about 40 nm or about 20 nm to about 30 nm. In various embodiments, the silicon nanowires may have a length of between about 2 μπι to about 50 μπι, for example between about 10 μπι to about 40 μιη or about 20 um to about 30 um. However, it should be appreciated that the dimensions of the nanowires are not limited to the values indicated and therefore other values may be provided in various embodiments.

Table 1 : Simulated thermoelectric performance of a silicon nanowire

Dimensions of a single nanowire 50 nm x 50 nm x 2 μηι

dT(max) at 0 W heat load 62°C at 300 K, 4.5 μΑ

Heat load (max) at 0°C cooling 0.2 μ\ν at 300K, 5.5 μΑ

Heat flux (max) at 0°C cooling 8000 W/cm² at 300K, 5.5 μΑ

[0099] FIGS. 3A and 3B show a schematic cross-sectional view and a schematic perspective view respectively of a fabrication process for manufacturing a thermoelectric device, according to various embodiments. A silicon-on-insulator (SOI) substrate 302, including a silicon substrate 304 and a buried oxide layer (BOX) 306, e.g. a layer of silicon oxide (Si0₂), is provided as the substrate for the thermoelectric device of various embodiments.

[0100] In various embodiments, an anisotropic deep reactive ion etching (DRIE) process is performed to etch an array of nanowires into the SOI substrate 302. As shown in FIGS. 3 A and 3B, a structure 310 may be obtained, including an array or a plurality of silicon nanowires, e.g. 312.

[0101] Subsequently, ion implantations are performed using the appropriate doping atoms to form N elements including n-doped nanowires and P elements including p- doped nanowires. As shown in FIG. 3A, a structure 320 may be obtained, including n- doped nanowires 322 and p-doped nanowires 324. In addition, there are undoped nanowires 312, for example located in between the n-doped nanowires 322 and the p- doped nanowires 324. Therefore, the structure 320 includes a successive arrangement of n-doped nanowires 322, undoped nanowires 312, p-doped nanowires 324, undoped nanowires 312, n-doped nanowires 322 and so on, for example. Such a successive arrangement may be provided along the x-direction and/or the y-direction. [0102] Referring to FIG. 3B, a structure 326 may also be obtained, where the structure 326 includes an alternating arrangement of n-doped nanowires 322 and p-doped nanowires 324 without any undoped nanowires in between. Such an alternating arrangement may be provided along the x-direction and/or the y-direction.

[0103] A dry etching process is then carried out to etch individual isolated silicon islands to define and form electrically isolated individual cells or modules, where each cell includes n-doped nanowires and p-doped nanowires. As shown in FIG. 3A, a structure 330 may be obtained, including individual and adjacent cells 332a and 332b. As an example and not limitation, the cell 332a includes a silicon island 334a, n-doped nanowires 322a, undoped nanowires 312 and p-doped nanowires 324a, while the adjacent cell 332b includes a silicon island 334b, n-doped nanowires 322b, undoped nanowires 312 and p-doped nanowires 324b.

[0104] Referring to FIG. 3B, a structure 340 may also be obtained, where the structure 340 includes a plurality of cells. As an example and with reference to the individual cell 332c, the cell 332c includes a silicon island 334c, an n-doped nanowire 322c and a p- doped nanowire 324c.

[0105] For illustration and clarity purposes, FIG. 3A shows that each cell (e.g. 332a, 332b) includes two n-doped nanowires (e.g. 322a, 322b) and two p-doped nanowires (e.g. 324a, 324b) while FIG. 3B shows that each cell (e.g. 332c) includes an n-doped nanowire (e.g. 322c) and a p-doped nanowire (e.g. 324c). However, it should be appreciated that in various embodiments, each cell (e.g. 332a, 332b, 332c) may include a plurality of n- doped nanowires and a plurality of p-doped nanowires. For example, each cell (e.g. 332a, 332b, 332c) may include a plurality of each type of doped nanowires in a range of between 1 to about 5000 nanowires, for example a range of between about 1 to about 1000 nanowires, a range of between about 1 to about 500 nanowires, a range of between about 500 to about 3000 nanowires, or a range of between about 1000 to about 2000 nanowires. However, it should be appreciated that any number of nanowires may be provided.

[0106] In various embodiments, a layer of insulating spacer (e.g. S13N4 or Si0₂) may then be formed to substantially surround the surface of the nanowires. Subsequently, the layer of the insulating spacer surrounding the tips of the nanowires may be etched to expose the tips. Metals, for example nickel (Ni), platinum (Pt), cobalt (Co) and titanium (Ti), may be deposited, for example on the exposed tips of the nanowires and the exposed surfaces of the silicon islands. A heat treatment process, may then be carried out for silicidation of the top ends (tips) and bottom ends of the nanowires, whilst the remaining portions of the nanowires are protected or covered by the insulating spacers. During silicidation, the bottom ends of the nanowires coupled to the silicon islands, as well as the silicon islands, may be silicided to form the bottom electrodes.

[0107] As shown in FIG. 3A, a structure 346 may be obtained, including silicided portions 348 at the tips of the n-doped nanowires (e.g. 322a, 322b), the p-doped nanowires (e.g. 324a, 324b) and the undoped nanowires 312 of the cells (e.g. 332a, 332b). In addition, each cell (e.g. 332a, 332b) includes a silicided bottom electrode (e.g. 348a, 348b). While not shown in FIG.3A, the sidewalls of the nanowires may be covered with a layer of insulating spacer.

[0108] Referring to FIG. 3B, a structure 350 may also be obtained, where the structure 350 includes silicided portions 352 at the tips of the n-doped nanowires (e.g. 322, 322c) and the p-doped nanowires (e.g. 324, 324c), and silicided portions 354 on the silicon islands (e.g. 334c). In various embodiments, the silicon islands (e.g. 334c) with the silicided portions 354 may act as the bottom electrodes. While not shown in FIG. 3B, the silicided portions 354 may cover areas of the bottom ends of the n-doped nanowires (e.g. 322, 322c) and the p-doped nanowires (e.g. 324, 324c). While not shown in FIG. 3B, the sidewalls of the nanowires may be covered with a layer of insulating spacer.

[0109] In various embodiment, an electrically insulating (dielectric) filling material may be provided for inter-nanowire filling, for example to fill the spaces between the nanowires for insulation and to provide structural integrity against any mechanical stress. An etch back process may then be performed to remove a portion of the filling material to expose the silicided top tips of the nanowires. Subsequently, a layer of metal, for example aluminum (Al), may be sputtered across the wafer, patterned and etched to form the top electrodes. In various embodiments, other metals may be used, including but not limited to copper (Cu), gold (Au), platinum (Pt), nickel (Ni), titanium-nitride (TiN), tantalum- nitride (TaN) and aluminium-vanadium (Al-V). Gold and platinum may be used for III-V materials. [0110] As shown in FIG. 3A, a structure 360 may be obtained, including an electrically insulating filling material 362 and top electrodes 364a, 364b, 364c. As shown for the structure 360, as an example and not limitation, for the cell 332a, the bottom ends of the n-doped nanowires 322a and the p-doped nanowires 324a are coupled to the bottom electrode 348a while the top ends of the n-doped nanowires 322a are coupled to the top electrode 364a and the top ends of the p-doped nanowires 324a are coupled to the top electrode 364b. In addition, for the cell 332b, the bottom ends of the n-doped nanowires 322b and the p-doped nanowires 324b are coupled to the bottom electrode 348b while the top ends of the n-doped nanowires 322b are coupled to the top electrode 364b and the top ends of the p-doped nanowires 324b are coupled to the top electrode 364c. Therefore, the top electrode 364b provides a bridging electrical connection between the adjacent cells 332a, 332b.

[0111] Referring to FIG. 3B, a structure 370 may also be obtained, including an electrically insulating filling material 372. Subsequently after metalisation to form the top electrodes, a structure 374 may be obtained, including a plurality of top electrodes, e.g. 376, 376a, 376b, 376c. As shown for the structure 374, as an example and not limitation, for the cell 332c, the bottom ends of the n-doped nanowire 322c and the p-doped nanowire 324c are coupled to the bottom electrode 378 while the top end of the p-doped nanowire 324c is coupled to the top electrode 376a and the top end of the n-doped nanowire 322c is coupled to the top electrode 376b. In addition, for the cell 332d, the bottom ends of the n-doped nanowire 322d and the p-doped nanowire 324d are coupled to the bottom electrode 380 while the top end of the p-doped nanowire 324d is coupled to the top electrode 376b and the top end of the n-doped nanowire 322d is coupled to the top electrode 376c. Therefore, the top electrode 376b provides a bridging electrical connection between the adjacent cells 332c, 332d.

[0112] In various embodiments, passivation of the thermoelectric device is performed, for example by providing or depositing a passivation layer (e.g. a layer of Si0₂). In various embodiments, a further dielectric layer may be provided on the passivation layer. Subsequently, the electrodes may be released, for example by etching or removing part of the substrate 304. As shown in FIG. 3A, a structure 386 may be obtained, including a layer of passivation 388 and a dielectric layer 390. The dielectric layer 390 may be of any dielectric material such as silicon oxide (Si0₂), silicon nitride (S13N4) or any material that is a good heat conductor and an electrical insulator. In various embodiments, the dielectric layer 390 may serve to passivate the structure 386 from any external effects or elements, for example to minimise or prevent any undesired connections (e.g. electrical connections) in subsequent processing or use.

Fabrication and experimental data

[0113] In various embodiments, a method as illustrated in the embodiments of FIGS. 3 A and 3B may be carried out to fabricate thermoelectric devices.

[0114] A silicon-on-insulator (SOI) substrate is used as the substrate for the thermoelectric device as the substrate may provide electrical and thermal isolation. The substrate is lithographically patterned with nano dots and may then be etched using anisotropic deep reactive ion etching (DRIE) to form nanowires, based on the patterned nano dots. In various embodiments, during the DRIE, cycles of etching with C₄F₈ and SFe gases, passivating the etched part with C4F8 gas and then etching again to form deep (long) pillars, may be carried out.

[0115] In various embodiments, the diameter of the nanowires etched may be modulated with self limiting oxidation, which is an oxidation process that stops or slows down considerably after a few hours due to the thick layer of oxide formed which restricts any further oxidation. In various embodiments, the oxidation process is performed at about 1000°C.

[0116] FIG. 4A shows SEM images 400, 402, 404, of the silicon nanowires formed, according to various embodiments, after a dry etching (DRIE) process. As shown in the SEM image 400, the surface of the silicon nanowires may be smooth. As shown in the SEM image 404, the surface of the silicon nanowires may be rough.

[0117] In various embodiments, silicon-germanium heterojunction nanowires, as shown in the SEM image of FIG. 4B may be also be formed.

[0118] P and N elements (e.g. p-doped nanowires and n-doped nanoriwes) of the thermoelectric device may be defined or formed through ion implantation. In various embodiments, each P element and/or each N element may include a plurality of nanowires as one bundle. [0119] Individual isolated silicon islands of P elements and N elements are formed by dry etching to define individual P/N couples or pairs, which are electrically isolated from neighboring couples or pairs. In other words, the individual silicon islands are electrically isolated from each other. Therefore, after this dry etching process, the P element and the N element of a silicon island are electrically isolated from the P element and the N element of another silicon island. In various embodiments, a similar process to that used for forming the nanowires may be carried out, but for a shallow etch.

[0120] In various embodiments, the N elements and the P elements serve as individual thermoelectric elements connected electrically in series and thermally in parallel.

[0121] A silicon nitride dielectric spacer or layer may then be formed on the surfaces of the nanowires. Subsequently, etching may be carried out to etch the dielectric spacer surrounding the tips of the nanowires so as to expose the tips. With the sidewalls of the nanowires covered or protected by the remaining dielectric spacer, the top and bottom electrodes are then formed by nickel (Ni) deposition, followed by a silicidation process.

[0122] FIG. 4C shows an SEM image 422 of the nanowire array after formation of silicon islands, e.g. 424, 426, and before the formation of bottom electrodes, according to various embodiments. The silicon islands (as represented by 424 and 426 in the SEM image 422), including P N nanowire couples or pairs, are formed after a dry etching process. As can be seen in the SEM image 422, each of the silicon islands 424, 426, includes an array of nanowires which may be of the embodiments shown in SEM images 400, 402, 404, of FIG. 4A. In various embodiments, the bottom electrode within each silicon island 424, 426, is formed using silicidation.

[0123] The spaces between the nanowires are then filled with high-density plasma (HDP) oxide for structural integrity against any mechanical stress. A contact oxide etch is then performed to expose the silicided top tips of the nanowires. FIG. 4D shows an SEM image 430 of the tips 432 of the nanowire array exposed after contact oxide etch, according to various embodiments. The SEM image 430 also shows the HDP oxide 434 provided in the spaces between the nanowires. In various embodiments, it should be appreciated that the spaces between the nanowires may be filled with any electrical insulator, for example parylene, polyimide or silicon-based dielectric. [0124] Lithography may be performed to define the areas for the top electrodes and metalisation may then be carried out, where a layer of aluminum (Al) is sputtered across the wafer and patterned and etched to form the top electrodes. However, it should be appreciated that any metals may be used to form the top electrodes.

[0125] FIG. 4E shows an SEM image 443 of photoresist patterns, as represented by 447, for forming the top electrodes, according to various embodiments. For illustration purposes, the letters 'N' and 'P' are superimposed on some of the photoresist patterns 447, where the top electrodes may be formed, to illustrate where the n-doped nanowires (e.g. N elements) and the p-doped nanowires (e.g. P elements) may be. In addition, for illustration purposes, the dotted rectangular boxes 449a are superimposed on some of the photoresist patterns 447 to illustrate where the bottom electrodes may be.

[0126] As can be seen in the SEM image 443, there are also nanowires in the spaces (for example as represented by the dotted circle 448 to illustrate an area) in between where the top electrodes may be formed.

[0127] FIG. 4F shows a schematic representation 410 of a nanowire array after lithography patterning, ion implantation and formation of n-doped and p-doped nanowires, according to various embodiments. The lithography patterning and ion implantation are performed to form n-doped nanowires (e.g. N elements 414) and p- doped nanowires (e.g. P elements 416). For the schematic representation 410 of FIG. 4F, the N elements 414 and the P elements 416 are arranged altematingly. It should be appreciated that there may be a plurality of nanowires (hundreds or thousands of nanowires) in each of the N elements 414 and the P elements 416. As shown in the schematic representation 410, top electrodes, e.g. as represented by the dotted box 418 for one such top electrode, may be formed over a pair of N elements 414 and P elements 416.

[0128] FIG. 4F also shows a microscope image 450 of a nanowire array after lithography patterning, ion implantation and formation of n-doped and p-doped nanowires. Top electrodes, e.g. as represented by the dotted box 452 may be formed over a pair of N elements and P elements.

[0129] In various embodiments, the thermoelectride device may have dimentions of approximately 5 mm x 5 mm x 2 μνα, with an active area of about 4 mm x 4 mm. [0130] In various embodiments, a number of thermoelectric devices of the embodiment as shown, may be provided, for example in a vertical arrangement (e.g. vertically stacked) to form a vertical thermoelectric device or module.

[0131] In various embodiments, by providing a plurality of top electrodes, location or site selectivity for example for cooling, may be achieved.

[0132] Subsequently, the performance of the thermoelectric device of various embodiments may be determined. FIG. 5 shows a schematic of a measurement setup 500, according to various embodiments. The measurement set-up 500 includes a substrate 502, a test chip 504, a thermal interface material (TIM) 506, a thermoelectric device 508 of various embodiments and a heat sink or heat spreader 510. The measurement set-up 500 may be used for measuring or determimng the characteristics of the thermoelectric device 506. During measurements, the test chip 504 may be configured as a hot surface while the heat sink 510 may be configured as a cold surface.

[0133] The substrate 502 may be a dedicated test board where measurements may be taken and may act as a substrate for the test chip 504. The test chip 504 is flipped chip bonded onto the substrate 502.

[0134] The test chip 504 may be self- fabricated to simulate a microchip, for example for thermal testing and hot spot simulation. The test chip 504 may include 3 layers of heater lines for heating or temperature sensing, and may be fabricated on a layer of temperature detection diode and a heating substrate.

[0135] FIG. 6A shows a plot 600 of current-voltage (I-V) characteristics of a thermoelectric device, according to various embodiments. The plot 600 shows the I-V curves of the thermoelectric device (e.g. thermoelectric device 508 of FIG. 5) when different numbers of elements (e.g. N elements and P elements) are connected. The linear relationship observed in the plot 600 of I-V curves show that ohmic contacts are formed between the nanowires and the top electrodes.

[0136] FIG. 6B shows a plot 620 of resistance of a thermoelectric device, according to various embodiments, when different numbers of elements are connected. The plot 620 may be obtained, for example, by calculating the resistance based on the I-V characteristics of the plot 600 of FIG. 6A. [0137] In various embodiments, temperature gradient may be set up using the test chip (e.g. test chip 504 of FIG. 5) upon power being supplied. The measurement set-up including the thermoelectric device for determining the temperature variation, dT, includes several thermal stacks which act as a parasitic to lower the effective dT across the thermoelectric device.

[0138] FIG. 7 shows a thermal stack 700, according to various embodiments. The thermal stack 700 may be used for the estimation of temperature variation, dT, across the thermoelectric device 710. The thermal stack includes a test chip 702 (thickness of about 700 μπι; thermal conductivity of about 150 W/mK; thermal resistance of about 4.7 m²K/W), a thermal interface material (TIM) 704 (about 50 μπι; about 0.7 W/mK; about 71 m²K/W), a silicon substrate 706 (about 200 μιη; about 150 W/mK; about 1.3 m²K/W), a bottom oxide 708 (about 1 μιη; about 1.4 W/mK; about 0.71 m²K/W), a silicon nanowire thermoelectric device (TED) 710 (about 1 μπι; about 25 W/mK; about 0.08 m²K/W) and a top aluminium electrode 712 (about 1 μιη; about 235 W/mK; about 0.004 m²K/W). The thermal conductivities of the individual layers are the bulk values, except for the silicon nano wires which has been estimated for a 50 nm diameter VLS grown silicon nanowire.

[0139] In various embodiments, the larger the thermal resistance, the larger the dT across the layer. Therefore, as the layer of TIM 704 has the largest thermal resistance, it has the largest dT across it.

[0140] 2D thermal calculation may be used to estimate the dT across the TED 710 upon determining the dT across the stack 700 using a micro thermocouple tip attached to the top and the test chip's resistance temperature detector (RTD).

[0141] FIG. 8 shows a plot 800 of current-voltage (I-V) characteristics of a thermoelectric device at different temperature gradients, according to various embodiments. A heater may be used to provide heating and different powers may be applied to the heater, resulting in different dT values across the thermoelectric device.

[0142] As shown in FIG. 8, the curves up-shift when dT is increased, showing thermoelectric generation. The results also show that power is generated in the presence of a temperature gradient. [0143] Different dT values may be applied across the thermoelectric device, based on the thermal stack 700 of the embodiment of FIG. 7 for the measurement of the open circuit voltage output, Voc, of the thermoelectric device.

[0144] FIG. 9 A shows a plot 900 of the Voc generated for different dT applied across the thermoelectric device. A linear relationship may be observed across the data points, suggesting that the thermoelectric device of various embodiments obeys the Seebeck effect. In other words, the Voc generated by the thermoelectric device is related to the dT across it and the Seebeck coefficient of the thermoelectric material. As shown in FIG. 9A, a Voc of approximately 1.5 mV may be obtained for an estimated dT of about 36.7mK.

[0145] A best fit line may be drawn through the data points in plot 900 of FIG. 9A and the results may be extrapolated. FIG. 9B shows a plot 920 of the extrapolated open circuit voltage for dT up to 2 K of the plot 900 of FIG. 9A, assuming no change in the parameters or conditions (i.e. constant conditions) as that applicable for the measurements carried out to obtain the results shown in FIG. 9A. Fig. 9B shows that a Voc of approximately 41 mV and 81 mV may be obtained respectively at a dT of 1 K and 2 K.

[0146] For a Voc of about 41 mV, the corresponding power output may be about 4.1 μ\ν. In various embodiments, the output power, and therefore the power generation performance, may be further increased by reducing the contact resistance between the nanowires and the top metal electrodes. In various embodiments, with the reduction of parasitics, the thermoelectric devices of various embodiments may generate a power of up to about 225 μW for a temperature gradient of about 1 K, which is the temperature gradient that may be harvested in chips.

[0147] FIG. 10A shows a plot 1000 of power generated for different dT applied across the thermoelectric device at different currents, according to various embodiments. Plot 1000 of FIG. 10A includes extrapolated results, assuming no change in the parameters or conditions (i.e. constant conditions) as that applicable for the measurements carried out to obtain part of the results shown in FIG. 10A.

[0148] FIG. 10B shows a plot 1020 of voltage and power generated at dT of 36.7 mK across the thermoelectric device at different currents, according to various embodiments. FIG. 10B shows that for dT of about 36.7 mK, an open circuit voltage Voc of about 1.5 mV and a short circuit current Isc of about 3.79 μΑ may be obtained.

[0149] In various embodiments, the external dT across the whole stack (e.g. the thermal stack 700 of FIG. 7) may be approximately 72 K with the TIM layer (e.g. TIM 704 of FIG. 7) having the largest dT across it. This may result in a very small effective dT for power generation and thus, the less than ideal expectation. The thermoelectric device fabricated has a thermoelectric material thickness of approximately 1 μιη. Such a thin thermoelectric device may have enhanced performance when it is integrated directly onto specific applications, such as on-chip waste energy harvesting, to minimize the parasitic loss, for example as shown in FIG. 13.

[0150] FIG. 11 shows a plot 1100 of temperature against current for a thermoelectric device, according to various embodiments. As can be seen in FIG. 11, the silicon nanowire thermoelectric device may function as a thermoelectric cooler, where temperature may drop or decrease at a hot spot. Passive cooling of about 8°C may be observed.

[0151] The performances of the thermoelectric device of various embodiments may be simulated using finite element simulations.

[0152] FIG. 12A shows a plot 1200 of simulated cooling performance with varying heat load, according to various embodiments.

[0153] FIG. 12B shows a plot 1210 of simulated cooling performance for different heat load power density, according to various embodiments. FIG. 12B shows that a cooling power density of about 6.6xl0³ W/cm² may be obtained, which is about 2 orders larger than that of conventional thermoelectric module.

[0154] FIG. 12C shows a plot 1220 of simulated cooling temperature with different thermal conductivities, according to various embodiments. FIG. 12C shows that a material of low thermal conductivity provides better cooling performance.

[0155] FIG. 12D shows simulated results for different dimensions of silicon nanowires, according to various embodiments. FIG. 12D shows a plot 1230 of thermal conductivity for different diameters of the nanowires, a plot 1232 of cooling temperature against current for silicon nanowires of different diameters, and a plot 1234 of maximum cooling temperature for silicon nanowires of different diameters. These results show that thermoelectric technology may be aligned towards silicon-based CMOS technologies.

[0156] The thermoelectric devices of various embodiments may be used in high performance electronic units, compact heat exchangers, small power generators, pharmaceutical temperature stabilizers, avionics, and environmental analyzers, amongst others. The thermoelectric devices or coolers may be used for heat removal ranging from milli-watts up to several thousand watts for a general range of applications. Besides microprocessor cooling, where the thermoelectric devices may be provided for on chip cooling, they may also be used in equipment used by military, medical, industrial, scientific/laboratory, and telecommunications organizations.

[0157] The thermoelectric devices of various embodiments may also be used to address the cooling issues of many electrical components such as optoelectronic devices, for example semiconductor lasers, photo detectors and CCD switches, that generate large heat fluxes, and also bio analytical devices which are temperature sensitive.

[0158] Furthermore, as thermoelectric materials also serve as major players in global sustainable energy sources, thermoelectric devices such as those of various embodiments, may be used to supplement batteries and may generate electricity from waste heat generated by local hot spots on chips, automobiles and exhausts. By potentially diverting this waste heat to on-chip self-powered circuits, a whole range of portable low power applications may be provided. Thermoelectric generators have an advantage over batteries in that they are more robust, have almost infinite lifetimes and use environmentally friendly materials. In addition, with a reduction in contact parasitic, the Si-based nanowire thermoelectric device may provide cheaper, scalable and easy to integrate thermoelectric power generators to provide viable solutions to hot spot cooling/waste energy harvesting. Furthermore, nanoscale thermoelectric energy harvesting may also be applied to current high heat flux applications such as lasers and sensors, to generate energy.

[0159] In addition, various embodiments provide a technology and method that fits or that may be adapted to be employed in the current fabrication schemes and using conventional semiconductors, that may provide a cumulative cost effective result to all the related industries. [0160] FIG. 13 shows a schematic of an integrated chip-level thermal management module 1300, according to various embodiments. The thermal management module 1300 includes a thermoelectric device 1302 of various embodiments, coupled to a heat sink 1304 and a chip module, via epoxy interfaces 1306. The chip module includes a plurality of chips, as represented by 1308 for one such chip, coupled to a substrate 1310. The chip module further includes a cap 1312 coupled to the chips 1308 via a thermal paste 1314.

[0161] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A thermoelectric device, comprising:

a plurality of cells, each cell comprising:

a first electrode comprising a first electrode portion and a second electrode portion;

a first nanowire, wherein a first end of the first nanowire is coupled to the first electrode portion of the first electrode, the first nanowire being doped with doping atoms of a first conductivity type; and

a second nanowire, wherein a first end of the second nanowire is coupled to the second electrode portion of the first electrode, the second nanowire being doped with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type; and wherein a second end of the first nanowire is coupled to a second electrode, the second electrode coupled to an adjacent cell;

wherein a second end of the second nanowire is coupled to a further second electrode, the further second electrode coupled to a further adjacent cell; and

wherein at least one of the first electrode and a portion at the second end of the first nanowire and the second end of the second nanowire are silicided.

2. The thermoelectric device of claim 1, wherein each of the first nanowire and the second nanowire comprises silicon.

3. The thermoelectric device of claim 2, wherein each of the first nanowire and the second nanowire is one of a silicon nanowire, a silicon germanium nanowire or a silicon heterojunction nanowire.

4. The thermoelectric device of any one of claims 1 to 3, further comprising insulating spacers surrounding the first nanowire and the second nanowire.

5. The thermoelectric device of claim 4, wherein the insulating spacers are silicon nitride or silicon dioxide spacers.

6. The thermoelectric device of any one of claims 1 to 5, further comprising electrically insulating filling material disposed between the first nanowire and the second nanowire.

7. The thermoelectric device of claim 6, wherein the electrically insulating filling material is selected from the group consisting of polyamide, polyimide, parylene, silicon based dielectric, air and any combination thereof.

8. The thermoelectric device of any one of claims 1 to 7, wherein each of the first nanowire and the second nanowire is textured.

9. The thermoelectric device of any one of claims 1 to 8, wherein each of the first nanowire and the second nanowire has a length of between about 2 μπι to about 50 um.

10. The thermoelectric device of any one of claims 1 to 9, wherein each of the first nanowire and the second nanowire has a width of between about 2 nm to about 50 nm.

11. A method for manufacturing a thermoelectric device comprising a plurality of cells, the method comprising:

forming a plurality of nanowires, wherein a first end of the nanowires is coupled to a substrate;

doping a first nanowire of the plurality of nanowires, with doping atoms of a first conductivity type;

doping a second nanowire of the plurality of nanowires, with doping atoms of a second conductivity type, the second conductivity type is different from the first conductivity type;

forming a cell comprising the first nanowire and the second nanowire; forming a second electrode such that the second electrode is coupled to a second end of the first nanowire and an adjacent cell;

forming a further second electrode such that the further second electrode is coupled to a second end of the second nanowire and a further adjacent cell; and

siliciding at least one of a portion at the second end of the first nanowire and the second end of the second nanowire, and a portion of the substrate to form a first electrode comprising a first electrode portion and a second electrode portion, wherein the first electrode portion is coupled to the first end of the first nanowire and wherein the second electrode portion is coupled to the first end of the second nanowire.

12. The method of claim 11, wherein each of the first nanowire and the second nanowire comprises silicon.

13. The method of claim 12, wherein each of the first nanowire and the second nanowire is one of a silicon nanowire, a silicon germanium nanowire or a silicon heterojunction nanowire.

14. The method of any one of claims 11 to 13, further comprising forming insulating spacers surrounding the first nanowire and the second nanowire.

15. The method of claim 14, wherein the insulating spacers are silicon nitride or silicon dioxide spacers.

16. The method of any one of claims 11 to 15, further comprising disposing electrically insulating filling material between the first nanowire and the second nanowire.

17. The method of claim 16, wherein the electrically insulating filling material is selected from the group consisting of polyamide, polyimide, parylene, silicon based dielectric, air and any combination thereof.

18. The method of any one of claims 11 to 17, wherein each of the first nanowire and the second nanowire is textured.

19. The method of any one of claims 11 to 18, wherein each of the first nanowire and the second nanowire has a length of between about 2 μπι to about 50 μπι.

20. The method of any one of claims 11 to 19, wherein each of the first nanowire and the second nanowire has a width of between about 2 nm to about 50 nm.