JP2011072020A - Decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoding device corresponding to multirate. <P>SOLUTION: The decoding device can separately use a plurality of low-density parity-check codes having different encoding rates. In a plurality of check matrices H, corresponding to the plurality of the low-density parity-check codes, code length N of the low-density parity-check code and weight column wc of the check matrix H are common. Moreover, a set of numbers expressing the column position of a non-zero element, included in the check matrix H, is common among the plurality of the check matrices. However, the difference of weight row wr between the plurality of the check matrices H causes the encoding rate R of the plurality of the check matrices H to be different. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a low-density parity check code decoding apparatus.

  In recent years, low-density parity check (LDPC) codes and sum-product decoding methods, which are decoding methods thereof, have attracted attention as one of error correction techniques (Non-patent Document 1 and Patents). Reference 1).

  The LDPC code is a linear code defined by a very sparse check matrix, and was invented by Gallager. With this LDPC code, it is known that a decoding characteristic of 0.004 dB can be obtained up to the Shannon limit of the white Gaussian channel. In addition, since the sum-product decoding method performs decoding processing by parallel processing, the code length can be increased and the processing capability can be improved.

In an LDPC code, in order to obtain better correction capability, it is necessary to define an appropriate check matrix. Here, a method for generating a parity check matrix proposed by Gallager is as follows.
First, the parity check matrix H to be generated has a column weight (hamming weight of the column; the number of 1 (non-zero elements) in each column) is wc, a row weight (hamming weight of the row; 1 (non-zero element) in each row) It is assumed that (number) is wr. In this case, the parity check matrix H is divided into wc = 3 blocks in the row direction of the parity check matrix H as shown in FIG.

  Here, the row weight wr = 6, and in the first block (H1), “1” (non-zero element) is arranged in the first column to the sixth column of the first row, and the second row In the seventh to twelfth columns, “1” (non-zero element) is arranged, and similarly, “1” (non-zero element) is also arranged for the following rows in the first block. Here, they are arranged so that the column weight of each column in the first block (H1) is 1.

Then, an arbitrary column in the first block is rearranged (replaced) using random numbers, and this is repeated a suitable number of times as the first block. Since the weight of each column of the first block is 1, the column weight remains 1 even if the columns are replaced.
For the second and subsequent blocks as well, similar to the first block, column replacement processing is performed using random numbers (random numbers different from other blocks) so that the arrangement of non-zero elements is different for each block.
If the above processing is performed for wc = 3 blocks, a parity check matrix having a column weight of wc is generated.

  In the LDPC code, the parity check matrix is generally determined using random numbers as described above. That is, by using random numbers, the arrangement of “1” (non-zero element) in the parity check matrix has no regularity, and the correction capability can be ensured.

  In recent years, it has been desired to change the check matrix for each communication location according to the state of communication error. That is, efficient communication can be realized by properly using a plurality of codes between communication companies. For example, 114 codes are defined in WiMAX, and 12 codes are defined in IEEE 802.11n.

Here, Non-Patent Document 2 discloses an LCPD code decoder that supports multi-rate. In consideration of implementation in hardware, the decoder of Non-Patent Document 2 adopts a block division type as a parity check matrix structure, and divides the parity check matrix according to the coding rate. . By dividing the parity check matrix according to the coding rate, it is possible to configure a decoder whose hardware configuration does not become enormous even if there are a plurality of parity check matrices.
When the S / N ratio is inferior, it is possible to increase the decoding throughput by adopting a parity check matrix configuration with a low coding rate, and when the S / N ratio is good, increasing the coding rate.

JP 2005-269535 A

Wadayama Tadashi, “About Low Density Parity Check Codes and Decoding Methods”, IEICE Technical Report, MR2001-83, December 2001 Yuta Imai (4 others), “Implementation of dynamically reconfigurable multi-rate LDPC code decoder”, IEICE Technical Report, RECONF 2006-43, November 2006

In the decoder of Non-Patent Document 2, the coding rate is “0.5”, “0.625”, “0.75”.
The code length N at each coding rate becomes 1536 bits, 2048 bits, and 3072 bits, respectively, by dividing the parity check matrix according to the coding rate. Has been.

  As described above, in the decoder of Non-Patent Document 2, the code length N increases as the encoding rate R increases, and the code length decreases as the encoding rate decreases. In Patent Document 2, it is presumed that the result that the code length is shortened as the coding rate is lowered because the configuration of the block division type is adopted in preference to the hardware implementation.

  However, when the communication environment is poor such as a low S / N ratio, the code length N is increased by increasing the number of redundant bits added to the information bits in order to reduce the coding rate R and increase the error correction capability. This is the general idea. Here, the code length N is the sum of the number of information bits K and the number of redundant bits M, and the coding rate R is represented by “number of information bits K / code length N”.

Therefore, when it is desired to reduce the coding rate R, if the code length N is shortened, a sufficient number of redundant bits may not be added, and the code length becomes shorter as the coding rate is lowered as in Non-Patent Document 2. This is inconsistent with the general method of adding redundant bits and is a disadvantageous restriction.
Therefore, it is desirable that the coding rate (correction capability) can be changed without the code length changing in conjunction.

  On the other hand, from the viewpoint of hardware implementation, if the circuits of a plurality of parity check matrices corresponding to a plurality of coding rates are completely different, the circuit scale becomes enormous. Therefore, in order to avoid enlarging the circuit scale, conventionally, as in Non-Patent Document 2, there has been a disadvantage that the code length is shortened as the coding rate is lowered.

Therefore, an object of the present invention is to use a plurality of parity check matrices corresponding to different coding rates without suffering from the disadvantageous restriction that the code length becomes shorter as the coding rate is lowered. Even in this case, it is possible to suppress an increase in circuit scale.
Another object of the present invention is to provide a check matrix that can be expressed based on a rule.

  The present invention is a decoding apparatus that can selectively use a plurality of low density parity check codes having different coding rates, and the plurality of check matrices corresponding to the plurality of low density parity check codes are low density parity check codes. The code length and the column weight of the check matrix are common, and a set of numbers indicating the column positions of the non-zero elements included in the check matrix is common among the plurality of check matrices, and the row weight is a plurality of checks. The decoding apparatus includes a plurality of parity check matrixes having different coding rates by being different between matrices.

  Here, the column weight is the number of non-zero elements included in each column of the parity check matrix, and the row weight is the number of non-zero elements included in each row of the parity check matrix. In the regular check matrix of the low-density parity check code, “total number of non-zero elements in the check matrix” = “column weight × number of columns of the check matrix” = “row weight × number of rows of the check matrix” holds.

According to the present invention, since the code length is common in a plurality of parity check matrices corresponding to a plurality of coding rates, the code length does not change depending on the coding rate.
In the present invention, since the column weights are also common to the plurality of parity check matrices, the relational expression “total number of non-zero elements in the parity check matrix” = “column weight × number of columns of the parity check matrix (code length)” The total number of non-zero elements is common among a plurality of parity check matrices with different coding rates. That is, the number of elements in a set of numbers indicating the column positions of non-zero elements included in the parity check matrix is common among the plurality of parity check matrices.

Then, from the relational expression “total number of non-zero elements in the parity check matrix” = “row weight × number of rows in the parity check matrix (number of redundant bits)”, the coding rate is different because the row weight is different among a plurality of parity check matrices. In other words, the number of rows (redundant bits) is different among the plurality of parity check matrices while the code length is common.
Thus, if the row weight is changed at a common code length in order to change the coding rate, the number of rows in the parity check matrix changes, which increases or decreases redundant bits. That is, changing the row weight changes the proportion of information bits in a certain code length, and is based on the general idea when changing the coding rate.

Moreover, in the present invention, the code lengths and column weights of the plurality of parity check matrices are common, and a set of numbers indicating the column positions of the non-zero elements included in the parity check matrix is common among the plurality of parity check matrices. Therefore, when the circuit using the processing using the check matrix is implemented, a circuit related to the common point can be shared by a plurality of check matrices, and the circuit scale can be prevented from increasing.
In the present invention, the number of columns indicating the column positions of the non-zero elements is changed according to the row weights in each row of the parity check matrix. do it.

  In the present invention, the above relationship between a plurality of parity check matrices does not have to be satisfied in all of the plurality of parity check matrices used by the decoding device. It is only necessary that the “partial check matrix” satisfies the above relationship.

The code length is N, the column weight of the parity check matrix is wc, the row weight of the parity check matrix is wr, and at least wc numbers that are relatively prime to N are A1,. , J is a number greater than or equal to wc, and A1,..., Aj are different numbers), each row of the parity check matrix includes a number sequence corresponding to the number of rows of the parity check matrix. And it is preferable that the non-zero element is arrange | positioned in the column position corresponding to each number contained in the number sequence which respectively satisfy | fills the following conditions (A)-(B).
(A) Each number sequence corresponding to the number of rows of the parity check matrix is a partial number sequence obtained by dividing a basic number sequence satisfying the following conditions (C) to (D) into wr numbers.
(B) Each number of partial sequences corresponding to the number of rows of the parity check matrix is assigned to any one row of the parity check matrix.
(C) The numbers included in the basic number sequence are natural numbers of 1 to N.
(D) In the basic number sequence, the number of appearances of each of the natural numbers 1 to N is the same as the column weight value wc.
(E) the basic sequence, the tolerances A1, · ·, X-number of arithmetic progression is either Aj (However, the number adjacent to any number y _A and the number y _A included in the sequence y _Even if the difference from _B is not A, if the difference between y _A and (y _B + N) is A, the difference between y _A and y _B is considered to be A). .

The present inventor has found that the check matrix has a good correction capability similar to that generated by random numbers, although it conforms to the above conditions.
It should be noted that a plurality of patterns can be taken for one row in a sequence of “numbers” indicating the positions of non-zero elements present in each row of the parity check matrix. For example, even if the parity check matrix satisfies the above conditions (A) to (E), a numerical sequence in which “numbers” indicating the positions of non-zero elements existing in one row of the parity check matrix are arranged in ascending order is as follows: It does not necessarily satisfy the condition (Equation Sequence) of (E) above.
However, in the present invention, it is only necessary that the non-zero elements are arranged at the column positions corresponding to the numbers included in the arithmetic sequence, and the sequence considered based on the arrangement of the non-zero elements in the parity check matrix is a condition. It is not necessary to consider whether or not (E) is satisfied. That is, it is sufficient if each row of the check matrix can have a number sequence that satisfies the condition (E).

  A plurality of partial sequences are assigned to each row of the parity check matrix so that the order of arrangement of the plurality of partial sequences in the basic number sequence matches the order of the rows of the parity check matrix to which the partial number sequence is assigned. Is preferred.

  In addition, it is preferable to support multirate by changing the row weight of the check matrix according to the communication rate.

In addition, the present invention relating to a parity check matrix generation method uses a code length N of a low density parity check code, a numerical value A that is relatively prime to N, and a row weight wr of the parity check matrix to generate a low density parity check code. A method for generating a parity check matrix of a parity check code, wherein the row weight changing step changes wr according to a communication rate, and each of P rows (P is a natural number of 2 or more) included in the parity check matrix A position calculating step for calculating the position of the zero element; and an arranging step for arranging a non-zero element at the position calculated by the position calculating step. In the position calculating step, the variable x is set to the initial value x _1. To (x ₁ + (N−1)) while calculating (A × x) by N to obtain a remainder to obtain N calculation results. In the arrangement step, Consists of N calculation results Dividing the column into P partial sequences of wr numbers, with the numbers contained in the P partial sequences as the column positions of the nonzero elements, and placing the nonzero elements in the corresponding P rows, This is a parity check matrix generation method.

  According to the present invention, it is possible to use a plurality of parity check matrices corresponding to different coding rates without being restricted by the fact that the code length becomes shorter as the coding rate is lowered, but this is a case where hardware is implemented. However, the increase in circuit scale can be suppressed.

1 is a diagram schematically showing a configuration of a communication system. It is a figure which shows an example of a response | compatibility with transmission data and demodulation data. It is a figure which shows the structure of a decoder roughly. It is an example of a check matrix (not an embodiment of the present invention) shown for reference. 5 is a Tanner graph of the parity check matrix shown in FIG. It is a block diagram of a primary estimated word production | generation part. It is a figure which shows one example of the check matrix which concerns on embodiment. It is a figure which shows the test matrix which concerns on a comparative example. It is explanatory drawing regarding the method of the production | generation of a check matrix. It is explanatory drawing of a basic number sequence. It is a relationship figure of column weight and row weight, and a coding rate. This is a parity check matrix with a coding rate R = 1/2. This is a parity check matrix with a coding rate R = 2/3. This is a parity check matrix with a coding rate R = 3/4. This is a parity check matrix with a coding rate R = 13/16. It is a BER characteristic view. It is a block diagram of an external value logarithm ratio calculation part. It is a block diagram of a line processing part. It is a block diagram of the minimum value search part. It is a block diagram of the minimum value search part. It is a block diagram of the minimum value search part. It is explanatory drawing of the production | generation method of the conventional test matrix.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a configuration of a communication system having a decoding device (decoder) 5 according to an embodiment of the present invention. In FIG. 1, a transmission side communication apparatus of a communication system includes an encoder 1 that generates a transmission code by adding redundant bits for error correction to transmission information, and a code of (K + M) bits from the encoder 1. And a modulator 2 that modulates the signal according to a predetermined method and outputs the result to the communication path 3.

  The encoder 1 adds M bits of redundant bits for parity calculation to the information of K bits, and generates an LDPC code (low density parity check code) of (K + M) = N bits.

  The modulator 2 performs modulation such as amplitude modulation, phase modulation, code modulation, frequency modulation or orthogonal frequency division multiplexing modulation according to the configuration of the communication path 3. For example, when the communication path 3 is an optical fiber, the modulator 2 performs light intensity modulation (a kind of amplitude modulation) by changing the luminance of the laser diode according to the transmission information bit value. For example, when the transmission data bit is “0”, it is converted to “+1”, and the laser diode is transmitted with an increased emission intensity. When the transmission data bit is “1”, it is changed to “−1”. After conversion, the emission intensity of the laser diode is weakened and transmitted.

  The receiving-side communication device of the communication system performs demodulation processing on the modulated signal transmitted via the communication path 3 to demodulate the (K + M) -bit digital code, and (K + M) from the demodulator 4. ) A decoder (decoding device) 5 is provided that performs decoding processing based on a parity check matrix on a bit code to reproduce the original K-bit information.

  The demodulator 4 performs demodulation processing according to the transmission form in the communication path 3. For example, in the case of amplitude modulation, phase modulation, code modulation, frequency modulation, orthogonal frequency division multiplexing modulation, etc., the demodulator 4 performs processing such as amplitude demodulation, phase demodulation, code demodulation, and frequency demodulation.

  FIG. 2 is a diagram showing a list of correspondence relationships between the output data of the modulator 2 and the demodulator 4 when the communication path 3 is an optical fiber. In FIG. 2, as described above, when the communication path 3 is an optical fiber, the modulator 2 converts the transmission data to “1” when the transmission data is “0”, and the transmission laser diode (light emitting diode) When the emission intensity increases and the transmission data bit is “1”, it is converted to “−1”, and the emission intensity of the laser diode is reduced to transmit.

The light intensity transmitted to the demodulator 4 due to transmission loss in the communication path 3 has an analog intensity distribution from the strongest intensity to the weakest intensity. The demodulator 4 performs a quantization process (analog / digital conversion) on the input optical signal to detect the received light level.
FIG. 2 shows the received signal intensity when the light reception level is quantized in eight steps. That is, when the light reception level is data “7”, the light emission intensity is considerably high, and when the light reception level is “0”, the light intensity is considerably low. Each light reception level is associated with signed data and output from the demodulator 4. The output of the demodulator 4 is data “3” when the light reception level is “7”, and data “−4” when the light reception level is “0”. Therefore, the demodulator 4 outputs a signal subjected to multilevel quantization with respect to a 1-bit received signal.

  The decoder 5 receives (K + M) -bit received information (each bit includes multi-value information) given from the demodulator 4 and has low density according to the sum-product decoding method or the min-sum decoding method. A parity check matrix is applied to restore the original K-bit information.

  In FIG. 2, the demodulator 4 generates bits quantized to 8 levels. However, in general, the demodulator 4 can perform decoding using bits quantized to L values (L ≧ 2).

  In FIG. 2, a binary signal may be generated by using a comparator to determine the level of the received signal using a certain threshold value.

FIG. 3 is a diagram schematically showing the configuration of the decoder 5. In FIG. 3, the demodulator 4 and the communication path 3 are also shown. The demodulator 4 includes a demodulation circuit 4a that demodulates a signal applied from the communication path 3, and an analog / digital conversion circuit 4b that converts an analog demodulated signal generated by the demodulation circuit 4a into a digital signal.
Output data Xn of the analog / digital conversion circuit 4b is applied to the decoder 5. The data Xn given to the decoder 5 is data of L value (L ≧ 2). Hereinafter, since the data Xn is multilevel quantized data, it is referred to as a symbol. The decoder 5 performs a decoding process on the input symbol Xn sequence according to a decoding method such as a sum-product decoding method or a min-sum decoding method to generate a code bit Cn.

  The decoder 5 performs a decoding operation process by a logarithmic likelihood ratio calculation unit 6 that generates the log likelihood ratio λn of the demodulated symbol Xn from the demodulator 4 and an iterative operation based on the log likelihood ratio λn and the parity check matrix. An external value log ratio calculation unit (decoding processing unit) 7, a decoded word generation unit 199 that generates a decoded word based on the external value log ratio α mn and the log likelihood ratio λ n calculated by the external value log ratio calculation unit 7; ,including.

The log likelihood ratio calculation unit 6 generates a log likelihood ratio λn independently of the noise information of the received signal. Normally, when noise information is taken into consideration, this log likelihood ratio λn is given by Xn / (2 · σ · σ). Here, σ represents noise variance.
However, in the present embodiment, the log likelihood ratio calculation unit 6 is formed of a buffer circuit or a constant multiplier circuit, and the log likelihood ratio λn is given by Xn · f. Here, f is a non-zero positive number. Further, in the min-sum decoding method, since the calculation is performed using the minimum value in the decoding process (row process) based on the parity check matrix, linearity is maintained in the signal processing. For this reason, processing such as normalization of output data according to noise information is unnecessary. In this case, by calculating the log-likelihood ratio without using noise information, the circuit configuration is simplified and the calculation process is also simplified.

Here, the external value log ratio calculation unit 7 performs a decoding process by a min-sum decoding method. Note that the decoding method may be a sum-product decoding method.
The external value log ratio calculation unit 7 performs arithmetic processing according to the following equations (1) and (2), and processes (row processing) and columns for each element (non-zero element: 1) in the row of the parity check matrix. The processing (column processing) for each element (non-zero element: 1) is repeatedly executed.

Here, in each of the above formulas (1) and (2), n′εA (m) \ n and m′εB (n) \ m mean elements other than themselves.
For the external value log ratio αmn, n ′ ≠ n, and for the prior value log ratio βmn, m ′ ≠ m. Further, the subscript “mn” indicating the position in the matrix of α and β is usually indicated by a subscript, but in this specification, it is indicated by “horizontal characters” for the sake of readability.

The function sign (x) is defined by the following equation (3).

In addition, the sets A (m) and B (n) have a set [1, N] = {1, 2, when the binary M · N matrix H = [Hmn] is a parity check matrix of the LDPC code to be decoded. .., N}.
A (m) = {n: Hmn = 1} (4)
B (n) = {m: Hmn = 1} (5)

  That is, the subset A (m) means a set of column indexes where 1 (non-zero element) stands in the m-th row of the parity check matrix H, and the subset B (n) A set of row indexes where 1 (non-zero element) stands in the n-th column is shown.

  Specifically, consider the parity check matrix H shown in FIG. In the parity check matrix H shown in FIG. 4, “1” stands in the first to third columns of the first row, “1” stands for the third and fourth columns of the second row, and “1” stands in the fourth column to the sixth column of the three rows. Therefore, in this case, the subset A (m) is as follows.

A (1) = {1, 2, 3}
A (2) = {3,4}
A (3) = {4, 5, 6}

Similarly, the subset B (n) is as follows.
B (1) = B (2) = {1}
B (3) = {1, 2}
B (4) = {2,3}
B (5) = B (6) = {3}

  In the parity check matrix H, when a Tanner graph is used, the connection relationship between a variable node corresponding to a column and a check node corresponding to a row is indicated by “1”. This is referred to as “1” stands ”in this specification. That is, as shown in FIG. 5, the variable nodes 1, 2, and 3 are connected to the check node X (first row), and the variable nodes 3 and 4 are connected to the check node Y (second row). The variable nodes 4, 5, and 6 are connected to the check node Z (third row). This variable node corresponds to a column of the check matrix H, and check nodes X, Y, and Z correspond to each row of the check matrix H. Therefore, the parity check matrix shown in FIG. 4 is applied to a code having a code length of 6 bits in total including 3 information bits and 3 redundant bits.

  In the LDPC parity check matrix H, the number of “1” s is small, and the parity check matrix is a low density, thereby reducing the amount of calculation.

  Each condition probability P (Xi | Yi) is propagated between the variable node and the check node, and a plausible code is determined for each variable node according to the MAP algorithm. Here, the conditional probability P (Xi | Yi) indicates the probability of being Xi under the condition of Yi.

  Referring to FIG. 3 again, decoded word generating section 199 that generates a decoded word based on external value log ratio αmn and log likelihood ratio λn includes primary estimated word generating section 180 and decoded word determining section 190. Including.

FIG. 6 is a diagram illustrating the configuration of the primary estimated word generation unit 180.
Referring to FIG. 6, primary estimated word generation unit 180 includes a Qn calculation unit 140 and a Cn calculation unit 141.

The Qn calculation unit 140 uses the log likelihood ratio λ from the log likelihood ratio calculation unit 6 and the external value log ratio α mn from the external log ratio calculation unit 7 according to the following equation (6) to estimate the received word (Q ₁ , Q ₂ ,..., Q _N ) are calculated.

The Cn calculation unit 141 calculates primary estimated words (C ₁ , C ₂ ,..., C _N ) according to the following equation (7). Here, the notation of (C ₁ , C ₂ ,..., C _N ) indicates that the first bit (LSB: Least Significant Bit) of the N-bit primary estimation word is C ₁ and the second bit is C _2. , and the indicating that the N bits (MSN) is a _{C N.}

Referring to FIG. 3 again, decoded word determining section 190 determines whether or not primary estimated words (C ₁ , C ₂ ,..., C _N ) form code words from primary estimated word generation section 180. inspect. When the following equation (8) is satisfied, that is, when the syndrome becomes “0”, the decoded word determining unit 190 ends the iterative calculation of the external value logarithmic ratio calculating unit 7 and the primary estimated word (C ₁ , C ₂ ,..., C _N ), that is, the information bits of K bits, that is, (C ₁ , C ₂ ,..., C _K ) are output to the outside of the decoder 5 as decoded words. . The decoded word determination unit 190 also terminates the iterative operation of the external value log ratio calculation unit 7 even when the number of loops, that is, the number of repetitions of the operation of the external value log ratio calculation unit 7 exceeds a predetermined value. , The K bit information bit portion of the primary estimation word (C ₁ , C ₂ ,..., C _N ), ie, (C ₁ , C ₂ ,..., C _K ) as a decoding word. 5 is output to the outside.
(C ₁ , C ₂ ,..., C _N ) · H ^t = 0 (where H ^t represents transposition of H (8))

  The decoder 5 of the present embodiment as described above can cope with a plurality of codes by properly using a plurality of check matrices. In the present embodiment, the decoding device 4 can selectively use a plurality of low density parity check codes having different coding rates. The coding rate can be determined according to the communication rate in a communication apparatus that can handle multi-rates. The coding rate is decreased at a high rate, and the coding rate is increased at a low rate. The communication rate is determined according to the channel quality such as the SN ratio or CIN ratio detected by the communication apparatus, and the decoding apparatus performs decoding using a check matrix corresponding to the determined coding rate. In the present embodiment, the row weight of the parity check matrix is changed in order to cope with different coding rates.

[Check matrix]
FIG. 7 shows a specific example of LDPC code parity check matrix H ₉₆ used in decoder 5 of the present embodiment. Check matrix _{H 96} in FIG. 7, the code length N = 96, row weight wr = 6, shows column weight wc = 3 for regular inspection matrix (matrix size = 48 × 96). In FIG. 7, a place where “1” (nonzero element) of the parity check matrix exists is indicated by a point. In the parity check matrix H ₉₆ in FIG. 7, there are 288 points indicating non-zero elements.

As a comparative example, FIG. 8 shows a regular check matrix of the same size generated by the Gallager method (random number based method) shown in FIG. In the parity check matrix of FIG. 8, the row weight wr and the column weight wc are the same as those in FIG.
Since the parity check matrix of FIG. 8 has no regularity, at least 2016 bits are required as information for expressing the parity check matrix. That is, in order to express the parity check matrix of FIG. 8, the positions (column numbers; column indexes) of the points in each row are listed, and the fact that the number of points per row is 6 is used. Each row can be reproduced by recording the positions of the points listed in. Therefore, in this system, each point takes a numerical value of 1 to 96, and 7 bits are required for each point. Therefore, 288 points and 7 × 288 × = 2016 are required.

On the other hand, the parity check matrix H ₉₆ in FIG. 7 according to the present embodiment can be expressed by three numerical values A1, A2, and A3 that are relatively prime to the code length N. Here, if the numerical values A1, A2 and A3 are smaller than the code length N, one numerical value can be expressed by 7 bits, so 7 × 3 = 21 bits is sufficient, and even if N is added, 7 × 4 = 28 bits is sufficient. In the present embodiment, the numbers A1 to A3 are prepared in numbers corresponding to the column weights wc.
Note that when a plurality of numerical values A1, A2, and A3 that are relatively prime to N are collectively referred to without distinction, they are simply referred to as “numerical value A”.

The parity check matrix H _{96 in} FIG. 7 corresponds to the column weight wc being 3, and when the parity check matrix H ₉₆ is viewed as partial matrices (blocks) H1 to H3 divided into three in the row direction, FIG. As shown, the first block H1 is generated by the numerical value A1, the second block H2 is generated by the numerical value A2, and the third block is generated by the numerical value A3. That is, each block can be configured by being given a numerical value A. Also, by making the numerical value A that is relatively prime with respect to N, such as A1 to A3, it is possible to generate a plurality of blocks H1 to H3 with different arrangements of non-zero elements.

In the check matrix H ₉₆ of FIG. 7, each of the blocks H1 to H3 is a partial matrix having a column weight of 1 and a row weight of 6. By combining these blocks H1 to H3, the blocks of FIG. A check matrix H ₉₆ is obtained.
In each of the blocks H1 to H3 in FIG. 7, a row of points (non-zero elements) facing in an oblique direction are arranged approximately regularly with a substantially constant interval. The slope of the point row and the interval between the point rows are different for each of the blocks H1 to H3.

  In each of the blocks H1 to H3 in FIG. 7, at first glance (when viewed macroscopically), it appears that the rows of points facing diagonally are arranged in a straight line. However, when viewed strictly (when viewed microscopically), the sequence of dots in FIG. 7 is not linearly arranged with points (non-zero elements), but rather is arranged in a meandering manner. As described above, the column weight of each of the blocks H1 to H3 is 1, and in order to ensure that only one point (non-zero element) exists at one column position in each of the blocks H1 to H3, However, the meandering of the points may be slightly different, or the intervals between the points constituting the row of points may be different.

In the parity check matrix H _{96 of} FIG. 7, the sequence of points is substantially equally spaced, and the distribution of the points (non-zero elements) is a uniform sparse matrix throughout the parity check matrix, which adversely affects the correction capability. A short cycle is hardly generated, and a good correction capability is obtained.

[Check matrix generation rule according to this embodiment]
The decoder 5 of the present embodiment performs decoding using the check matrix H ₉₆ having the above characteristics. The generation rule of the first block H1 of this check matrix H ₉₆ is as follows. The number of rows P included in each of the blocks H1 to H3 is P = row length M / column weight wr = 48/3 = 16.

(0: Row weight change step) The row weight wr is determined according to the communication rate.
(1) Let N be the code length (length in the column direction of the check matrix).
(2) A1 is a value that is relatively prime to N.
(3) variable x, initial values _{x 1} from _(x 1 + (N-1)) to until the following (3-1) (3-2) repeated processing of (N times iteration). Here, it is assumed that the initial value x ₁ = 1.
(3-1: Position Calculation Step) Mod (A1 × x, N) is calculated, and 1 is added to the result. That is, “mod (A1 × x, N) +1” is calculated. Note that mod (A1 × x, N) is a function for obtaining a remainder when (A1 × x) is divided by N.
(3-2: Arrangement Step) The non-zero element “1” is arranged at the column position indicated by the result (column index) of “mod (A1 × x, N) +1” in the first block H1. For example, if the calculation result of “mod (A1 × x, N) +1” is “10”, “1” is set in the 10th column of the designated row. The row where “1” is arranged is sequentially switched from the first row to the P-th row of the first block H1. Each row is sequentially arranged with the number “1” corresponding to the row weight wr, and when one row is set with the number “1” corresponding to the row weight, the operation proceeds to the next row and similarly the row weight amount is set. Set the number of "1".

  Here, the number calculated by “mod (A1 × x, N) +1” indicates the column position (column index) where “1” should be placed in the parity check matrix, and “mod (A1 × x, N) “1” is set at the column position indicated by the value of +1 ″.

  Since A1 and N are relatively prime numbers, when x takes a numerical value from 1 to (N−1), A1 × x is not divisible by N. That is, when x takes a numerical value from 1 to (N−1), “mod (A1 × x, N) +1” generates the numerical value from 2 to N only once. When x = N, A1 × x is divisible by N, and the calculation result of “mod (A1 × x, N) +1” is 1.

Thus, when x takes a numerical value from 1 to N, “mod (A1 × x, N) +1” generates the numerical value from 1 to N only once.
In other words, all values can be generated as N calculation results without duplicating numerical values from 1 to N. For this reason, based on this calculation result, the check matrix (each block H1 to H3) is non-existent. If the zero element “1” is arranged, the non-zero element “1” can be arranged in each block at only one point for all the columns.

  Note that in the equation “mod (A1 × x, N) +1”, the essential operation is “mod (A1 × x, N)”. “+1” is used to correspond the calculation result of “mod (A1 × x, N)” (with a range of 0 to N−1) to the column index of the parity check matrix (with a range of 1 to N). It is a conversion process. Therefore, for example, if the range of the column index of the parity check matrix is (0 to N−1), the operation of “+1” is not necessary.

Further, in the above productions, it has been one of the initial value x ₁ of x, for example, may be other values. For example, x may be repeated in the range of 0 to N-1. When the initial value of x is adjusted, the numerical value generated by the calculation of “mod (A1 × x, N) +1” shifts, but the numerical values from 1 to N are generated only once, and x A parity check matrix having similar properties can be obtained by adjusting the initial value of.

Now, the position calculation step 3-1 and the arrangement step 3-2 will be described in more detail below. Here, N = 96 and A1 = 29. N = 96 and A1 = 29 are relatively prime.
Repeating the position calculating step 3-1 to the initial value _{x 1} to 6 times (the value of the row weight), it is obtained a total of six numbers of the {30,59,88,21,50,79} as follows .
mod (29 × 1,96) + 1 = 30
mod (29 × 2,96) + 1 = 59
mod (29 × 3, 96) + 1 = 88
mod (29 × 4, 96) + 1 = 21
mod (29 × 5, 96) + 1 = 50
mod (29 × 6, 96) + 1 = 79

  In arrangement step 3-2, when “mod (A1 × x, N) +1” is obtained, “1” is sequentially set in the check matrix (first block H1 thereof). That is, starting from the first row of the first block H1, “1” is set in the 30th, 59th, 88th, 21st, 50th, and 79th columns of the first row. Here, since the row weight wr = 6, “1” can be arranged in the first row by repeating 6 times.

When the arrangement of “1” in the first line is completed, “1” is arranged in the next line. That is, in the repetition of the seventh time (x = 7) to the twelfth time (x = 12), “1” is set at the column position indicated by “mod (A1 × x, N) +1” for the second row.
Similarly, in the 13th to 18th repetition, “1” is set in the 3rd line, and this is repeated thereafter until the 1st line to the Pth line (16th line) constituting the first block H1. N "1" s can be set in

  The generation rule is also applied to the second block H2 generated by the numerical value A2 and the third block generated by the numerical value A3. In this case, “A1” in the generation rule may be replaced with “A2” to “A3”. In order to abstract the generation rule “A1” so as not to be limited to “A1”, the generation rule “A1” may be set to “A”.

Therefore, in the (P + 1) -th to (2 × P) -th lines constituting the second block H2 of the check matrix H ₉₆ , N “1” s are based on the calculation result of the position calculation step using the variable A2. Is established. In the (2 × P + 1) -th to (3 × P) -th rows of the third block H3 of the check matrix H ₉₆ , N “1” s are based on the calculation result of the position calculation step using the variable A3. Is established.

The following is a calculation when the position calculation step is executed with the first block H1 of the parity check matrix H _{96 being} a numerical value A1 = 29, the second block H2 being a numerical value A2 = 31, and the third block H3 being a numerical value A3 = 37. Results are shown.

1st block H1
1st line: 30, 59, 88, 21, 50, 79
2nd line: 12, 41, 70, 3, 32, 61
3rd line: 90, 23, 52, 81, 14, 43
4th line: 72, 5 34, 63, 92, 25
5th line: 54, 83, 16, 45, 74, 7
6th line: 36, 65, 94, 27, 56, 85
7th line: 18, 47, 76, 9, 38, 67
8th line: 96, 29, 58, 87, 20, 49
9th line: 78, 11, 40, 69, 2, 31
10th line: 60, 89, 22, 51, 80, 13
11th line: 42, 71, 4, 33, 62, 91
12th line: 24, 53, 82, 15, 44, 73
13th line: 6, 35, 64, 93, 26, 55
14th line: 84, 17, 46, 75, 8, 37
15th line: 66, 95, 28, 57, 86, 19
16th line: 48, 77, 10, 39, 68, 1

Second block H2
17th line: 32, 63, 94, 29, 60, 91
18th line: 26, 57, 88, 23, 54, 85
19th line: 20, 51, 82, 17, 48, 79
20th line: 14, 45, 76, 11, 42, 73
21st line: 8, 39, 70, 5, 36, 67
22nd line: 2, 33, 64, 95, 30, 61
23rd line: 92, 27, 58, 89, 24, 55
24th line: 86, 21, 52, 83, 18, 49
25th line: 80, 15, 46, 77, 12, 43
26th line: 74, 9, 40, 71, 6, 37
27th line: 68, 3, 34, 65, 96, 31
28th line: 62, 93, 28, 59, 90, 25
29th line: 56, 87, 22, 53, 84, 19
30th line: 50, 81, 16, 47, 78, 13
31st line: 44, 75, 10, 41, 72, 7
32nd line: 38, 69, 4, 35, 66, 1

3rd block H3
33rd line: 38, 75, 16, 53, 90, 31
34th line: 68, 9, 46, 83, 24, 61
35th line: 2, 39, 76, 17, 54, 91
36th line: 32, 69, 10, 47, 84, 25
37th line: 62, 3, 40, 77, 18, 55
38th line: 92, 33, 70, 11, 48, 85
39th line: 26, 63, 4, 41, 78, 19
40th line: 56, 93, 34, 71, 12, 49
41st line: 86, 27, 64, 5, 42, 79
42nd line: 20, 57, 94, 35, 72, 13
43rd line: 50, 87, 28, 65, 6, 43
44th line: 80, 21, 58, 95, 36, 73
45th line: 14, 51, 88, 29, 66, 7
46th line: 44, 81, 22, 59, 96, 37
47th line: 74, 15, 52, 89, 30, 67
48th line: 8, 45, 82, 23, 60, 1

A parity check matrix H ₉₆ shown in FIG. 7 is obtained by arranging “1” (points in FIG. 7) on the (N × 3) numerical values (column positions) thus obtained.
As is clear from the above, the generation rule placement step 3-2 is N (= 96).
A sequence of N computation results is divided into _P (= 16) partial sequence S _{1 to} SP consisting of the number of row weights wr (= 6) of parity check matrix H ₉₆ , and P partial sequences S ₁ the number contained in the to S _P as a column position of the non-zero elements, by arranging the non-zero elements in the corresponding P rows (first row ~P line) which generates each block H1~H3 It can be said.

In order to facilitate the correspondence between the calculated numerical values indicating (N × 3) column positions and the points in FIG. 7, numerical values (column positions) in each row are rearranged in ascending order from the left. Shown in
1st block H1
1st line: 21, 30, 50, 59, 79, 88
2nd line: 3, 12, 32, 41, 61, 70
3rd line: 14, 23, 43, 52, 81, 90
4th line: 5, 25, 34, 63, 72, 92
5th line: 7, 16, 45, 54, 74, 83
6th line: 27, 36, 56, 65, 85, 94
7th line: 9, 18, 38, 47, 67, 76
8th line: 20, 29, 49, 58, 87, 96
9th line: 2, 11, 31, 40, 69, 78
10th line: 13, 22, 51, 60, 80, 89
11th line: 4, 33, 42, 62, 71, 91
12th line: 15, 24, 44, 53, 73, 82
13th line: 6, 26, 35, 55, 64, 93
14th line: 8, 17, 37, 46, 75, 84
15th line: 19, 28, 57, 66, 86, 95
16th line: 1,10,39,48,68,77

Second block H2
17th line: 29, 32, 60, 63, 91, 94
18th line: 23, 26, 54, 57, 85, 88
19th line: 17, 20, 48, 51, 79, 82
20th line: 11, 14, 42, 45, 73, 76
21st line: 5, 8, 36, 39, 67, 70
22nd line: 2, 30, 33, 61, 64, 95
23rd line: 24, 27, 55, 58, 89, 92
24th line: 18, 21, 49, 52, 83, 86
25th line: 12, 15, 43, 46, 77, 80
26th line: 6, 9, 37, 40, 71, 74
27th line: 3, 31, 34, 65, 68, 96
28th line: 25, 28, 59, 62, 90, 93
29th line: 19, 22, 53, 56, 84, 87
30th line: 13, 16, 47, 50, 78, 81
31st line: 7, 10, 41, 44, 72, 75
32nd line: 1, 4, 35, 38, 66, 69

3rd block H3
33rd line: 16, 31, 38, 53, 75, 90
34th line: 9, 24, 46, 61, 68, 83
35th line: 2, 17, 39, 54, 76, 91
36th line: 10, 25, 32, 47, 69, 84
37th line: 3, 18, 40, 55, 62, 77
38th line: 11, 33, 48, 70, 85, 92
39th line: 4, 19, 26, 41, 63, 78
40th line: 12, 34, 49, 56, 71, 93
41st line: 5, 27, 42, 64, 79, 86
42nd line: 13, 20, 35, 57, 72, 94
43rd line: 6, 28, 43, 50, 65, 87
44th line: 21, 36, 58, 73, 80, 95
45th line: 7, 14, 29, 51, 66, 88
46th line: 22, 37, 44, 59, 81, 96
47th line: 15, 30, 52, 67, 74, 89
48th line: 1, 8, 23, 45, 60, 82

As is apparent from the above result in which the numbers included in the partial sequence S _{1 to} S ₄₈ corresponding to each row are replaced in ascending order, in the first block H1, the difference between adjacent numbers in the sequence in which the numbers are replaced in ascending order is The value is around 9 or around 20. For this reason, as shown in FIG. 7, in the first block H <b> 1, the interval between the “dot rows” in the diagonal direction is about 10 in the row direction.
Further, in the second block H2, the difference between adjacent numbers in the sequence in which the numbers are replaced in ascending order is a value of around 3 or a value of around 28. For this reason, as shown in FIG. 7, in the second block H <b> 2, the interval between the “dot rows” in the diagonal direction is about 30 in the row direction.
Further, in the third block H3, the difference between adjacent numbers in the sequence in which the numbers are changed in ascending order is a value of around 7, a value of around 15, or a value of around 22. For this reason, as shown in FIG. 7, in the third block H <b> 3, the interval between the “dot rows” in the diagonal direction is about 7 in the row direction.
In the first to third blocks H1, H2, and H3, since the numerical values A1, A2, and A3 are different from each other, the slopes of the “sequence of points” are also different from each other.

[Characteristic matrix properties according to this embodiment]
The properties of the check matrix H _{96 according} to this embodiment are as follows.
Here, the calculation result obtained by repeating “mod (A1 × x, N) +1” N times from x = 1 to N as described above is considered as a sequence S arranged in the calculation order, and is as follows: Express. In the following, {} is used as a symbol surrounding a sequence of numbers.
Sequence S: {y ₁ , y ₂ ,..., Y _N }

Further, the partial sequence S ₁ to S _P indicating the column position of the non-zero elements in each row to the first row ~P row constituting the first block H1, expressed as follows.
Partial sequence corresponding to the first row S ₁ : {y ₁ , y ₂ ,..., Y ₆ }
Partial sequence corresponding to the second row S ₂ : {y ₇ , y ₈ ,..., Y ₁₂ }
・ ・
・ ・
・ ・
Partial sequence S _P-1 corresponding to the P-1 line: {y _N-11 , y _N-10 ,..., Y _N-6 }
Partial sequence corresponding to the P-th row S _P : {y _N-5 , y _N-4 ,..., Y _N }

The sequence S is the use of partial sequence _S 1 to S _P, it can be expressed as a concatenation sequence of partial sequences _S 1 to S _P, and specifically as follows.
Sequence S = {y ₁ , y ₂ ,..., Y _N } = {S ₁ , S ₂ ,..., S _P−1 , S _P }

The partial sequences S _{1 to} S _P have the following properties (1) and (2), as is apparent from the contents of the arithmetic processing in the position calculation step.
(Property 1) The partial sequences _S 1 to S _P is different for each row.
(Property 2) the number included in the partial sequence _S 1 to S _P is a natural number of 1 to N.

Moreover, partial sequences _S 1 to S _P is tolerance has become a arithmetic progression is A1 (Property 3).
This is an operation of mod (A1 × x, N). When x is increased by one, A1 × x increases by A1 (= 29) and is calculated by mod (A1 × x, N). This is because the remainder also increases by A1 (= 29).

For example, the first partial sequence S ₁ corresponding to the first row is {30, 59, 88, 21, 50, 79} as described above. In this case, the difference between the first term “30” of the first partial sequence S ₁ and the adjacent second term “59” is A1 = 29.
Similarly, the difference between the other terms is 29, but the difference between “88” in the fourth term and “21” in the fifth term is “−67”, not “29”.
This is because the calculation result of mod (A1 × x, N) does not exceed N due to the nature of the calculation for calculating the remainder mod (A1 × x, N), and mod (A1 × x, N) This is because N) also increases, but increases cyclically between 1 and N.

Under the assumption that mod (A1 × x, N) increases cyclically between 1 and N, even if the difference between adjacent numbers in the sequence is not A1, the difference (first partial sequence S ₁₎ If the difference between the fourth term “88” and the fifth term “21” is “−67” plus N = 96), the difference may be regarded as A1. .
These exceptions, but also present in other partial sequence S ₂ to S _P, a difference between numerical values such exceptions, it regarded as A1, all partial sequences S ₁ to S _P is , “It is an arithmetic sequence of tolerance A1”.

In other words, the above (Property 3) can be rephrased as follows.
(Property 3) is a partial sequence _S 1 to S _P is arithmetic progression tolerance is A1 (However, the number adjacent to any number _{y A} and the number _{y A} included in the partial sequence _S 1 to S _P Even if the difference from y _B is not A, if the difference between y _A and (y _B + N) is A, the difference between y _A and y _B is regarded as A).

Moreover, the condition that A1 and N are relatively prime, partial sequences _S 1 to S _P also has the following properties.
(Characteristic 4) In a plurality of equality sequences having the same tolerance A (partial number sequences S _{1 to} S _P ), the number of appearances of each of natural numbers 1 to N is within one.

Moreover, partial sequences _S 1 to S _P of the check matrix _{H 96} produced according to the above generated rule also has the following properties.
(Property 5) P partial number sequences S _{1 to} S _P are obtained by dividing the connected number sequence S into P parts.
(Property 6) P number of partial sequences _S 1 to S _P is the order of the P of the partial sequence _S 1 to S _P in the connection sequence S, P consecutive rows (first row ~P line Are assigned to P consecutive rows (1st row to Pth row) included in the parity check matrix H ₉₆ so that the order of the eye) matches.

Further, the connected sequence S generated according to the generation rule has the following property.
(Characteristic 7) The concatenated number sequence S has “number” corresponding to the total number of non-zero elements included in P consecutive rows (1st to Pth rows).
(Property 8) The numbers included in the connected number sequence S are natural numbers of 1 to N.
(Nature 9) In the connected number sequence S, the number of appearances of each of the natural numbers 1 to N is within one.
(Property 10) The connected number sequence S is an even number sequence having a tolerance of A1 (however, a difference between an arbitrary number y _A included in the connected number sequence and a number y _B adjacent to the number y _A is A1. If the difference between y _A and (y _B + N) is A1, the difference between y _A and y _B is regarded as A1.

As shown in the above (Property 10), the sequence S: {y ₁ , y ₂ ,..., Y _N } is also an equidistant sequence with a tolerance of A1. This is obvious from the nature of the operation for calculating the remainder mod (A1 × x, N), as in (Property 3).

Note that (property 6) indicates that the line where “1” is arranged in the generation rule arrangement step 3-2 so as to satisfy the (property 6) is changed from the first line to the P-th line of the first block H1. Therefore, for example, first, the odd-numbered lines from the first line to the P-th line are sequentially switched to place “1”, and then the even-numbered lines from the first line to the P-th line. When the switching rule of sequentially switching to rows and arranging “1” is adopted, (Property 6) does not hold.
In addition, after generating a parity check matrix satisfying the properties 1 to 10, (Property 6) is lost when row replacement (column replacement) between rows (columns) included in the parity check matrix is performed.
However, even if such a special switching rule is adopted, blocks that satisfy the properties 1 to 4 are still generated from the numerical value A1.
In the above case, the above (property 6) can be rephrased as follows, and even when row substitution or the like is performed and the above (property 5) is not satisfied, the properties 5 to 10 can be satisfied. .

(Property 6) P number sequences are respectively assigned to P rows or P columns included in the parity check matrix.

The above properties 1-10 has been described sequence group _S 1 to S _P of the first block H1, similarly holds for sequences groups other block H2, H3. That is, the other blocks H2 and H3 are different from the first block H1 in the numerical value that is relatively prime to N, and the other points are generated in the same manner as the first block H1.
Thus, the nature 1-10, holds the entire check matrix _{H 96.} In addition, since the properties 1 to 10 are established regardless of the code length N, the properties 1 to 10 can be generalized to a check matrix H having an arbitrary code length (column length).

[Method of determining numerical values A1, A2, A2]
Numerical A1, A2, A3 determination procedure is the generation information for generating the check matrix H ₉₆ is, for example, as follows. Here, the numerical values A1, A2, and A3 are numerical values that are relatively prime to N, respectively. The numerical values A1, A2, and A3 are different numerical values. Here, it is assumed that numerical values A1, A2, and A3 <N.

(Determination Procedure 1) Set 1 is created.
A set of numbers obtained by factoring N is defined as set 1. When N is 96, the set 1 is (2, 2, 2, 2, 2, 3).

(Determination Procedure 2) Set 2 is created.
Let prime numbers up to N be set 2. When N is 96, the set 2 is (2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47).

(Determination Procedure 3) Set 3 is created.
A set 3 is obtained by removing the elements of set 1 from set 2. If N is 96, set 2 is (5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47).

(Determination Procedure 4) A set of candidate sets of numerical values A1, A2, and A3 is created.
The number of elements corresponding to the column weight wc (= 3) is taken from the set 3, and the set of these three numerical values A1, A2, A3 is taken as one candidate. Since there are 13 elements in the set 3, there are 13C3 = 286 candidates. Let 286 candidates be set 4.

(Decision Procedure 5) One candidate set (A1, A2, A3) is taken out from the set 4, and a check matrix is generated according to the generation rule.

(Determination Procedure 6) The parity check matrix generated in the determination procedure 5 is evaluated. The evaluation can be performed by the presence / absence of a cycle, the calculation of the rank of the matrix, the evaluation of the weight distribution of the matrix, the distribution of Stopping Set, and the like.

(Decision Procedure 6) The determination procedures 5 and 6 are performed for all 286 candidates, and a candidate set (A1, A2, A3) that can generate a check matrix having an excellent correction capability is determined.

In the method of this embodiment in which a parity check matrix is generated using a numerical value A that is relatively prime to N, a certain level of correction capability can be obtained without performing the evaluation as in the decision procedure 5. Thus, by interposing evaluation, a particularly excellent check matrix can be selected.
Further, in the method of this embodiment in which a parity check matrix is generated using a numerical value A that is relatively prime to N, a large number of candidate sets (A1, A2, A3) are obtained by computer computation by following the above-described determination procedure. It can be generated automatically. Therefore, it is possible to evaluate a large number of candidates, and the numerical values (A1, A2, A3) determined through the evaluation can be expected to generate a check matrix with very excellent correction capability.

  In the above determination procedure, a prime number is selected as A (A1, A2, A3), but A may be a number that is a product of a plurality of prime numbers. It is not limited to prime numbers.

[Check matrix generation information]
According to the generation rule of the parity check matrix of the present embodiment, in order for the decoder 5 to generate a parity check matrix according to the generation rule, at least the numbers A1, A2, and A3 corresponding to the column weight wc are It only has to be generated information. Therefore, the decoder 5 stores a smaller number of numerical values A1, A2 and A3 even if it does not store information indicating the positions of all “1” included in the parity check matrix. By using the numerical values A1, A2, and A3, a check matrix can be dynamically generated by a generation unit (not shown) that executes.

In addition, in order for the decoder 5 to generate a parity check matrix according to the generation rule, in addition to the numerical values A1, A2, and A3, the code length of the parity check matrix (column length in the column direction of the parity check matrix) N is used as generation information of the parity check matrix. is necessary.
Further, in order to set “1” in the parity check matrix according to the generation rule, the number (row weight) wr of “1” included in one row is also necessary as the generation information of the parity check matrix. By using the information of the row weight wr, a plurality of parity check matrices corresponding to different coding rates can be generated.

Hereinafter, parameters related to the size of the parity check matrix such as N and parameters related to the number of “1” such as wr will be considered.
First, in the regular check matrix, the column direction length (code length) is N, the row direction length is M, the number of “1” per row (row weight) is wr, and the number of “1” per column. Let (column weight) be wc. The total number of “1” included in this check matrix is expressed as follows.
(Total number of 1) = wr × M = wc × N
From the above formula, M / N = wc / wr holds.

If the coding rate is R and the number of information symbols is K,
Coding rate R = K / N
= (NM) / N
= 1-M / N
= 1-wc / wr
It becomes.
In the above equation, M / N indicates the size of the parity check matrix, and wc / wr indicates the rate at which “1” is set.

Here, when it is assumed that the communication apparatus having the decoder 5 performs communication with the coding rate R and the code length N being fixed values, the decoder 5 acquires numerical values A1, A2, and A3. As a result, various check matrices can be generated (N and wr are known to the decoder 5).
That is, as described above, the decoder 5 acquires the numerical values A1, A2, and A3 stored in the storage unit (not shown) included in the decoder 5 (communication device) from the storage unit, and generates the data. A parity check matrix can be generated and decoded according to a rule. In this case, even when the decoder 5 stores a plurality of types of parity check matrices, the size of the memory for storing the parity check matrix can be reduced.
In particular, a standard (communication method) such as WiMAX requires that a plurality of different check matrices be used properly. In such a system, using the check matrix requires a memory for storing a plurality of check matrices. The merit in reducing is great.

  It is also possible to obtain numerical values A1, A2, and A3 from the outside of the decoder 5 (for example, receive from other decoders via a communication channel), generate a check matrix according to the generation rule, and perform decoding. In this case, by exchanging information on the check matrix between the decoders (communication devices) by communication, the check matrix can be changed during communication according to a communication status such as an error status. In addition, even if the parity check matrix information is sent to another decoding apparatus, the parity check matrix can be expressed with a small amount of information, so that an increase in communication load can be prevented.

On the other hand, when the communication apparatus having the decoder 5 changes the coding rate R according to the communication status, for example, when N or wc is a fixed value, according to the above equation, wr is the decoder (communication apparatus). ) Can be realized by communicating with each other. That is, the coding rate can be changed by changing wr. Then, the number of “1” per line is determined according to wr, and a check matrix may be generated.
That is, the decoder 5 (communication device) of the present embodiment determines wr according to the coding rate that varies according to the communication quality status (error status), and uses it to determine the other decoder 5 (communication device). The function to transmit to can be provided. The decoder 5 (communication device) that has received wr can generate a check matrix using the received wr in addition to the numerical value A.

[Relationship between coding rate R and row weight wr]
FIG. 10 is a diagram illustrating the relationship between the coding rate R and the row weight. First, if a number sequence indicating a column position of “1” included in the entire check matrix is referred to as a “basic number sequence”, the above-described check matrix H ₉₆ is the first connected number sequence generated by the numerical value A1. (Tolerance sequence A1) S, second connected number sequence generated by numerical value A2 (tolerance sequence A2 differential sequence) S, and third connected number sequence generated by numerical value A3 (tolerance is A3) An arithmetic sequence (S) is connected.

  Here, the number j of the connected number sequences S constituting the basic number sequence is equal to or greater than the column weight wc. That is, when the number of numbers included in the connected number sequence S is N, the number j of the connected number sequences S is equal to the column weight wc. When the number of numbers included in the connected number sequence S is less than N, the number j of the connected number sequences S is required to be larger than the column weight wc.

Then, as described above, connecting sequence S, S, S of the j, respectively, and a P-number of partial sequences _S 1 to S _P. Each partial sequence S ₁ to S _P corresponds to each row of the check matrix, since the number of rows check matrix to the total number P × j partial sequence is the same, the number of rows M of the check matrix becomes P × j .
Further, the number P of the partial sequence is equal to the number obtained by dividing the length N of the connected sequence by the length wr of one partial sequence. Therefore, M = N · j / wr.

Therefore, if the length (row weight; the number of “1” per row) wr of one partial sequence is changed, the number of rows M of the check matrix changes. That is, the number of rows (number of redundant bits) M can be changed without changing the number of columns (code length) N of the parity check matrix.
Here, since the coding rate R = 1−M / N, the coding rate R is changed by changing M.
As described above, in the present embodiment, check matrices having different coding rates are obtained by changing the row weights based on the common basic number sequence. Therefore, even if a plurality of parity check matrices corresponding to different coding rates are required, a common basic matrix can be used.

  The coding rate can be determined as shown in FIG. 12 using the column weight wc and the row weight wr. As shown in FIG. 12, when the column weight wc is 3, the coding rate R is 1/2, 2/3, 3/4, by setting the row weight wr to 6, 9, 12, 15. 4/5. In addition, when the column weight wc is 4, by setting the row weight wr to 8, 12, the coding rate becomes 1/2, 2/3.

  As described above, if the code length N and the column weight wc are determined, the coding rate R can be changed by changing the row weight wc. Of course, the coding rate can be changed by adjusting the code length N and the column weight wc.

If the concept of the basic number sequence is introduced, it can be said that the parity check matrix of the present embodiment has the following properties A to E.
(Property A) Each number sequence corresponding to the number of rows of the parity check matrix is a partial number sequence obtained by dividing a basic number sequence satisfying the following conditions (C) to (D) into wr numbers.
(Property B) Each number of partial sequences corresponding to the number of rows of the parity check matrix is assigned to one row of the parity check matrix.
(Property C) The numbers included in the basic number sequence are natural numbers of 1 to N.
(Property D) In the basic number sequence, the number of appearances of each of the natural numbers 1 to N is the same as the column weight value wc.
(Characteristic E) The basic number sequence is an X number of difference number sequences whose tolerance is any of A1,..., Aj (however, an arbitrary number y _A included in the number sequence and a number adjacent to the number y _A) Even if the difference from y _B may not be A, if the difference between y _A and (y _B + N) is A, the difference between y _A and y _B is considered to be A). is there.

  In the present embodiment, regarding the property B, a plurality of partial sequences are arranged so that the arrangement order of the plurality of partial sequences in the basic number sequence matches the arrangement order of each row of the parity check matrix to which the partial sequences are assigned. It is assigned to each row of the check matrix. However, the order of arrangement does not have to be the same as in the case where line replacement is performed as described above, and there is no difference in error correction capability even if line replacement is performed.

12 to 15 show a plurality of parity check matrices generated by changing the row weight wr from the common base matrix. 12 to 15, all have a code length N = 576, a column weight wc = 3 (= j), and numerical values (A1 to Aj) = (A1, A2, A3) = N that are relatively prime to N. (5, 61, 557). Since the basic number sequence is generated by the expression “mod (A × x, N) +1” using A1, A2, and A3, the basic number sequence is common in each check matrix of FIGS. Yes. Here, the initial value x ₁ to 0 x.

  The total number nz of “1” in the parity check matrix of FIG. 12 (code length N, row weight wr, numerical value A1, numerical value A2, numerical value A3) = (576, 6, 5, 61, 557) is 1728 (FIG. 13 to FIG. 13). The same applies to the parity check matrix in FIG. 14). The number of rows M is 288, and the coding rate R = 1−wc / wr = 1−3 / 6 = 1/2.

  As shown in the enlarged view of FIG. 12B, corresponding to the row weight wr being 6, six points (“1”) are arranged in one row.

  In the parity check matrix of FIG. 13 (code length N, row weight wr, numerical value A1, numerical value A2, numerical value A3) = (576, 9, 5, 61, 557), the number of rows M of “1” is 192, and encoding is performed. The rate R = 1−wc / wr = 1−3 / 9 = 2/3. As shown in the enlarged view of FIG. 13B, nine points (“1”) are arranged in one row corresponding to the row weight wr being nine.

    The number of rows M of “1” in the parity check matrix (code length N, row weight wr, numerical value A1, numerical value A2, numerical value A3) = (576, 12, 5, 61, 557) in FIG. The rate R = 1−wc / wr = 1−3 / 12 = 3/4. As shown in the enlarged view of FIG. 14B, in correspondence with the row weight wr being 12, twelve points (“1”) are arranged in one row.

    The number of rows M of “1” in the parity check matrix (code length N, row weight wr, numerical value A1, numerical value A2, numerical value A3) = (576, 16, 5, 61, 557) in FIG. The rate R = 1−wc / wr = 1−3 / 16 = 13/16. As shown in the enlarged view of FIG. 15B, 16 points (“1”) are arranged in one row corresponding to the row weight wr being 16.

  As described above, the check matrices in FIGS. 12 to 15 all have a common basic number sequence. In other words, it can be said that a set of numbers indicating the column positions of the non-zero elements included in the parity check matrix is common among the plurality of parity check matrices shown in FIGS. However, in the present embodiment, not only “the set of numbers indicating the column positions of the non-zero elements” is common, but also the basic number sequence obtained by concatenating the arithmetic sequence is common.

FIG. 16 shows BER (Bit Error Rate) characteristics when decoding is performed using the parity check matrix of FIGS. In FIG. 16, the BER characteristic when no error correction is performed is represented as “no correction” for reference.
As shown in FIG. 16, the check matrices in FIGS. 12 to 15 have a correction capability according to the coding rate R. Further, it is shown that the use of the parity check matrix of FIGS. 12 to 15 provides good characteristics without drawing an error floor.

[Decoder circuit configuration]
FIG. 17 shows a block diagram of the external value log ratio calculation unit 7 in the decoder 5 shown in FIG. In the case of the min-sum decoding method, the external value logarithmic ratio calculation unit 7 performs decoding by repeating the row processing of Equation (1) and the column processing of Equation (2). Therefore, the external value log ratio calculation unit 7 includes a row processing unit 7a that performs row processing and a column processing unit 7b that performs column processing, as shown in FIG.

Here, the row processing is roughly divided into an operation for determining a sign indicated by “sign” in Equation (1) and an operation for searching for the minimum value indicated by “min” in Equation (1). Since the code determination and the minimum value search are performed on λn + βmn, processing for adding λn and βmn is also necessary.
Therefore, as shown in FIG. 18, the row processing unit 7a includes an addition unit 7a-1 that performs addition of λn and βmn, a code processing unit 7a-2 that performs a sing operation of Expression (1), and a minimum of Expression (1). A minimum value search unit 7a for performing a value search is provided. Then, the results of the code processing unit 7a-2 and the minimum value search unit 7a-3 are multiplied by the code multiplication unit 7a-4, and αmn shown in Expression (1) is obtained.

FIG. 19 shows a circuit configuration of the minimum value search unit 7a-3 when the row weight wr = 6 (check matrix in FIG. 12), and FIG. 20 shows the minimum when the row weight wr = 9 (check matrix in FIG. 13). The circuit structure of the value search part 7a-3 is shown. The minimum value search unit here employs a tournament method in order to obtain the minimum value of λn + βmn in a certain row m. That is, the minimum value is obtained by providing a plurality of comparators 200 that output a smaller value of the two values and sequentially performing the comparison. In Formula (1), since it is the minimum value for the elements other than itself, in practice, the minimum value search unit for calculating the minimum value of λn ′ + βmn ′ excluding the element itself is used. Is not entered. For example, in the minimum value search for obtaining the element α ₁₁ in the first row and the first column, the corresponding (λ ₁ + β ₁₁ ) is excluded from the input to the minimum value search unit, and is included in the other elements in the first row. The minimum value is searched from.

In the minimum value search unit 7a-3 of FIGS. 19 and 20, processing circuits 300 and 301 for obtaining the minimum value for each row are provided, and the minimum value search processing is performed by the number of non-zero elements per row. Is repeated. Each processing circuit 300, 301 is provided with a comparator 200 having the number of non-zero elements per row (row weight) -1 of the check matrix, and performing a tournament-type operation for obtaining a minimum value for each row. Is done.
Accordingly, in FIGS. 19 and 20, the number of comparators 200 in each processing circuit 300, 301 is different, and the total number of processing circuits 300, 301 is also different. That is, in FIG. 19 and FIG. 20, the circuit configuration of the minimum value search unit 7a-3 is different.

  However, as shown in FIGS. 19 and 20, the input contents to the minimum value search unit 7a-3 are common as a whole. That is, in this embodiment, the basic number sequence indicating the column position of the non-zero element is common among the plurality of parity check matrices, and thus λn + βmn is also common (aside from the row position m). In FIG. 19 and FIG. 20, the only difference is in which row m of processing circuit 300 each λn + βmn is given.

  Accordingly, in the circuits of FIG. 19 and FIG. 20, the configuration of the minimum value search unit 7a-3 itself, and which row of processing circuit 300 each λn + βmn is assigned to (what m of βmn) is, Although different, it is possible to share the adder 7a-1 that performs the calculation of λn + βmn. As a result, an increase in circuit scale can be suppressed.

FIG. 21 shows another example of the minimum value search unit 7a-3. FIG. 21 shows a common minimum value search unit 7a-3 for a parity check matrix having different row weights. Here, the processing circuit 302 for searching for the minimum value is provided not in units of rows but in units of least common multiples of a plurality of row weights. For example, in the case where the row weight = 6 as shown in FIG. 19 and the row weight = 9 as shown in FIG. 20, in order to make both common, 18 inputs (λn) which are the least common multiples of 6 and 9 are used. A circuit for obtaining the minimum value from “+ βmn”) may be a single processing circuit 302. Actually, since its own elements are removed, in the actual calculation using the processing circuit 302, the minimum value is obtained from 17 inputs.

A comparator 200 indicated by a solid line in FIG. 21 is used to obtain the minimum value of each row (for three rows) when the row weight is 6. In FIG. 21, a comparator 200 indicated by a dotted line is used to obtain a minimum value for each row (for two rows) in the case of row weight 9 by partially using the comparison result in the case of row weight 6. is there.
Since the processing circuit 302 in FIG. 21 can output outputs for a plurality of row weights, it is not necessary to provide the processing circuit 302 for each row weight. Moreover, since the comparator 200 is shared between different row weights, an increase in the number of elements is suppressed.

  In the minimum value search unit 7a-3 of FIG. 21, a selector 304 for selecting and outputting an output (minimum value) for the selected row weight from the output of each row weight output from the processing circuit 302. Is provided. The selector can determine which minimum value to output according to the selected row weight information wr. The row weight is determined according to the communication rate of the communication device.

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof. For example, the processing (row processing or column processing) based on the check matrix of this embodiment is hardware. It is not necessary to be executed by hardware, and may be executed by a computer program. Further, the basic number sequence is not limited to the concatenation of the arithmetic number sequences, and may be any number sequence. Further, the processing circuit for obtaining the minimum value is not limited to the tournament method, and may be a method based on a distribution counting sort. A method based on the distribution counting sort is, for example, “Takae Mae,“ Implementation of LDPC decoder by FUMP-APP decoding method ”, IEICE, IEICE Technical Report, CAS 2006, pp. 8-20 June 2006 ".

DESCRIPTION OF SYMBOLS 1 Encoder 2 Modulator 3 Communication path 4 Demodulator 5 Decoder H Check matrix N Code length wc Column weight wr Row weight R Coding rate

Claims (1)

A decoding apparatus capable of properly using a plurality of low density parity check codes having different coding rates,
A plurality of parity check matrices corresponding to the plurality of low density parity check codes are:
The code length of the low density parity check code and the column weight of the check matrix are common,
A set of numbers indicating column positions of non-zero elements included in the check matrix is common among the plurality of check matrices,
What is claimed is: 1. A decoding apparatus comprising: a plurality of parity check matrixes having different coding rates due to different row weights among the plurality of parity check matrices.