JP2011071722A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform envelope detection while achieving a differential output. <P>SOLUTION: This semiconductor integrated circuit device inputs a differential signal, the gain of which is adjusted so as not to negate beat components of the differential signal to the gates of field effect transistors M1 and M2 while driving the sources of the field effect transistors M1 and M2 with a signal having the same frequency component as that of a differential signal having two or more frequency components. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and is particularly suitable for application to an envelope detector capable of performing differential input / output and a transmitter using the same.

  In the field of wireless LAN and the like, there is a method using orthogonal modulation as a modulation method in order to increase transmission efficiency. In this orthogonal modulation system, it is inevitable that an orthogonal error occurs between the I channel and the Q channel due to mismatch between elements, and transmission performance may deteriorate. Here, when an orthogonal error occurs, an image component and a carrier leak (local leak) component which are unnecessary spurious are output. For this reason, the magnitude of the image component and the carrier leak component with respect to a desired signal component may be monitored by envelope detection, and feedback control may be performed so that these components become small (Non-Patent Document 1).

  Here, as a method for performing such envelope detection, there is a method in which a differential signal is input to a pair of transistors, and an envelope is extracted using the second-order nonlinearity of the transistors (Patent Document 1). ).

C. P. Lee et al. , “A High Linear Direct-Conversion Transmission Mixer Transconductance Stage with Local Oscillation Feedthrough and I / Q Immobilization Scheme SPE”. 1450-1459, 2006.

USP7336129

  However, in the method disclosed in Patent Document 1, the output is a single-phase signal even though the differential signal is input to the detector. For this reason, there is a problem in that various noises are superimposed during transmission of the output signal from the detector, and noise resistance is reduced.

  An object of the present invention is to provide a semiconductor integrated circuit device capable of performing envelope detection while realizing differential output.

  According to one embodiment of the present invention, a first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, and a first output signal that outputs a first output signal. A first nonlinear circuit having a first output terminal; third and fourth input terminals to which the second input signal is input; and a second output that is a differential signal of the first output signal. A semiconductor integrated circuit device comprising: a second nonlinear circuit having a second output terminal for outputting a signal; and a bias circuit for supplying a bias voltage to the first and second nonlinear circuits. .

According to one aspect of the present invention, a first input terminal to which a first input signal is input via an amplifier, a second input terminal to which a second input signal is input, and a first output signal A first non-linear circuit having a first output terminal for outputting the second input signal, a third input terminal to which the second input signal is input via an amplifier, and a second input signal to which the second input signal is input. A second non-linear circuit having four input terminals and a second output terminal that outputs a second output signal that is a differential signal of the first output signal;
A semiconductor integrated circuit device comprising: a bias circuit that supplies a bias voltage to the first and second nonlinear circuits.

  According to the present invention, it is possible to perform envelope detection while realizing differential output.

FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 3 is a diagram showing an equivalent circuit for a low frequency signal of the semiconductor integrated circuit device of FIG. FIG. 4 is a diagram showing a small-signal equivalent circuit for a single phase of the circuit of FIG. FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention. 6 is a diagram showing an equivalent circuit for a low-frequency signal in the semiconductor integrated circuit device of FIG. FIG. 7 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. FIG. 8 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 9 is a block diagram showing a schematic configuration of a transmitter according to the sixth embodiment of the present invention. 10 is a diagram showing a spectrum component of an output signal output from the transmitter of FIG. FIG. 11 is a block diagram showing a schematic configuration of a transmitter according to the seventh embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a schematic configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention.
This semiconductor integrated circuit device is provided with field effect transistors (hereinafter referred to as transistors) M1 and M2, amplifiers Z1 and Z2, and a bias circuit as nonlinear circuits. The transistors M1 and M2 are the same conductivity type transistors. Here, a transistor is used as the nonlinear circuit, but the nonlinear circuit may be an element or a circuit having a second-order nonlinearity. The bias circuit includes resistors R1 and R2, and supplies the bias voltage Vb to the nonlinear circuit via the resistors R1 and R2. The amplifier Z1 is connected to the gate (first input terminal) of the transistor M1 (first nonlinear circuit), and the amplifier Z2 is connected to the gate (third input terminal) of the transistor M2 (second nonlinear circuit). Has been. The drains of the transistors M1 and M2 are connected in common via resistors R1 and R2, respectively.

  A bias voltage Vb is supplied to the drains of the transistors M1 and M2 via the resistors R1 and R2, respectively. The sources (second and fourth input terminals) of the transistors M1 and M2 are driven by the input signal Vip. An input signal Vin (first input signal) is input to the amplifier Z1, and an input signal Vip (second input signal) is input to the amplifier Z2. An output signal Vop (first output signal) is output from the drain (first output terminal) of the transistor M1, and an output signal Von (second output signal) is output from the drain (second output terminal) of the transistor M2. Is done.

  Note that differential signals having two or more frequency components can be used as the input signals Vin and Vip. For example, Vin is a signal obtained by adding the input signal 1 having the frequency 1 and the input signal 2 having the frequency 2, and Vip is obtained by adding the signal 3 obtained by inverting the polarity of the input signal 1 and the signal 4 obtained by inverting the polarity of the input signal 2. A signal can be used. The amplification factors of the amplifiers Z1 and Z2 are set so that the beat components of the input signals Vin and Vip are not canceled from the frequency components of the output signals Vop and Von. Here, -A (A is a real number other than 1) is set.

  Input signals Vin and Vip are multiplied by −A by amplifiers Z1 and Z2, respectively, and input to the gates of transistors M1 and M2. When the transistors M1 and M2 operate as passive mixers (multipliers), they are multiplied by the input signal Vip input to the sources of the transistors M1 and M2, and the output signals Vop and Von are differential signals from the drains of the transistors M1 and M2. Is output as

  For example, for the sake of simplicity, if the input signals Vin and Vip are differential signals having two frequency components, the input signal Vip is expressed by the following equation (1), and the input signal Vin is expressed by the following equation (2). be able to.

Here, ω _c + ω _b is the frequency of the signal component, ω _c is the frequency of the carrier leak component, α is the amplitude of the signal component, and β is the amplitude of the carrier leak component. K is a second-order nonlinear coefficient of the transistors M1 and M2.

  In this case, the drain current ip of the transistor M1 can be expressed by the following formula (3), and the relationship between the drain current ip of the transistor M1 and the drain current in of the transistor M2 can be expressed by the following formula (4).

  As can be seen from the equations (3) and (4), the drain currents ip and in have a differential relationship. Therefore, the output signals Vop and Von output from the drains of the transistors M1 and M2 are differential signals.

(3) In the equation, for example, a frequency ω _{c +} ω _b and frequency omega _c of the carrier leak component of the signal component and a high frequency of several GHz. The first, second, and third terms on the right side of equation (3) are high-frequency components (for example, 2.4 GHz or more). Therefore, assuming that the cutoff frequency of the transistors M1 and M2 is about several tens of MHz, the components of the first to third terms on the right side of the equation (3) are not output due to the low-pass filter characteristics of the transistors M1 and M2.

The fourth term on the right side of the equation (3) is a beat component between the signal component and the carrier leak component. For example, if the frequency ω _c + ω _{b of} the signal component is 2.501 GHz and the frequency ω _c of the carrier leak component is 2.5 GHz, the frequency ω _{b of the} beat component is 1 MHz. The fifth term on the right side of the equation (3) is a direct current component, and can be removed by, for example, a high pass filter having a cutoff frequency of about 100 kHz.

  Therefore, by extracting the output signals Vop and Von from the drains of the transistors M1 and M2, the beat component between the signal component and the carrier leak component can be extracted as a differential signal, and the carrier can be realized while realizing the differential output. The leak component can be detected by envelope detection.

  In the above-described embodiment, the method of driving the sources of the transistors M1 and M2 with the input signal Vip has been described. However, the signals for driving the sources of the transistors M1 and M2 have the same frequency components as the input signals Vin and Vip. For example, the sources of the transistors M1 and M2 may be driven by the input signal Vin, or may be driven by the signal Vin-Vip. It may be driven by a signal called Vip-Vin, or a signal obtained by multiplying such a signal by a gain may be used.

(Second Embodiment)
FIG. 2 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention.
This semiconductor integrated circuit device is provided with capacitors C1 and C2 in addition to the configuration of FIG. The capacitors C1 and C2 are connected to the sources of the transistors M1 and M2, respectively. The sources of the transistors M1 and M2 are driven by the input signal Vip through capacitors C1 and C2, respectively.

Here, when the frequency ω _{c +} ω _b and frequency omega _c of the carrier leak component of the signal component and a high frequency of several GHz, the capacitor C1, C2 is the high frequency it appears to be short-circuited. For this reason, the circuit of FIG. 2 is equivalent to the circuit of FIG. 1 in terms of high frequency, and can operate in the same manner as the circuit of FIG. In this case, the transistors M1 and M2 serve as current sources that output a low frequency component of about several MHz or less.

FIG. 3 is a diagram showing an equivalent circuit for the low frequency signal of the semiconductor integrated circuit device of FIG.
In this equivalent circuit, the transistor M1 in FIG. 2 is replaced with a parallel circuit of the current source I1 and the output impedance Rs1 of the current source I1, and the transistor M2 of FIG. 2 is in parallel with the output impedance Rs2 of the current source I2 and the current source I2. It has been replaced with a circuit. In the equivalent circuit for the low-frequency signal in FIG. 3, the capacitors C1 and C2 do not appear to be short-circuited, and thus the capacitors C1 and C2 are not omitted.

FIG. 4 is a diagram showing a small signal equivalent circuit for a single phase of the circuit of FIG.
In the equivalent circuit of FIG. 4, a current source I0 and an output impedance Rs0 are connected in parallel, a capacitor C0 is connected in series to this parallel circuit, and a resistor R0 is connected in parallel to this series circuit. The output signal Vo of this circuit can be expressed by the following equation (5).

Incidentally, i is the current flowing through the current source I0, _{R s} is the value of the output impedance Rs0, C is the capacitance value of the capacitor C0, R is the resistance of the resistor R0.

As can be seen from the equation (5), the current i output from the current source I0 flows into the resistor R0 and the output impedance Rs0, and passes through a high-pass filter having a time constant of (R + R _s ) C. Therefore, in the configuration of FIG. 2, it appears that the high-pass filter is built in the semiconductor integrated circuit device. For this reason, even when the direct current component of the fifth term on the right side of the equation (3) is generated, the direct current component of the fifth term on the right side of the equation (3) is not output, and the output direct current of this semiconductor integrated circuit device. The component can be uniquely determined by the bias voltage Vb through the resistors R1 and R2.

  As a result, the function of the high-pass filter can be built into the semiconductor integrated circuit device of the present invention, and the output signals Vop and Von in FIG. For this reason, it is possible to prevent the DC level of the output signals Vop and Von from fluctuating depending on the amplitude of the signal component and the amplitude of the carrier leak component. Furthermore, even when the amplifier is directly connected to the subsequent stage of the semiconductor integrated circuit device of the present invention, it is possible to prevent the amplifier from malfunctioning.

(Third embodiment)
FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention.
This semiconductor integrated circuit device is provided with a capacitor C3 in addition to the configuration of FIG. Here, the capacitor C3 is connected between the sources of the transistors M1 and M2.

  Here, since the capacitor C3 is inserted in the same phase with respect to the input signal Vip, it does not act on the high frequency signal, but seems to be inserted between the differentials for the low frequency signal. Looks like.

FIG. 6 is a diagram showing an equivalent circuit for the low frequency signal of the semiconductor integrated circuit device of FIG.
In this equivalent circuit, a capacitor C3 is provided in addition to the configuration of FIG. The capacitor C3 is connected between connection points of the current sources I1 and T2 and the capacitors C1 and C2.

ただし、Ｃ_０は図４のコンデンサＣ０の容量値、Ｃ_３は図６のコンデンサＣ３の容量値である。 When the equivalent circuit of FIG. 6 is replaced with a single-phase small signal equivalent circuit, the output signal Vo of this circuit can be expressed by the following equation (6).

However, _{C 0} is the capacitance value, _{C 3} of the capacitor C0 in FIG. 4 is the capacitance value of the capacitor C3 of FIG.

As can be seen from this equation (6), by connecting the capacitor C3 between the sources of the transistors M1 and M2, the time constant of the high-pass filter built in the semiconductor integrated circuit device can be increased, and the high-pass filter Efficiency can be improved. For example, if C ₀ = C / 2 (where C is the capacitance value of the capacitors C1 and C2 in FIG. 2) and C ₃ = C, the total capacity is the same in the configuration of FIG. 2 and the configuration of FIG. Become. On the other hand, the time constant of the high-pass filter built in this semiconductor integrated circuit device is (R + R _s ) C in the configuration of FIG. 2, and 2.5 (R + R _s ) C in the configuration of FIG. However, the time constant of the high-pass filter becomes large. In this case, the efficiency of the high-pass filter can be further improved by increasing the ratio of the capacitor C3 to the capacitors C1 and C2.

(Fourth embodiment)
FIG. 7 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention.
This semiconductor integrated circuit device is provided with transistors M11 to M14 as non-linear circuits, amplifiers Z11 to Z14, capacitors C11 to C14, and a bias circuit. Here, as in the first embodiment, a transistor is used as the nonlinear circuit, but the nonlinear circuit may be an element or circuit having a second-order nonlinearity. The bias circuit includes resistors R1 and R2, and supplies a bias voltage Vb to each nonlinear circuit via the resistor R1 or R2. Amplifiers Z11 to Z14 are connected to gates (first, third, fifth, and seventh input terminals) of the transistors M11 to M14 (first to fourth nonlinear circuits), respectively. The drains of the transistors M11 and M14 are commonly connected via a resistor R11, and the drains of the transistors M12 and M13 are commonly connected via a resistor R12. The capacitors C11 to C14 are connected to the sources of the transistors M11 to M14, respectively.

  A bias voltage Vb is supplied to the drains of the transistors M11 and M14 via the resistor R11, and a bias voltage Vb is supplied to the drains of the transistors M12 and M13 via the resistor R12. The source of the transistor M11 (second input terminal) and the source of the transistor M12 (fourth input terminal) are driven by the input signal Vip through the capacitors C11 and C12, respectively, and the source of the transistor M13 (sixth input terminal). The input terminal) and the source (eighth input terminal) of the transistor M14 are driven by the input signal Vin through capacitors C13 and C14, respectively. In addition, the input signal Vin is input to the amplifiers Z11 and Z13, and the input signal Vip is input to the amplifiers Z12 and Z14. An output signal Vop is output from the drains (first output terminal) of the transistors M11 and M14, and an output signal Von is output from the drains (second output terminal) of the transistors M12 and M13.

  When the input signals Vin and Vip are input, the amplifiers Z11 to Z14 respectively multiply the signals by −A. The -A multiplied input signal Vin is input to the gates of the transistors M11 and M13, and the -A multiplied input signal Vip is input to the gates of the transistors M12 and M14.

  In the transistor M11, the input signal Vin multiplied by −A is multiplied by the input signal Vip inputted. In the transistor M14, the input signal Vip multiplied by −A is multiplied by the input signal Vin. Output as an output signal Vop. The transistor M12 multiplies the input signal Vip multiplied by -A by the input signal Vip inputted, and the transistor M13 multiplies the input signal Vin multiplied by -A by the input signal Vin. Output as an output signal Von. The output signals Vop and Von can constitute a differential signal.

  As a result, the input of the semiconductor integrated circuit device of the present invention can have a differential configuration, and the output level from the semiconductor integrated circuit device can be doubled. Further, the input / output balance by the differential configuration can be balanced, and the noise tolerance can be improved.

  Note that although the method of connecting the capacitors C11 to C14 to the sources of the transistors M11 to M14 has been described in the embodiment of FIG. 7, as an aspect of the present invention, the capacitors C11 to C14 are respectively connected to the sources of the transistors M11 to M14. You may make it use the structure which is not connected.

(Fifth embodiment)
FIG. 8 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.
This semiconductor integrated circuit device is provided with capacitors C15 and C16 in addition to the configuration of FIG. The capacitor C15 is connected between the sources of the transistors M11 and M12, and the capacitor C16 is connected between the sources of the transistors M13 and M14.

  As a result, the input of the semiconductor integrated circuit device of the present invention can have a differential configuration, and the output level from the semiconductor integrated circuit device can be doubled. Input / output can be balanced, and noise tolerance can be improved. Further, by adding capacitors C15 and C16, the efficiency of the high-pass filter built in the semiconductor integrated circuit device of FIG. 8 can be doubled compared to the configuration of FIG. 5, and the efficiency of the high-pass filter is further increased. Can be improved.

(Sixth embodiment)
FIG. 9 is a block diagram showing a schematic configuration of a transmitter according to the sixth embodiment of the present invention.
In this transmitter, mixers 18 and 19, a local oscillator 16 and a frequency divider 17 are provided. The mixers 18 and 19 up-convert the transmission signal. The inputs of the mixers 18 and 19 are connected to the low-pass filters 14 and 15, respectively, and the outputs of the mixers 18 and 19 are commonly connected to the antenna via the power amplifier 20. The local oscillator 16 generates a local oscillation signal, and the frequency divider 17 divides the local oscillation signal by two.

  Further, the transmitter is provided with a detector 21, an AD converter 22, a beat component detection unit 23, an IQ balance adjustment unit 13, a DA converter 11, and a DA converter 12. The detector 21 performs envelope detection, and the AD converter 22 digitizes the output of the detector 21. The beat component detector 23 detects a beat component based on the envelope detection result. The IQ balance adjustment unit 13 adjusts the balance between the in-phase component BI and the quadrature component BQ of the baseband signal so that the detected beat component is reduced. The DA converters 11 and 12 convert the in-phase component BI and the quadrature component BQ of the baseband signal into analog signals, respectively.

  In addition, as the detector 21, the structure of 2nd-5th embodiment can be used, for example. The beat component detector 23 detects the strength of the envelope detected by the detector 21. The IQ balance adjustment unit 13 adjusts the magnitude or phase of the in-phase component BI and the quadrature component BQ of the baseband signal so that the intensity of the envelope detected by the beat component detection unit 23 decreases. Or Further, the in-phase component BI and the quadrature component BQ of the baseband signal, the input / output of the mixers 14 and 15, the input / output of the power amplifier 20, and the input / output of the detector 21 can be configured to be differential.

  The in-phase component BI and the quadrature component BQ of the baseband signal are converted into analog signals by the DA converters 11 and 12, respectively, and then the balance is adjusted by the IQ balance adjustment unit 13 and input to the low-pass filters 14 and 15, respectively. Then, after unnecessary high frequency components are removed by the low-pass filters 14 and 15, they are input to the mixers 18 and 19, respectively. Note that the IQ balance adjustment unit can be arranged in front of the DA converter, and the IQ balance can be adjusted in the digital domain.

  The local oscillation signal generated by the local oscillator 16 is divided by two by the frequency divider 17 and input to the mixers 18 and 19, respectively. When the mixers 18 and 19 have a differential configuration, the local oscillator 16 generates local oscillation signals for four phases having the same frequency and phases shifted from each other by 90 °.

  The in-phase component BI and the quadrature component BQ of the baseband signal are up-converted by being mixed with the local oscillation signal by the mixers 18 and 19, respectively, amplified by the power amplifier 20, and then spatially transmitted through the antenna. And input to the detector 21.

  The output signal of the power amplifier 20 is subjected to envelope detection by the detector 21, digitized by the AD converter 22, and then input to the beat component detection unit 23. The beat component detection unit 23 detects the intensity of the detected envelope, thereby detecting the beat component included in the output of the power amplifier 20 and sending the detection result to the IQ balance adjustment unit 13. The IQ balance adjustment unit 13 adjusts the balance between the in-phase component BI and the quadrature component BQ of the baseband signal so that the detected beat component is reduced. As a result, unnecessary spurious image components are reduced. Similarly, for the differential DC offset of each of the in-phase component and the quadrature component, the differential DC offset adjustment unit is arranged at the same location as the IQ balance adjustment unit to adjust the differential DC offset. Carrier leak components can be reduced. The differential DC offset adjustment unit can be arranged before the DA converter, and the differential DC offset can be adjusted in the digital domain.

FIG. 10 is a diagram illustrating a spectrum component of an output signal output from the transmitter of FIG.
In FIG. 10, when an orthogonal error occurs between the I channel and the Q channel due to mismatch between elements, the image component S3 or the carrier leak component S2 is superimposed on the signal component S1. For this reason, as shown in FIG. 9, even when the signal component S1 has a single frequency, the power amplifier 20 outputs a differential signal S4 having two or more frequency components and generates a beat component. For example, assuming that the frequency of the signal component S1 is 2.501 GHz, the frequency of the carrier leak component S2 is 2.5 GHz, and the differential signal S4 is composed of the signal component S1 and the carrier leak component S2, 1 MHz Beat component is generated. Then, by detecting the envelope Sh corresponding to the beat component by the detector 21, it is possible to determine whether or not the carrier leak component S2 is included in the differential signal S4.

  Even if the signal transmission distance between the detector 21 and the AD converter 22 is long, the detector 21 extracts the beat component between the signal component S1 and the carrier leak component S2 as a differential signal. Resistance can be improved, and erroneous detection can be suppressed.

  Further, by using the configurations of the second to fifth embodiments as the detector 21, it is possible to prevent the output of the detector 21 from including a DC component, and when an amplifier is directly connected to the subsequent stage of the detector 21. In this case, it is possible to prevent the amplifier from malfunctioning.

(Seventh embodiment)
FIG. 11 is a block diagram showing a schematic configuration of a transmitter according to the seventh embodiment of the present invention.
This transmitter is provided with a high-pass filter 24 and an amplifier 25 in addition to the configuration shown in FIG. 9, and a detector 26 is provided instead of the detector 21. As the detector 26, for example, the configuration of FIG. 1 can be used. An amplifier 25 is connected to the subsequent stage of the detector 26 via a high pass filter 24. Note that the cutoff frequency of the high-pass filter 24 can be set to about 100 kHz.

  The high pass filter 24 includes a resistor R21 and a capacitor C21. The capacitor C21 is connected between the detector 26 and the amplifier 25. The resistor R21 is connected between the connection point of the amplifier 25 and the capacitor C21 and the bias voltage Vb.

  The DC component of the signal detected by the detector 26 is attenuated by the high pass filter 24 and then input to the amplifier 25. Then, the detected differential envelope signal is amplified by the amplifier 25 and then input to the AD converter 22.

  Thereby, even when the detected signal includes a direct current component, the differential envelope signal detected by the detector 26 can be amplified while preventing the amplifier 25 from malfunctioning.

  In addition, although embodiment mentioned above demonstrated the case where amplifier Z1, Z2, Z11-Z14 was provided, amplifier Z1, Z2, Z11-Z14 may not be.

  M1, M2, M11 to M14 field effect transistors, Z1, Z2, Z11 to Z14, 25 amplifiers, R0 to R2, R11, R12, R21 resistors, C0 to C3, C11 to C16, C21 capacitors, I0 to I2 current sources, Rs0 to Rs2 Output impedance, 11, 12 DA converter, 13 IQ balance adjustment unit, 14, 15 Low pass filter, 16 Local oscillator, 172 Frequency divider, 18, 19 Mixer, 20 Power amplifier, 21, 26 Detector, 22 AD Converter, 23 beat component detector, 24 high-pass filter

Claims (6)

A first input terminal that receives a first input signal, a second input terminal that receives a second input signal, and a first output terminal that outputs a first output signal. A nonlinear circuit of
A second input terminal having third and fourth input terminals to which the second input signal is input, and a second output terminal for outputting a second output signal that is a differential signal of the first output signal. A nonlinear circuit of
A semiconductor integrated circuit device comprising: a bias circuit that supplies a bias voltage to the first and second nonlinear circuits. A first input terminal to which a first input signal is input via an amplifier; a second input terminal to which a second input signal is input; and a first output terminal for outputting a first output signal; A first non-linear circuit having
A third input terminal to which the second input signal is input via an amplifier, a fourth input terminal to which the second input signal is input, and a differential signal of the first output signal. A second non-linear circuit having a second output terminal for outputting a second output signal;
A semiconductor integrated circuit device comprising: a bias circuit that supplies a bias voltage to the first and second nonlinear circuits. A first capacitor having one end input with the second input signal and the other end connected with the second input terminal;
3. The semiconductor integrated circuit device according to claim 1, further comprising: a second capacitor having one end input to the second input signal and the other end connected to the fourth input terminal. 4. .   4. The semiconductor integrated circuit device according to claim 3, further comprising a third capacitor connected between the second input terminal and the fourth input terminal. A third nonlinear circuit having fifth and sixth input terminals to which the first input signal is input and connected to the second output terminal;
A fourth input terminal connected to the first output terminal and having a seventh input terminal to which the second input signal is input and an eighth input terminal to which the first input signal is input; A nonlinear circuit;
A fourth capacitor in which a first input signal is input to one end and the sixth input terminal is connected to the other end;
A fifth capacitor in which a first input signal is input to one end and the eighth input terminal is connected to the other end;
The semiconductor integrated circuit device according to claim 4, further comprising a sixth capacitor connected between the sixth input terminal and the eighth input terminal.   6. The semiconductor integrated circuit device according to claim 1, wherein the first and second input signals are differential signals having two or more identical frequency components.

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