JP2011019156A - Chopper amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chopper amplifier that suppresses spurious.SOLUTION: The chopper amplifier includes a first chopper circuit which multiplies an input signal with a chopping signal, an operational amplifier which amplifies an output of the first chopper circuit, and a second chopper circuit which multiplies the output of the operational amplifier with the chopping signal and outputs an output signal. It further includes a pseudo random signal generating circuit which generates a pseudo random signal that varies its pulse width at random, and a multiplier which multiplies the pseudo random signal with a first signal which has a first frequency (f1) that is either a second frequency (f2) in which a frequency spectrum of the pseudo random signal becomes null or a sum frequency (f2+fin) of the second frequency (f2) and input signal frequency (fin), for outputting a chopping signal. Thus, noise level at low frequencies region in the output signal can be lowered.

Description

  The present invention relates to a chopper amplifier.

  The chopper amplifier is an operational amplifier used for amplifying a weak signal from DC to low frequency. An operational amplifier which is an operational amplifier is known to have flicker noise (1 / f noise) as noise caused by traps in the gate oxide film of the MOS transistor when it is configured using a MOS transistor. In addition, an operational amplifier is also known for output voltage offset voltage caused by variations in characteristics such as mutual conductance gm of transistor pairs constituting the operational amplifier and variations in resistance values of load resistors.

  The chopper amplifier is an operational amplifier that can remove such flicker noise and offset voltage. The chopper amplifier up-converts an input signal to a predetermined frequency by a preceding chopper circuit, amplifies it by an operational amplifier, and then down-converts the input signal at the same predetermined frequency by a subsequent chopper circuit. Thereby, the noise component generated in the operational amplifier is shifted to a high frequency band. By passing the output through a low pass filter (LPF), noise components in the high frequency band can be removed.

  The chopper amplifier is described in, for example, Non-Patent Document 1 and Patent Documents 1 to 5.

  The chopper amplifier up-converts flicker noise and output offset voltage as described above, but it is not always easy to sufficiently remove these high-frequency noises with the LPF connected in the subsequent stage, and a steep filter such as a high-order LPF Characteristics may be required. However, such a filter increases the cost of the system because of its large circuit scale and large power consumption.

  A clock signal is generally used as the chopping signal having a predetermined frequency supplied to the chopper circuit. If the duty ratio of the chopping signal deviates from 50%, the DC offset component of the chopping signal unbalances the operation of the chopper circuit. Furthermore, the operation of the chopping circuit is unbalanced due to manufacturing variations of the transistors constituting the chopping circuit. Such an unbalanced operation causes a DC offset leak in the output signal.

Special Table 2009-502057 (P2009-502057A) Gazette Special Table 2008-527915 (P2008-527915A) Gazette JP-A-5-175787 JP-A-6-244732 Special Table 2002-530916 (P2002-530916A)

P. Godoy and J. L. Dawson, “Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 10, pp. 2311-2321, Oct. 2008.

  As a method for removing the spurious of the chopper amplifier, it has been proposed to use a random signal as the chopping signal to disperse the spurious frequency (Non-patent Document 1, Patent Document 1, 2, etc.). However, unless the frequency characteristics of the random signal are made spectral null (low power or zero) in the low frequency band of the input signal, spurious noise that is frequency-distributed remains in the frequency band of the output signal. However, it is not always easy to generate a spectrum null random signal in the low frequency band of the input signal, except in the case of high cost.

  Accordingly, an object of the present invention is to provide a chopper amplifier capable of suppressing spurious.

  The first aspect of the chopper amplifier includes a first chopper circuit that multiplies an input signal by a chopping signal, an operational amplifier that amplifies the output of the first chopper circuit, and an output of the operational amplifier multiplied by the chopping signal. A second chopper circuit for outputting a signal, a pseudo random signal generating circuit for generating a pseudo random signal whose pulse width changes randomly, a second frequency (f2) at which the frequency spectrum of the pseudo random signal is null, Alternatively, a first signal having a first frequency (f1) that is one of the sum frequency (f2 + fin) of the second frequency (f2) and the frequency (fin) of the input signal is defined as the pseudo-random signal. And a multiplier for outputting the chopping signal.

  According to the first aspect, spurious can be suppressed from the output signal of the chopper amplifier.

It is a figure explaining a structure and operation | movement of a chopper amplifier. It is a figure which shows the equivalent circuit of a chopper amplifier, and the frequency spectrum of an output signal. It is a figure which shows the chopping imbalance of a chopper amplifier. It is a figure which shows the frequency spectrum of an output signal at the time of using a random signal for a chopping signal. 1 is a circuit diagram of a chopper amplifier in a first embodiment. FIG. It is a specific circuit diagram of the chopper amplifier in the first embodiment. 3 is a diagram illustrating an example of an input signal and an output signal of an exclusive OR circuit 24. FIG. It is a circuit diagram of a chopper amplifier in a second embodiment. It is a circuit diagram of another chopper amplifier in a 2nd embodiment. It is a figure which shows the DC voltage of the random signal and chopping signal in a random chopping signal generation circuit. It is a figure explaining the calibration process in the chopper amplifier of FIG. 8, FIG. FIG. 6 is a circuit diagram of a chopper amplifier according to a third embodiment. 1 is a circuit diagram of a first order delta-sigma modulator. FIG. It is a figure which shows the frequency spectrum of the chopper amplifier output at the time of using a pseudo random number bit sequence generator for a pseudo random signal generation circuit. It is a figure which shows the frequency spectrum of the chopper amplifier output at the time of using a pseudo random number bit sequence generator for a pseudo random signal generation circuit. It is a figure which shows the frequency spectrum of the chopper amplifier output at the time of using a primary delta-sigma modulator for a pseudorandom signal generation circuit. It is a figure which shows the frequency spectrum of the chopper amplifier output at the time of using a primary delta-sigma modulator for a pseudorandom signal generation circuit.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  FIG. 1 is a diagram for explaining the configuration and operation of a chopper amplifier. This chopper amplifier chops a differential input signal Vin +, Vin- with a chopping signal fc, a preceding chopper circuit CHP1, an operational amplifier AMP that amplifies the chopped signal, and an operational amplifier output Vamp +, Vamp-. And a subsequent chopper circuit CHP2 that performs chopping (multiplication) with the signal fc. The output signal Vout +, Vout− of the subsequent chopper circuit CHP2 can be passed through a low-pass filter LPF (not shown) to obtain an output signal from which noise has been removed.

  As shown in FIG. 1, since the input signal Vin is in the direct current or low frequency band, it is up-converted by the chopper circuit CHP1 at the previous stage with the frequency fc and amplified by the operational amplifier AMP. The output Vamp of the operational amplifier AMP always includes flicker noise (1 / f noise) and output offset noise. However, by chopping at the frequency fc by the subsequent chopper circuit CHP2, the output signal Vout is returned to the low frequency band, and the noise component is up-converted to the high frequency band. Therefore, these high frequency band noise components can be removed by passing the low pass filter LPF.

  FIG. 2 is a diagram showing an equivalent circuit of the chopper amplifier and the frequency spectrum of the output signal. As described with reference to FIG. 1, the chopper amplifier includes a front-stage chopper circuit CHP1, an operational amplifier AMP, and a rear-stage chopper circuit CHP2. The flicker noise (1 / f noise) and the output offset noise are indicated by Voffset in the drawing, and the noise Voffset is added to the output of the operational amplifier AMP by the adder 10 in an equivalent circuit. In the figure, an arithmetic expression of the output signal Vout is shown. c1 and c2 correspond to chopping signals, and A corresponds to the amplification factor of the operational amplifier.

  FIG. 2 shows an example of the frequency spectrum of the output signal Vout obtained by simulation. According to this, the signal component signal exists in the low frequency band fin, but many spurious Spurs described above exist in a specific frequency in the high frequency band. Further, as in the example of FIG. 2, spurious spur having higher power than the signal signal may occur, and in order to effectively remove the spurious spur with the low-pass filter LPF, a complicated and large-scale filter circuit is required. Required.

  FIG. 3 is a diagram showing the chopping imbalance of the chopper amplifier. As described above, a DC offset leak occurs in the output signal when a DC offset occurs in the chopping signal or due to an imbalance in the chopping operation caused by manufacturing variations in the transistors of the chopper circuit that is a multiplier. FIG. 3A shows the frequency spectrum of the output signal when a chopping operation is ideal in a chopper amplifier, that is, when no imbalance occurs. There is no DC offset leak component in the low frequency band of the signal component Signal. On the other hand, FIG. 3B shows the frequency spectrum of the output signal when the chopping operation is unbalanced in the same chopper amplifier. A DC offset leak component DC leak occurs in the low frequency band of the signal component signal. Such a DC offset leak component is undesirable because it becomes noise in the same frequency band as the signal component signal.

  FIG. 4 is a diagram showing the frequency spectrum of the output signal when a random signal is used as the chopping signal. The random signal is generated by, for example, a pseudo random number bit sequence generation circuit or a delta sigma modulator. Since the random signal has a large number of frequency components, by multiplying the random signal as a chopping signal in the chopper circuit, the spurious existing in the output signal can be distributed over a wide frequency band instead of a specific frequency.

  According to the frequency spectrum of FIG. 4, the noise component Noise is distributed over a wide frequency band, so that the peak of the high power spurious Spur at the frequency having the characteristics shown in FIG. 2 disappears. However, the dispersed noise component is not necessarily low in the low frequency band of the signal component Signal, or is not spectral null. Therefore, even if the signal of FIG. 4 is passed through the low-pass filter LPF, the SN ratio is hardly improved. This is because the envelope of the frequency spectrum of the random signal appears as it is in the frequency spectrum of the output signal. It is desirable that the envelope of the random signal is low in the low frequency band of the signal component. However, it is not preferable that the circuit for generating such a random signal becomes complicated and large-scale.

  FIG. 5 is a circuit diagram of the chopper amplifier according to the first embodiment. This chopper amplifier has a first chopper circuit CHP1 that multiplies the input signal Vin by the chopping signal CP, an operational amplifier AMP that amplifies the output of the first chopper circuit, and an output Vamp of the operational amplifier AMP that multiplies the chopping signal CP and outputs it. And a second chopper circuit CHP2 that outputs the signal Vout. Further, the chopper amplifier has a random chopping signal generation circuit 20 and uses a pseudo-random signal whose pulse width changes at random as the chopping signal CP.

  The random chopping signal generation circuit 20 includes a pseudo random signal generation circuit 22 that generates a pseudo random signal 23 whose pulse width changes at random, and a pseudo random signal 23 that includes a first random random signal generation circuit 22 as indicated by a broken line in FIG. And a multiplier 24 that multiplies the signal CLK1 and outputs a chopping signal CP. The first signal CLK1 is either the second frequency f2 at which the frequency spectrum of the pseudo-random signal 23 becomes null, or the sum f2 + fin of the second frequency f2 and the frequency fin of the input signal. It has a first frequency f1.

  As shown in FIG. 5, the frequency spectrum of the chopping signal CP has a characteristic that the power becomes zero or lower in the vicinity of the frequency fin of the input signal Vin, which is a weak signal from DC to low frequency. The reason is as follows. The pseudo random signal generation circuit includes, for example, a pseudo random bit sequence generation circuit and a delta sigma modulator. The frequency spectrum of the pseudo random signal generated by these pseudo random signal generation circuits is equivalent to the envelope of the noise component Noise in FIG. 4. For example, the frequency spectrum in which the power is zero or decreased at the second frequency f2 is null. Become. However, when the pseudo-random signal generation circuit has a simple circuit configuration, the frequency spectrum is not likely to be null at the frequency fin or low frequency of the input signal Vin (the frequency is zero if the input signal is DC).

  Therefore, in the present embodiment, the multiplier 24 is either the same frequency f2 as the second frequency f2 or the sum frequency (f2 + fin) of the second frequency f2 and the frequency fin of the input signal. The pseudo random signal 23 is multiplied by the signal CLK1 having the first frequency f1 (= f2 or f2 + fin). As a result, the frequency spectrum of the chopping signal CP after multiplication has a null at a frequency f2−f1 = 0 or a frequency f2−f1 = fin and the power becomes zero or small. This is as indicated by Null in the frequency spectrum in FIG.

  That is, the random chopping signal generation circuit 20 of the present embodiment generates a pseudo random signal 23 by a pseudo random signal generation circuit 22 that has a simple configuration and low power consumption, and multiplies the first signal CLK1 by a multiplier 24. To generate a chopping signal CP. As a result, as shown in FIG. 5, the chopping signal CP can have a frequency spectrum that becomes null in the vicinity of the frequency fin of the input signal. If the second frequency f2 at which the frequency spectrum of the pseudo random signal generation circuit 22 becomes null is known, the clock signal CLK1 having the first frequency f1 (= f2 or f2 + fin) that matches the second frequency f2 is generated. All you have to do is

  FIG. 6 is a specific circuit diagram of the chopper amplifier according to the first embodiment. This chopper amplifier has a front-stage chopper circuit CHP1, an operational amplifier AMP, and a rear-stage chopper circuit CHP2. The chopper circuits CHP1 and CHP2 are, for example, the first switch pair SW1 that switches the polarities of the differential input signals Vin + and Vin− in response to the chopping signals CP + and CP−, similarly to the chopper circuit shown in FIG. It is composed of a second switch pair SW2. If the first switch pair SW1 is turned on and the second switch pair SW2 is turned off, the differential input signal is output without inverting the polarity, and conversely, the first switch pair SW1 is turned off. When the second switch pair SW2 becomes conductive, the differential input signal is output with the polarity reversed. These first and second switch pairs are controlled in opposite phases by chopping signals CP + and CP-, respectively.

  The operational amplifier AMP has, for example, a pair of transistors, a pair of load resistors connected thereto, and a current source that supplies current to the pair of transistors. An input signal is supplied, and an amplified differential output signal is output from the drains of the pair of transistors.

  The random chopping signal generation circuit 20 of FIG. 6 generates a pseudo random signal 23 that generates a pseudo random signal 23 in which an H level and an L level are randomly generated according to the clock signal CLK2 having the second frequency f2 and the control signal CONT. The circuit 22 includes an exclusive OR circuit 24 that calculates and outputs an exclusive OR of the pseudo random signal 23 and the clock signal CLK1. The multiplier 24 shown in FIG. 5 includes this exclusive OR circuit 24. This exclusive OR circuit has a very simple configuration and low cost. Differential chopping signals CP + and CP− output from the exclusive OR circuit 24 are supplied to the chopper circuits CHP1 and CHP2.

  As described above, the pseudo-random signal generation circuit 22 is a pseudo-random bit sequence generation circuit that generates a pseudo-random signal 23 in synchronization with the clock signal CLK2 having the second frequency f2, or a first-order delta-sigma modulator. These circuits generate a pseudo-random signal whose frequency spectrum is null at the second frequency f2.

  FIG. 7 is a diagram illustrating an example of an input signal and an output signal of the exclusive OR circuit 24. The clock signal CLK1 alternately generates 1 level and 0 level with a period T. In the example of FIG. 7, the 1-level period is 0.6T, and the 0-level period is 0.4T. That is, the duty ratio is an example of 60%. On the other hand, the pseudo random signal 23 is a signal in which the 1 level and the 0 level are randomly generated, and the pulse width is changed randomly. Then, the exclusive OR circuit 24 calculates EOR of these signals CLK1 and CLK23 and outputs a chopping signal CP.

  The exclusive OR of the pseudo random signal 23 and the clock signal CLK1 is equivalent to multiplying the pseudo random signal 23 by the clock signal CLK1 having the frequency 1 / T = f1. As a result, the frequency spectrum of the pseudo random signal 23 is down-converted or up-converted by the frequency of the clock signal CLK1. Thereby, in the output signal of the exclusive OR circuit 24, the frequency spectrum becomes null at the frequency f2-f1.

  In FIG. 6, the frequency f1 of the clock signal CLK1 is a natural number multiple n * f2 of the frequency f2 of the second clock CLK2 or a natural number multiple n * f2 of the frequency f2 of the second clock CLK2 and the frequency fin of the input signal. (N * f2 + fin). In this case, the frequency nf2 of the spectrum null in FIG. 4 is down-converted to the frequency zero or the frequency fin of the input signal by the multiplication operation of the exclusive OR circuit 24. However, it is more preferable to down-convert the lowest spectral null frequency f2 in FIG. 4 to the frequency zero or the frequency fin of the input signal.

  FIG. 8 is a circuit diagram of the chopper amplifier according to the second embodiment. The first and second chopper circuits CHP1 and CHP2 and the operational amplifier AMP are the same as those in the first embodiment. Similarly to the first embodiment, the random chopping signal generation circuit 20 also includes a pseudo random signal generation circuit 22 and a multiplier 24 including an EOR circuit.

  However, the pseudo random signal generation circuit 22 is, for example, a first-order delta sigma modulator, and the probability of occurrence of 1 level and 0 level of the generated pseudo random signal can be changed according to the control signal CONT. For example, the DC component of the chopping signal CP can be increased by increasing the probability of 1 level by the control signal CONT, and conversely, the DC component of the chopping signal CP can be decreased by increasing the probability of 0 level. be able to. When the occurrence probability is 50%, the DC component is ½ of the voltage of one level.

  Further, the chopper amplifier of FIG. 8 includes a DC measurement circuit 30 that measures the DC component of the output signal Vout, and a control circuit 32 that variably controls the control signal CONT so that the measured DC component becomes zero.

  As described above, the chopping signal CP includes a DC offset component. Furthermore, a DC offset component is also generated in the chopped output signal due to variations in characteristics of the transistor switches of the chopper circuits CHP1 and CH2. Due to such an unbalanced operation of the chopping circuit, as shown in FIG. 3B, a DC offset leak component is generated in the vicinity of the signal frequency in the output Vout of the chopper amplifier.

  Therefore, in the second embodiment, the DC measurement circuit 30 and the control circuit 32 perform feedback control of the pseudo random signal generation circuit using the control signal CONT so that the DC component of the output signal Vout becomes zero. According to such feedback control, it is possible not only to adjust the duty ratio and skew of the chopping signal CP but also to eliminate imbalance caused by variations in transistors of the chopper circuit. This means that by making the chopping signal CP have a slight DC offset, it is possible to cancel the imbalance caused by variations in the characteristics of the transistors in the chopper circuit. For this purpose, the above feedback control is effective.

  FIG. 9 is a circuit diagram of another chopper amplifier in the second embodiment. A difference from the circuit diagram of FIG. 8 is that a switch SW10 connected to a constant voltage, for example, a ground GND, is provided at the terminal of the input signal Vin. The other configuration is the same as that of FIG.

  In this chopper amplifier, the switch SW10 is closed in a calibration process such as when the power is turned on, and the input is fixed to a constant voltage, for example, ground GND. Therefore, an appropriate DC level of the output signal Vout can be predicted. Then, the control circuit 32 detects the control signal CONT in which the DC component of the output signal Vout becomes zero. As this detection method, for example, a binary search method can be used. Specific examples will be described later.

  FIG. 10 is a diagram illustrating a random signal and a DC voltage of the chopping signal in the random chopping signal generation circuit. The control bit on the horizontal axis in FIG. 10 is the control signal CONT, and the DC voltage on the vertical axis is the DC component of the signal. As shown in FIG. 7, the ratio between the 1 level and 0 level of the random signal 23 can be changed by the control signal CONT of the pseudo random signal generation circuit. By changing the ratio, the DC voltage of the random signal 23 changes greatly as shown in the figure. As a result, the chopping signal multiplied by the first clock CLK1 also has a small slope but changes in a small range according to the control bit. The normal phase CP + of the chopping signal has the same slope as that of the random signal 23, and the reverse phase CP− of the chopping signal has a slope opposite to that of the random signal 23.

  In the example of FIG. 10, when the 8-bit control bit CONT is 0, the 0 level of the random signal is 100% and the DC voltage is 0V. On the other hand, when the control bit CONT is 255, one level of the random signal is 100% and the DC voltage is 1200 mV. When the control bit CONT is 127, the ratio between the 0 level and 1 level of the random signal is 50%, and the DC voltage is 600 mV, which is intermediate between 0 V of 0 level and 1200 mV of 1 level.

  FIG. 11 is a diagram for explaining a calibration process in the chopper amplifiers of FIGS. In this example, the control signal CONT in which the DC component 31 of the output signal Vout is zero is searched by the binary search method described above. In FIG. 11, the horizontal axis represents the control bit CONT, and the vertical axis represents the DC component 31 of the output signal Vout. In this example, when the 8-bit control bit CONT is changed from 0 to 255, the DC component changes from a positive voltage to a negative voltage.

  Therefore, in a state where the input voltage is connected to the ground voltage, the control circuit 32 searches for the control bit CONT in which the DC component 31 becomes zero by the binary search method. First, in step S1, the control circuit 32 sets the control bit CONT = 127 and checks the measurement result of the DC measurement circuit 30. In the example of FIG. 11, since the measured DC voltage is positive higher than the reference value 0, in step S2, the control circuit 32 sets the control bit CONT to +64 and sets CONT = 191 to set the DC measurement circuit 30. Check the measurement result. This measurement result is negative in which the DC voltage is lower than the reference value 0. Therefore, in step S3, the control circuit 32 checks the measurement result of the DC measurement circuit 30 by setting the control bit CONT to -32 and setting CONT = 159. This measurement result is positive in which the DC voltage is higher than the reference value 0. Therefore, in step S4, the control circuit 32 checks the measurement result by setting the control bit CONT to -16 and setting CONT = 143. Similarly, the control circuit 32 changes the control bit to CONT = 151,155, and detects that the measurement result matches the reference value 0 at CONT = 155.

  This completes the calibration process. In normal operation thereafter, the control bit CONT = 155 is maintained, and the output voltage of the chopper amplifier does not include a DC offset leak component.

  FIG. 12 is a circuit diagram of a chopper amplifier according to the third embodiment. In the figure, frequency spectra 40 to 47 of each signal are shown. As in the second embodiment, this chopper amplifier includes a front-stage chopper circuit CHP1, an operational amplifier AMP, and a rear-stage chopper circuit CHP2. Further, the chopper signals CP + and CP− supplied to the chopper circuits CHP1 and CHP2 are generated by a random chopper signal generation circuit including a pseudo random signal generation circuit 22 and a multiplier 24, as in FIG. The pseudo random signal generation circuit 22 is, for example, a first-order delta sigma modulator, and is a circuit capable of controlling the ratio between the 1 level and the 0 level of the pseudo random signal 23 in accordance with the control signal CONT.

  Further, the chopper amplifier receives a low-pass filter LPF for inputting the chopper amplifier output Vout, an analog-to-digital conversion circuit ADC for converting the output into analog to digital, and a bit 31 of a DC component of the digital output, and a control signal corresponding thereto. And a decoder DEC for setting CONT. The analog-to-digital conversion circuit ADC generates a DC component bit, and therefore corresponds to the DC measurement circuit 30 in FIGS. The decoder DEC corresponds to the control circuit 32 shown in FIGS.

  FIG. 13 is a circuit diagram of a primary delta-sigma modulator. This delta-sigma modulator has an adder / subtractor 50, an integrating circuit 52, a quantizing circuit 54 composed of a comparator, and a delay circuit 56. These circuits operate in synchronization with the clock CLK2. The quantization circuit 54 compares the input value with a reference value and outputs a 1-level or 0-level pseudorandom signal 23 according to the magnitude relationship. The quantization error is fed back to the input side via the delay circuit 56 and added to the input signal. Then, a 1-level or 0-level pseudo-random signal 23 having a ratio corresponding to the value of the control signal CONT is generated.

  Returning to FIG. 12, the clock signal CLK <b> 1 has a frequency f <b> 1 as shown in the frequency spectrum 40. The pseudo random signal generation circuit 22 generates a pseudo random signal 23 according to the clock CLK2 and the control bit CONT. Since the pseudo-random signal 23 is a random signal, it is distributed over a wide frequency as shown in the frequency spectrum 41. Further, the pseudo random signal 23 has a frequency characteristic having a null in which power is reduced at the frequency f2 of the clock signal CLK2. However, the pseudo random signal 23 has high power at a low frequency which is the frequency of the input signal Vin of the chopper amplifier.

  Therefore, the EOR circuit 24 calculates an exclusive OR of the pseudo-random signal 23 and the first clock CLK1 having the frequency f1 = f2 or f2 + fin, and the positive-phase chopping signal CP + and the negative-phase chopping signal CP. -And output. As a result, as shown in the frequency spectrum 42 of the chopping signal, the envelope becomes null at the frequency f2-f1.

  The input signal Vin to the chopper amplifier has a direct current or low frequency frequency fin. As shown in the frequency spectrum 43. The chopper circuit CHP1 at the previous stage multiplies the input signal Vin by the chopping signals CP + and CP-. As a result, the input signal Vin is up-converted. However, since the frequency spectrum 42 of the chopping signals CP + and CP− has dispersed frequency components, the up-converted signal has a frequency characteristic corresponding to the chopping signal as indicated by the frequency spectrum 44.

  The operational amplifier AMP amplifies the output of the chopper circuit CHP1 and outputs an output signal Vamp. In this signal Vamp, as indicated by the frequency spectrum 45, flicker noise 1 / f is mixed. In the subsequent chopper circuit CHP2, the output signal Vamp is multiplied by the chopping signal, the signal component is down-converted, and the flicker noise is up-converted to a large number of dispersed frequencies. That is, by multiplying random chopping signals distributed over many frequencies, the multiplied signal is distributed over a wide frequency band with spurious such as flicker noise.

  As a result, as shown in the frequency spectrum 46, the output signal Vout generates an amplified output signal Vout at the frequency fin of the input signal, and spurious such as flicker noise is distributed to many frequencies. Such spurious with high power at a specific frequency is not formed. Furthermore, this noise component has a characteristic that the power becomes null at the frequency f1-f2. Therefore, the SN ratio with respect to the output signal Vout is improved.

  A high frequency band of the output signal Vout is removed by the low pass filter LPF. As shown in the frequency spectrum 47. This low-pass filter LPF does not necessarily have a high order, and even a simple filter can sufficiently reduce high frequency noise. This is because there is no spurious having high power at a specific frequency.

  The analog output signal that has passed through the low-pass filter is converted into a digital signal by the analog-digital converter ADC. This digital signal includes a bit indicating a DC component together with a sign bit. A signal indicating the code and the DC component is supplied as a measured DC component 31 to a decoder DEC which is a control circuit.

  As described above, the decoder DEC searches for the control signal CONT in which the DC component 31 becomes zero. In this search process, the input signal Vin is set to a constant voltage or a ground voltage.

  FIG. 14 and FIG. 15 are diagrams showing the frequency spectrum of the chopper amplifier output when a pseudo-random bit sequence generator is used in the pseudo-random signal generation circuit. It is a simulation result. In the example of FIG. 14, the frequency f1 of the first clock signal CLK1 is made equal to the frequency f2 (10 MHz) of the clock signal CLK2 of the pseudo random number bit sequence generator. As a result, spectrum null Null is formed at frequency 0, and the noise power in the frequency band of the output signal signal is low.

  In the illustrated example, the frequency f1 of the first clock signal CLK1 is equal to the sum of the frequency f2 (10 MHz) of the clock signal CLK2 of the pseudo random number bit sequence generator and the frequency fin of the input signal. As a result, the spectrum component Null is formed at the frequency fin, and the noise power in the frequency band of the output signal signal is low.

  16 and 17 are diagrams showing the frequency spectrum of the chopper amplifier output when a first-order delta-sigma modulator is used in the pseudo-random signal generation circuit. FIG. 16A shows a frequency spectrum when the frequency f1 of the first clock signal CLK1 is equal to the frequency f2 (10 MHz) of the clock signal CLK2 of the delta-sigma modulator 24. There is a spectrum null Null at a frequency of zero.

  FIGS. 16B and 16C also show frequency spectra when f1 = f2, but are examples of control signals CONT1 and CONT2, respectively. That is, the control signals are different. Further, the frequency on the horizontal axis is 0 to 20 MHz, which is narrower than that in FIG. Note that the control signal CONT2 in FIG. 16C is the same as the example in FIG. Therefore, FIGS. 16A and 16C have the same frequency spectrum. As can be seen from a comparison between FIGS. 16B and 16C, the noise envelopes near the frequency 0 are almost the same even if the control signal CONT is different.

  The example of FIG. 17 is a frequency spectrum when f1 = f2 + fin. A spectrum null is generated at the frequency fin of the signal. That is, compared to FIG. 16, the noise floor near the frequency of the signal Signal is lower over a wider frequency band.

  As understood from the above simulation results, according to the chopper amplifier of the present embodiment, it is possible to eliminate the spurious signal that increases at a specific frequency, and in the frequency band of the signal amplified by the chopper amplifier, Can be lowered. Further, the DC offset leak component of the output signal can be removed by the feedback loop.

  The above embodiment is summarized as follows.

(Appendix 1)
A first chopper circuit for multiplying an input signal by a chopping signal;
An operational amplifier for amplifying the output of the first chopper circuit;
A second chopper circuit for multiplying the output of the operational amplifier by the chopping signal and outputting an output signal;
A pseudo-random signal generation circuit that generates a pseudo-random signal whose pulse width changes randomly;
Either the second frequency (f2) at which the frequency spectrum of the pseudo-random signal is null, or the sum frequency (f2 + fin) of the second frequency (f2) and the frequency (fin) of the input signal A chopper amplifier having a multiplier that multiplies the pseudo-random signal by a first signal having a first frequency (f1) and outputs the chopping signal.

(Appendix 2)
In Appendix 1,
The first signal is a first clock signal (CLK1) having the first frequency;
The multiplier is a chopper amplifier that is an exclusive OR circuit that inputs the pseudo random signal and the first clock signal and outputs an exclusive OR signal thereof as the chopping signal.

(Appendix 3)
In Appendix 2,
The pseudo-random signal generation circuit is a pseudo-random bit sequence generator or a delta-sigma modulator that generates the pseudo-random signal based on a second clock (CLK2),
A chopper amplifier in which the frequency (f1) of the first clock signal is a natural number multiple of the frequency of the second clock (CLK2).

(Appendix 4)
In Appendix 2,
The pseudo-random signal generation circuit is a pseudo-random bit sequence generator or a delta-sigma modulator that generates the pseudo-random signal based on a second clock (CLK2),
A chopper amplifier in which the frequency (f1) of the first clock signal is a sum of a natural number multiple of the frequency of the second clock (CLK2) and the frequency of the input signal.

(Appendix 5)
In Appendix 1,
A DC component measuring unit for measuring a DC component of the output signal output from the second chopper circuit;
A control unit that supplies a control signal to the pseudo-random signal generation circuit so that the DC component measured by the DC component measurement unit is zero;
The pseudo-random signal generation circuit is a chopper amplifier that changes a DC component of the pseudo-random signal in accordance with the control signal.

(Appendix 6)
In Appendix 5,
The pseudo-random signal generation circuit is a delta-sigma modulator that quantizes an input signal in synchronization with a clock and adds or subtracts a quantization error to the input signal for further quantization, and the control signal is the delta-sigma modulator. A chopper amplifier that is input as the modulator input signal.

(Appendix 7)
A first chopper circuit for multiplying an input signal by a chopping signal;
An operational amplifier for amplifying the output of the first chopper circuit;
A second chopper circuit for multiplying the output of the operational amplifier by the chopping signal and outputting an output signal;
A pseudo-random signal generation circuit for generating a pseudo-random signal whose pulse width changes randomly,
The pseudo-random signal is supplied to the first and second chopper circuits as the chopping signal;
A DC component measuring unit for measuring a DC component of the output signal output from the second chopper circuit;
A control unit that supplies a control signal to the pseudo-random signal generation circuit so that the DC component measured by the DC component measurement unit is zero;
The pseudo-random signal generation circuit is a chopper amplifier that changes a DC component of the pseudo-random signal in accordance with the control signal.

(Appendix 8)
In Appendix 7,
The pseudo-random signal generation circuit is a delta-sigma modulator that quantizes an input signal in synchronization with a clock and adds or subtracts a quantization error to the input signal for further quantization, and the control signal is the delta-sigma modulator. A chopper amplifier that is input as the modulator input signal.

CHP1: Front stage chopper circuit CPH2: Rear stage chopper circuit
AMP: operational amplifier 20: random chopping signal generation circuit 22: pseudo random signal generation circuit 23: pseudo random signal 24: multiplier CLK1: first signal
CLK2: Pseudorandom signal generation circuit clock signal
f1: CLK1 frequency f2: CLK2 frequency
Vin: Input signal fin: Input signal frequency
Vout: Output signal CONT: Control signal, control bit

Claims (5)

A first chopper circuit for multiplying an input signal by a chopping signal;
An operational amplifier for amplifying the output of the first chopper circuit;
A second chopper circuit for multiplying the output of the operational amplifier by the chopping signal and outputting an output signal;
A pseudo-random signal generation circuit for generating a pseudo-random signal whose pulse width changes randomly;
A first signal having a first frequency that is either a second frequency at which the frequency spectrum of the pseudo-random signal is null or a sum frequency of the second frequency and the frequency of the input signal is represented by the pseudo-signal. A chopper amplifier having a multiplier for multiplying a random signal and outputting the chopping signal. In claim 1,
The first signal is a first clock signal having the first frequency;
The multiplier is a chopper amplifier that is an exclusive OR circuit that inputs the pseudo random signal and the first clock signal and outputs an exclusive OR signal thereof as the chopping signal. In claim 1,
A DC component measuring unit for measuring a DC component of the output signal output from the second chopper circuit;
A control unit that supplies a control signal to the pseudo-random signal generation circuit so that the DC component measured by the DC component measurement unit is zero;
The pseudo-random signal generation circuit is a chopper amplifier that changes a DC component of the pseudo-random signal in accordance with the control signal. In claim 3,
The pseudo-random signal generation circuit is a delta-sigma modulator that quantizes an input signal in synchronization with a clock and adds or subtracts a quantization error to the input signal for further quantization, and the control signal is the delta-sigma modulator. A chopper amplifier that is input as the modulator input signal. A first chopper circuit for multiplying an input signal by a chopping signal;
An operational amplifier for amplifying the output of the first chopper circuit;
A second chopper circuit for multiplying the output of the operational amplifier by the chopping signal and outputting an output signal;
A pseudo-random signal generation circuit for generating a pseudo-random signal whose pulse width changes randomly,
The pseudo-random signal is supplied to the first and second chopper circuits as the chopping signal;
A DC component measuring unit for measuring a DC component of the output signal output from the second chopper circuit;
A control unit that supplies a control signal to the pseudo-random signal generation circuit so that the DC component measured by the DC component measurement unit is zero.
The pseudo-random signal generation circuit is a chopper amplifier that changes a DC component of the pseudo-random signal in accordance with the control signal.

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