JP2011071262A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus capable of suppressing the formation of a parasitic MOS and reducing narrow channelization. <P>SOLUTION: A method of manufacturing a semiconductor apparatus 100 forms a transistor whose source and drain regions are a first conductivity type on an SOI substrate 1, including a supporting substrate 2, an insulating layer 3 and a semiconductor layer 4. The method includes the following steps of forming a first oxidation resistant film 6a' on the semiconductor layer 4; injecting an impurity 7 with a second conductivity type whose conductivity is different from that of the first conductivity type into the semiconductor layer 4 by using the first oxidation resistant film 6a' as a mask; forming a second oxidation resistant film 6b' on a side surface of the first oxidation resistant film 6a' after injecting the impurity 7 with the second conductivity type into the semiconductor layer 4; forming an element separation layer 8 by using the first oxidation resistant film 6a' and the second oxidation resistant film 6b' as masks; and removing the first oxidation resistant film 6a' and the second oxidation resistant film 6b' from the semiconductor layer 4, after the element separation layer 8 is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a MOSFET using an SOI substrate, and more particularly to suppression of parasitic MOS formation and reduction of a narrow channel effect.

  A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) formed on a semiconductor substrate (hereinafter also referred to as an SOI substrate) including an SOI (Silicon On Insulator) layer, that is, an SOI-MOSFET is a conventional bulk semiconductor substrate. The device has a smaller parasitic capacitance than the formed MOSFET, and is expected to increase the operation speed and voltage. There are roughly two types of SOI-MOSFETs. One type is a “fully depleted type” where the depletion layer reaches the BOX layer included in the SOI substrate during operation, and the other type is a “partial depletion type” where the depletion layer does not reach this BOX layer during operation and a neutral region remains. Is.

  Although fully depleted SOI-MOSFETs exhibit the features of SOI-MOSFETs such as high-speed operation and low voltage, the thickness of the SOI layer is several tens of nanometers or less. . On the other hand, the partially-depleted SOI-MOSFET shows complicated behavior such as a kink phenomenon due to the substrate floating effect and a change in body potential due to the state of the body neutral region, but the thickness of the SOI layer is It is at the level of 100 nm, and its difficulty in manufacturing is not so high as compared with the fully depleted type. In the partially depleted type, by setting the substrate potential (body potential) to an appropriate value, it is possible to obtain excellent characteristics as in the fully depleted type. The structure of this partially depleted SOI-MOSFET is described in Patent Document 1, for example.

JP 2004-128254 A Japanese Patent No. 3184348

By the way, although it is a partially depleted SOI-MOSFET having excellent characteristics as described above, the prior art has significant problems of suppressing the formation of parasitic MOS and reducing the narrow channel effect. Therefore, first, the “parasitic MOS” will be described, and then the “narrow channel effect” will be described.
5A is a plan view of the SOI-MOSFET 200 manufactured by the conventional technique, FIG. 5B is a cross-sectional view taken along Y ₅ -Y ′ ₅ , and FIG. 5C is X ₅ -X ′. Sectional views along ₅ are shown respectively. As shown in FIG. 5B, the parasitic MOS 201 is formed in the SOI layer 204 under an end portion (that is, bird's beak) 208a of a LOCOS (LOCal Oxidation of Silicon) layer 208 used for element isolation. The cause is that when the LOCOS layer 208 is formed, impurities are sucked out from the SOI layer 204 under the bird's beak 208a to the LOCOS layer 208, and stress is applied under the bird's beak 208a. There are various things such as leaking.

In addition, the parasitic MOS 201 may cause defects in the electrical characteristics of the partially depleted SOI-MOSFET 200. The parasitic MOS 201 is a MOS that has a lower threshold voltage _Vth and a smaller gate width than the main MOS (that is, the one obtained by removing the parasitic MOS from the SOI-MOSFET). Therefore, as shown in FIG. 6 (a), we obtain the transmission characteristic of the SOI-MOSFET200 _(V g -I _d characteristics), and transfer characteristics of the parasitic MOS201 the drain current _{I d} rises above is saturated earlier The transmission characteristics of the main MOS, which rises late and the drain current increases, overlap with each other. Therefore, as shown in FIG. 6B, the characteristic of the parasitic MOS 201 is the main characteristic (that is, the dominant characteristic) in the off region, and the main MOS characteristic is the main characteristic in the on region. It becomes. That is, a phenomenon occurs in which the OFF region current (OFF leak) increases due to the parasitic MOS 201.

As a countermeasure against such a problem caused by the parasitic MOS 201, generally, channel stopper ion implantation is performed in the SOI layer 204 under the bird's beak 208a to raise the threshold voltage _Vth of the parasitic MOS 201, thereby There is a method of making it difficult for the transfer characteristic of the parasitic MOS 201 to appear in the transfer characteristic. Specifically, for example, as already disclosed in Patent Document 2, channel stopper ion implantation is performed after nitride film patterning (that is, after mask formation), a diffusion process is performed, and the channel stopper region is expanded. Thus, the parasitic MOS 201 is suppressed by avoiding the suction area to the LOCOS layer 208 (first method described in Patent Document 2).

Further, by performing channel stopper ion implantation at a constant incident angle, it is covered with a patterned nitride film (ie, mask) in the vicinity of the boundary between the SOI layer 204 and the BOX layer 203 included in the SOI substrate. A method of forming a channel stopper region in at least a part of the SOI layer 204 and avoiding a suction region to the LOCOS layer 208 has been proposed (second method described in Patent Document 2).
Further, a method has been proposed in which channel stopper ion implantation is performed after the formation of the LOCOS layer 208 to completely avoid sucking into the LOCOS layer 208 (third method described in Patent Document 2).

  However, each of these three methods disclosed in Patent Document 2 has a problem. In the first method, since a long diffusion process is newly added, there is a problem that the number of processes increases, and manufacturing time and manufacturing cost increase. Further, since the impurity concentration (concentration of implanted channel stopper ions) is reduced by diffusion, the formation of the parasitic MOS 201 may not be suppressed depending on the thickness (film thickness) of the LOCOS layer 208 to be formed.

Next, in the second method, a channel stopper region is formed on at least a part of the SOI layer 204 that is near the boundary between the SOI layer 204 and the BOX layer 203 and is covered with a mask (that is, a patterned nitride film). Even if it is formed, the bird's beak 208a is still formed inside the portion covered with the mask, so that channel stopper ions are also sucked out to the bird's beak 208a side even in this method, and the parasitic MOS 201 may be formed.
Finally, in the third method, since the channel stopper ion implantation damage remains in the LOCOS layer 208, there is a high possibility that the LOCOS layer 208 is reduced by cleaning or the like, and an unexpected problem may occur.

Next, the “narrow channel effect” will be described. As described in the description of the parasitic MOS 201, when the LOCOS layer 208 is formed, the bird's beak 208a may be formed inside the portion of the SOI layer 204 covered with the mask. This may cause the channel width to be narrower than desired. This is not a big problem for a relatively large size transistor, but for a small size transistor, it can cause a narrow channel effect (an effect of increasing _Vth by narrowing the channel width). There is.

Thus, in the conventional manufacturing method, the parasitic MOS 201 is formed under the bird's beak 208a, and the parasitic MOS 201 may operate before the main MOS. In addition, the SOI-MOSFET 200 may be narrowed by the bird's beak 208a. For this reason, the electrical characteristics (for example, transfer characteristics) of the manufactured semiconductor device may differ from what was initially expected.
Accordingly, some aspects of the present invention have been made in view of such circumstances. When forming a MOSFET on an SOI substrate (that is, when forming an SOI-MOSFEFT), the formation of the parasitic MOS 201 is performed. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be suppressed and can reduce the narrowing of an SOI-MOSFET.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a supporting substrate, an insulating layer formed over the supporting substrate, and a semiconductor layer formed over the insulating layer. A method of manufacturing a semiconductor device, wherein a transistor having a source region and a drain region of a first conductivity type is formed on an SOI substrate including the semiconductor substrate, wherein the semiconductor layer included in the SOI substrate is patterned into a desired shape. Forming a first oxidation-resistant film, and using the first oxidation-resistant film as a mask, a second conductivity type impurity having a conductivity different from that of the first conductivity type impurity is used as the semiconductor. And a step of forming a second oxidation-resistant film on a side surface of the first oxidation-resistant film after the step of implanting into the layer and the step of injecting the second conductivity type impurity into the semiconductor layer; , The first oxidation resistant film and the second After the step of forming an element isolation layer by thermally oxidizing the semiconductor layer using the oxide film as a mask and the step of forming the element isolation layer, the first oxidation-resistant film and the Removing the second oxidation-resistant film from the semiconductor layer.

  According to the manufacturing method of the semiconductor device, the second conductivity type impurity can be implanted into the semiconductor layer under the region where the end portion (that is, bird's beak) of the element isolation layer is formed. Thereby, even if the second conductivity type impurity is sucked out from under the region where the bird's beak is formed in the element isolation layer forming step, the impurity concentration of the second conductivity type impurity in the region after the suction is high. Kept. Accordingly, it is possible to suppress the formation of parasitic elements (that is, parasitic MOS) in the transistor.

Further, by thermally oxidizing the semiconductor layer using not only the first oxidation resistant film but also the second oxidation resistant film as a mask, the bird's beak formed on both sides of the semiconductor layer in a cross-sectional view is fixed. (That is, a constant channel width). Thereby, it can also reduce that the channel width of the manufactured transistor becomes narrower than a desired value.
Furthermore, in the method for manufacturing a semiconductor device, in the step of injecting the second conductivity type impurity into the semiconductor layer, the second conductivity type impurity may be injected into a lower layer portion of the semiconductor layer. .
According to the method for manufacturing a semiconductor device, the impurity concentration of the second conductivity type impurity can be kept high even in the lower layer portion of the semiconductor layer, in which the second conductivity type impurity is particularly easily extracted. Thereby, it becomes possible to further suppress the formation of the parasitic MOS included in the transistor.

Furthermore, in the method for manufacturing a semiconductor device, the second oxidation-resistant film may be a harder film than the first oxidation-resistant film.
According to the manufacturing method of the semiconductor device, the deformation amount (degree of deformation) of the second oxidation-resistant film when forming the element isolation layer is determined by setting the hardness of the second oxidation-resistant film to the first value. This is smaller than the case where the hardness of the oxidation resistant film 1 is the same as that of the film (that is, the film is more difficult to deform). For this reason, it is possible to suppress the formation of bird's beak that proceeds toward the inside of the first oxidation-resistant film. As a result, the transistor can have a larger channel width, so that formation of a parasitic MOS can be suppressed.

Furthermore, in the method of manufacturing the semiconductor device, in the step of injecting the second conductivity type impurity into the semiconductor layer, the second conductivity type impurity is directed from above the SOI substrate toward the surface of the semiconductor layer. The injection may be performed at an oblique angle.
According to the semiconductor device manufacturing method, the second conductivity type impurity can be implanted into the semiconductor layer included in the SOI substrate and inside the region covered with the first oxidation resistant film. . As a result, the distribution range of the second conductivity type impurity can be further expanded to the inside of the region (element region) covered with the first oxidation-resistant film, so that the bird's beak can be formed even after the element isolation layer is formed. It becomes easy to keep the impurity concentration of the second conductivity type impurity below high. Therefore, formation of parasitic MOS can be further suppressed.

Furthermore, in the method for manufacturing a semiconductor device, before the step of forming the first oxidation resistant film, an upper surface of the semiconductor layer is interposed between the semiconductor layer and the first oxidation resistant film. The method may include a step of forming an oxide film so as to cover the surface.
According to the method for manufacturing a semiconductor device, when the second conductivity type impurity is implanted into the lower layer portion of the semiconductor layer, the formed oxide film serves as a buffer, and damage to the semiconductor layer can be reduced.
Furthermore, in the method for manufacturing a semiconductor device, the first oxidation resistant film and the second oxidation resistant film may each be a silicon nitride film.

The figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). 1 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. The figure which shows the difference in channel width. FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 6 is a diagram illustrating a configuration example of a semiconductor device according to a conventional example. The figure which shows the transfer characteristic of the semiconductor device which concerns on a prior art example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) First Embodiment FIGS. 1A to 1I are cross-sectional views showing a method for manufacturing an SOI-MOSFET 100 according to an embodiment of the present invention. As shown in FIG. 1A, first, an SOI substrate 1 is prepared. The SOI substrate 1 includes a support substrate 2 made of, for example, single crystal silicon, an insulating layer (hereinafter also referred to as a BOX layer) 3 formed on the support substrate 2, and a single substrate formed on the BOX layer 3. And a crystalline silicon layer (hereinafter also referred to as an SOI layer) 4. The SOI substrate 1 can be manufactured by various manufacturing methods. For example, the SOI substrate 1 can be manufactured by a bonding method, SIMOX (Separation by IMplanted Oxygen), or the like. The bonding method is a method of manufacturing the SOI substrate 1 by preparing two silicon substrates having an insulating film on the surface and bonding the insulating films of these silicon substrates together. SIMOX is a method for manufacturing the SOI substrate 1 by implanting oxygen into a single crystal silicon substrate at a high concentration to form an oxide film inside the silicon substrate.

Next, as shown in FIG. 1B, a pad oxide film (SiO ₂ film) 5 is formed on the SOI layer 4. The pad oxide film (hereinafter also simply referred to as an oxide film) 5 is formed by, for example, thermal oxidation. Next, a first oxidation resistant film 6 a is formed on the oxide film 5. The first oxidation resistant film 6a is, for example, a silicon nitride film (Si ₃ N ₄ film), and is formed by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, a photoresist film is applied onto the first oxidation resistant film 6a, exposed and developed to form a resist pattern (not shown) having an opening above the element isolation region.

Next, the first oxidation-resistant film 6a is dry-etched, for example, using this resist pattern as a mask. Thus, as shown in FIG. 1C, a first oxidation-resistant film 6a (that is, a mask 6a ′) patterned in a desired shape is provided. Then, after forming the mask 6a ′, the resist pattern is removed.
After removing the resist pattern, a second conductivity type impurity (hereinafter also referred to as channel stopper ions) 7 is implanted into the SOI layer 4 partially covered with the mask 6a ′. At this time, channel stopper ions 7 are implanted, for example, from above the SOI substrate 1 toward the surface of the SOI layer 4 at a substantially vertical angle.

  Thereby, the channel stopper ions 7 are implanted into the lower layer portion of the SOI layer 4, which is a boundary region with the BOX layer 3, and as a result, a channel stopper region 7a is formed (see FIG. 1D). Here, the “channel stopper region 7 a” refers to a region in the SOI layer 4 where the impurity concentration of the channel stopper ions 7 is high. In the case where an n-channel MOSFET is formed in the SOI layer 4, an impurity having p-channel conductivity (for example, boron) is implanted as channel stopper ions 7. Further, when a p-channel MOSFET is formed in the SOI layer 4, an impurity having n-channel conductivity (for example, phosphorus, arsenic, etc.) is implanted.

After the implantation of the second conductivity type impurity 7, that is, the channel stopper ion 7, a second oxidation resistant film 6b is formed so as to cover the entire surface of the SOI layer 4 partially covered by the mask 6a ′. Form (see FIG. 1 (e)). The second oxidation resistant film 6b is, for example, a silicon nitride film (Si ₃ N ₄ film). As the method for forming the second oxidation resistant film 6b, for example, the CVD method can be used similarly to the method for forming the first oxidation resistant film 6a. In this case, the hardness of the second oxidation resistant film 6b is equal to that of the first oxidation resistant film 6a.

  Next, the second oxidation resistant film 6b is etched back to provide a side wall spacer 6b 'formed of the second oxidation resistant film 6b on the side surface of the mask 6a'. When the sidewall spacer 6b 'is provided, as shown in FIG. 1 (f), at least the side surface of the mask 6a' is continuously covered. This etch back is performed by dry etching, for example.

Next, the SOI layer 4 partially covered with the mask 6a ′ and the sidewall spacer 6b ′ is thermally oxidized. Thereby, as shown in FIG. 1G, a LOCOS layer 8 is formed on the BOX layer 3 in the element isolation region. The LOCOS layer 8 electrically isolates the SOI layer 4 in the element region from the surroundings.
After electrically isolating the SOI layer 4, the mask 6 a ′, the side wall spacer 6 b ′, and the pad oxide film 5 are removed to form the SOI substrate 1 a. The removal of the mask 6a ′ made of the first oxidation resistant film 6a is performed by wet etching using, for example, hot phosphoric acid. The pad oxide film 5 is removed by wet etching using, for example, a hydrofluoric acid aqueous solution. The “SOI substrate 1a” includes a support substrate 2, a BOX layer 3 formed on the support substrate 2, and an SOI layer 4 formed on the BOX layer 3, as shown in FIG. And a substrate including a LOCOS layer 8 that electrically isolates the SOI layer 4 and a channel stopper region 7a.

A MOSFET is formed on the SOI substrate 1a thus formed. For example, a gate insulating film 9 is formed on the surface of the SOI layer 4 as shown in FIG. The gate insulating film 9 may be a gate oxide film formed by thermal oxidation of the SOI layer 4 or may be another insulating film (for example, a high-k film).
Further, for example, a polysilicon film is deposited so as to cover the entire surface of the SOI layer 4 including the gate insulating film 9. Thereafter, the polysilicon film is patterned to form the gate electrode 10 as shown in FIG. Next, a first conductivity type impurity (not shown) is ion-implanted into the SOI layer 4 using the gate electrode 10 as a mask, and thermal diffusion is performed. Thereby, as shown in FIGS. 2A to 2C, the source region 11 or the drain region 12 is formed in the SOI layer 4 below both sides of the gate electrode 10.

  Here, when an n-channel MOSFET is formed in the SOI layer 4, an n-type impurity (for example, phosphorus, arsenic, etc.) is ion-implanted as a first conductivity type impurity to form the source region 11 or the drain region 12. To do. When a p-channel MOSFET is formed in the SOI layer 4, a p-type impurity (for example, boron) is ion-implanted as a first conductivity type impurity to form the source region 11 or the drain region 12. The first conductivity type impurity is a conductivity type impurity different from the second conductivity type impurity 7. By such a method, the partially depleted SOI-MOSFET 100 is formed.

FIG. 3 is a diagram comparing the channel width W ₁ of the SOI-MOSFET 100 manufactured according to the present invention and the channel width W ₂ of the SOI-MOSFET ₂₀₀ manufactured according to the prior art. 3A is a cross-sectional view of the channel width W ₁ of the SOI-MOSFET 100 manufactured according to the present invention, and FIG. 3B is a cross-sectional view of the channel width W ₂ of the SOI-MOSFET ₂₀₀ manufactured according to the prior art. It is shown schematically by using. As shown in FIGS. 3A and 3B, according to the embodiment of the present invention, it is possible to provide a width between bird's beaks as compared to the case of the prior art. 3A and 3B, the gate insulating film and the gate electrode are not shown.
Thereby, formation of a parasitic MOS can be suppressed, and the influence of the parasitic MOS on the characteristics of the partially depleted SOI-MOSFET can be prevented. That is, it is possible to prevent the characteristics of the parasitic MOS from overlapping the characteristics of the main MOS. Further, narrowing of the channel of the SOI-MOSFET can be avoided, and desired electrical characteristics can be obtained.

(2) Other Embodiments In the above embodiment, when the first oxidation-resistant film 6a is dry-etched using the resist pattern as a mask, the first oxidation-resistant film is formed as shown in FIG. Although the case of etching only the film 6a has been described, the present invention is not limited to this. For example, at least a part of the SOI layer 4 may be exposed by etching the pad oxide film 5 in addition to the first oxidation resistant film 6a. Thereby, compared with the case where the pad oxide film 5 is provided, the channel stopper ions 7 can be efficiently implanted into the SOI layer 4 to form the channel stopper region 7a.

  Further, in the above embodiment, as shown in FIG. 1D, the channel stopper ions 7 are implanted at a substantially vertical angle from above the SOI substrate 1 toward the surface of the SOI layer 4 (that is, the second conductive In the above description, the type impurity 7 is implanted from a substantially normal direction of the upper surface of the SOI layer 4 included in the SOI substrate 1. However, the present invention is not limited to this. For example, as shown in FIG. 4A, it may be implanted at an oblique angle α from above the SOI substrate 1 toward the surface of the semiconductor layer (that is, the second conductivity type impurity 7 may be implanted). And may be implanted at a desired angle α from the normal direction of the surface of the SOI layer 4 included in the surface). The angle α is, for example, in the range of 0 degrees to 11 degrees.

  As a result, the channel stopper region 7a can be expanded to the inside of the SOI layer 4 that is partially covered with the mask 6a '(see FIG. 4A). Thus, by expanding the channel stopper region 7a and further providing the sidewall spacer 6b 'as shown in FIG. 4B, the impurity concentration of the channel stopper ion 7 under the bird's beak 8a can be sufficiently maintained. Thereby, formation of parasitic MOS can be further suppressed.

  In the above embodiment, the case where the hardness of the second oxidation-resistant film 6b is made equal to that of the first oxidation-resistant film 6a has been described, but the present invention is not limited to this. Absent. For example, the hardness of the second oxidation resistant film 6b may be higher than that of the first oxidation resistant film 6a. Note that the hardness of the second oxidation-resistant film 6b can be changed to the first oxidation-resistant film by adjusting the conditions for forming the second oxidation-resistant film 6b (for example, temperature, gas type, degree of vacuum, etc.). Higher than that of the conductive film 6a.

  Thereby, the hardness (rigidity) of the sidewall spacer 6b 'can be higher than that of the mask 6a'. Therefore, the amount of deformation (degree of deformation) of the sidewall spacer 6b ′ when forming the bird's beak 8a is made smaller than when the hardness of the sidewall spacer 6b ′ is equivalent to that of the mask 6a ′. (That is, it can be more difficult to deform). Therefore, it is possible to further suppress the formation of the bird's beak 8a that proceeds toward the inside of the SOI layer 4 that is partially covered by the mask 6a 'and the sidewall spacer 6b'. Thereby, when viewed in cross section, a large width can be provided between the bird's beaks 8a, and the formation of parasitic MOS can be suppressed.

1 SOI substrate, 1a SOI substrate, 2 support substrate, 3 BOX layer, 4 SOI layer, 5 pad oxide film, 6a first oxidation resistant film, 6a ′ mask, 6b second oxidation resistant film, 6b 'Sidewall spacer, 7 Second conductivity type impurity, 7a Channel stopper region, 8 LOCOS layer, 8a Bird's beak, 9 Gate insulating film, 10 Gate electrode, 11 Source region, 12 Drain region, 100 Partially depleted SOI-MOSFET 200 partially depleted SOI-MOSFET, 201 parasitic MOS, 202 support substrate, 203 BOX layer, 204 SOI layer, 208 LOCOS layer, 208a bird's beak, 209 gate insulating film, 210 gate electrode, 211 source region, 212 drain region, W ₁ Channel width in SOI substrate according to the present invention, W ₂ Channel width and α angle in the SOI substrate

Claims (6)

A semiconductor for forming a transistor having a source region and a drain region of a first conductivity type on an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer A device manufacturing method comprising:
Forming a first oxidation-resistant film patterned into a desired shape on the semiconductor layer included in the SOI substrate;
Injecting into the semiconductor layer a second conductivity type impurity having a conductivity different from that of the first conductivity type impurity, using the first oxidation resistance film as a mask;
Forming a second oxidation-resistant film on a side surface of the first oxidation-resistant film after injecting the second conductivity type impurity into the semiconductor layer;
Forming a device isolation layer by thermally oxidizing the semiconductor layer using the first oxidation-resistant film and the second oxidation-resistant film as a mask;
And a step of removing the first oxidation resistant film and the second oxidation resistant film from the semiconductor layer after the step of forming the element isolation layer. Manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of injecting the second conductivity type impurity into the semiconductor layer, the second conductivity type impurity is injected into a lower layer portion of the semiconductor layer. .   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second oxidation-resistant film is a harder film than the first oxidation-resistant film.   In the step of injecting the second conductivity type impurity into the semiconductor layer, the second conductivity type impurity is injected at an oblique angle from above the SOI substrate toward the surface of the semiconductor layer. A method for manufacturing a semiconductor device according to any one of claims 1 to 3.   A step of forming an oxide film so as to cover an upper surface of the semiconductor layer between the semiconductor layer and the first oxidation-resistant film before the step of forming the first oxidation-resistant film; 5. The method of manufacturing a semiconductor device according to claim 1, wherein:   6. The semiconductor device according to claim 1, wherein each of the first oxidation-resistant film and the second oxidation-resistant film is a silicon nitride film. Production method.

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