JP2011071200A - Semiconductor, semiconductor element, method of manufacturing semiconductor, and method of manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor with a low-resistance semiconductor crystal formed on a nonpolar surface. <P>SOLUTION: The semiconductor includes a substrate 101, and p-type layers 108 and 109 laminated on a principal surface of the substrate 101, wherein the substrate principal surface is nonpolar, the p-type layers 108 and 109 are each formed of at least one of a group-III nitride semiconductor and a group-II oxide semiconductor, and each upper surface of the p-type layers 108 and 109 includes a facet plane having a plane direction different from that of the substrate principal surface. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor, a semiconductor element, a semiconductor manufacturing method, and a semiconductor element manufacturing method.

  The group III nitride semiconductor material has excellent properties such as a sufficiently large forbidden band (band gap) and direct transition between bands. For this reason, group III nitride semiconductors are actively studied for application to various semiconductor elements such as short wavelength light emitting elements. For example, the performance of light emitting diodes (LEDs) in the ultraviolet to blue and green wavelength regions using Group III nitride semiconductors has improved dramatically since the mid-1990s. For this reason, the application range of the LED to illumination, various display uses, etc. is remarkably widened, forming a very large market. The group III nitride semiconductor is also important as a material for a semiconductor laser used for, for example, a light source for a high-density optical disk and a display. The semiconductor laser is also referred to as a semiconductor laser or laser diode, and may be abbreviated as “LD”.

  LDs using group III nitride semiconductors are also being studied as light sources for projection displays and the like. For example, the inner stripe type GaN laser described in Patent Document 1 has good laser oscillation characteristics. The air ridge type GaN-based laser described in Patent Document 2 has a lower threshold current value and lower operating voltage than the conventional product.

JP 2003-78215 A JP 2003-179111 A

  A semiconductor device formed of group III nitride has the following problems. For example, a GaN-based laser can be obtained by growing GaN on the (0001) plane (polar plane). In this GaN-based laser, when the In composition of the InGaN quantum well layer is increased in order to increase the emission wavelength, the influence of piezoelectric polarization due to lattice mismatch increases, and electrons and holes are spatially separated. There is a problem that QCSE (Quantum Confined Stark Effect) occurs and the light emission efficiency rapidly decreases. In order to solve this problem, a GaN-based laser having a structure in which GaN is grown on a nonpolar plane that is a crystal plane inclined from the (0001) plane is conceivable. In this GaN-based laser, in addition to the improvement in light emission efficiency due to the reduction in QCSE, an improvement such as a lower threshold due to a decrease in valence band state density due to strain anisotropy is expected.

For example, the (11-22) semipolar plane is a crystal plane in which the atomic arrangement on the surface is close to the (001) plane arrangement of the zincblende structure and the crystal growth is relatively easy. However, as shown in FIG. 1, according to the study by the present inventors, the doping efficiency of Mg, which is a p-type dopant, on the (11-22) plane is about an order of magnitude higher than that on the (0001) plane. It is low and it is difficult to obtain a p-type layer with low resistance on the (11-22) plane. Further, the (1-100) plane is a nonpolar plane and essentially no QCSE problem occurs. However, as shown in FIG. 1, according to the study by the present inventors, the Mg doping efficiency on the (1-100) plane is about half of the (0001) plane, and (1-100) ) It is difficult to obtain a low resistance p-type layer even on the surface. In FIG. 1, the horizontal axis represents the supply amount of biscyclopentadienyl magnesium (Cp ₂ Mg), which is an Mg raw material, and the vertical axis represents the Mg atom concentration in the crystal measured by secondary ion mass spectrometry. Show.

  Accordingly, an object of the present invention is to provide a semiconductor, a semiconductor element, a semiconductor manufacturing method, and a semiconductor element manufacturing method in which a low-resistance semiconductor crystal is formed on a nonpolar plane.

In order to achieve the above object, the semiconductor of the present invention comprises:
A substrate, and a p-type layer stacked on the main surface of the substrate,
The substrate main surface is a nonpolar surface,
The p-type layer is formed of at least one of a group III nitride semiconductor and a group II oxide semiconductor, and an upper surface of the p-type layer includes a facet surface having a plane orientation different from that of the main surface of the substrate. And

  A semiconductor element of the present invention includes the semiconductor of the present invention.

The method for producing a semiconductor of the present invention comprises:
Including a step of forming a p-type layer from at least one of a group III nitride semiconductor and a group II oxide semiconductor on the main surface of a substrate having a nonpolar plane as a main surface. In the p-type layer forming step, The p-type layer is formed as a semiconductor including a facet surface having an upper surface different from the main surface of the substrate and is doped with a p-type dopant.

  The semiconductor device manufacturing method of the present invention is characterized in that the semiconductor is manufactured by the semiconductor manufacturing method of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor in which the low resistance semiconductor crystal was formed on the nonpolar surface, a semiconductor element, the manufacturing method of a semiconductor, and the manufacturing method of a semiconductor element can be provided.

FIG. 1 is a graph showing the surface orientation dependence of Mg doping efficiency. FIG. 2 is a cross-sectional view showing a configuration of an example of the semiconductor element of the present invention. FIG. 3 is a cross-sectional view showing the configuration of another example of the semiconductor element of the present invention. FIG. 4 is a cross-sectional view showing the configuration of still another example of the semiconductor element of the present invention. FIG. 5 is a cross-sectional view showing a configuration of a semiconductor element of one comparative example of the present invention.

  In the present invention, the bottom surface of the p-type layer is in direct contact with the substrate or is opposed to the substrate via another component.

  When the semiconductor of the present invention is used in a semiconductor light emitting device, examples of the “p-type layer” include a p-type optical confinement layer, a p-type cladding layer, and a p-type contact layer. In the case where there are a plurality of the p-type layers, it is not necessary that all the upper surfaces of the p-type layers include a facet surface having a plane orientation different from that of the main surface of the substrate, and the upper surfaces of at least one of the plurality of p-type layers. However, a facet plane having a plane orientation different from that of the substrate main surface may be included. In the present invention, in addition to the upper surface of the p-type layer, the bottom surface of the p-type layer may include a facet surface having a plane orientation different from that of the main surface of the substrate.

  In the semiconductor of the present invention and the manufacturing method thereof, examples of the substrate main surface (nonpolar surface) include a semipolar surface and a nonpolar surface. Examples of the semipolar plane include a (11-22) plane. Examples of the nonpolar plane include a (1-100) plane.

  In the semiconductor of the present invention and the method for manufacturing the same, the facet surface is at least one selected from the group consisting of (11-20) plane, (0001) plane, (1-100) plane, and (1-101) plane. When the substrate main surface is a (1-100) plane, the facet surface is preferably not a (1-100) plane.

  The type and area of the facet surface can be controlled, for example, by adjusting conditions such as pressure, temperature, and V / III ratio when forming the p-type layer. For example, when the substrate main surface is a (11-22) plane, when the p-type layer is formed under conditions of low pressure and high temperature, a facet plane composed of a (0001) plane and a (11-20) plane is obtained. When it is formed under the conditions of low pressure and high V / III ratio, a facet plane consisting of (0001) plane and (1-100) plane is obtained. The same applies to the case where the substrate main surface is another nonpolar surface such as a (1-100) surface. Since the doping efficiency of p-type dopants such as Mg is higher on these facet planes than on nonpolar planes, the p-type layer having a low resistance can be obtained. In the method for producing a semiconductor of the present invention, the p-type layer is formed under conditions of, for example, a pressure of 10 to 900 hPa and a temperature of 600 to 1300 ° C., preferably a pressure of 50 to 600 hPa and a temperature of 700 to 1200 ° C. Preferably, the pressure is 100 to 400 hPa and the temperature is 800 to 1100 ° C. Moreover, in the manufacturing method of the semiconductor of this invention, V / III ratio in the formation material of the said p-type layer is 1000-20000, for example, Preferably, it is 2000-15000, More preferably, it is 3000-10000. is there. The p-type dopant is not particularly limited, but for example, Mg is preferable.

  Here, it is known that the doping efficiency of Mg has a plane orientation dependency of (1-101)> (11-20) ≈ (0001) (S. N. Lee et al., J. MoI. Crystal Growth 307 (2007) 358, and T. Hikosaka et al., J. Crystal Growth 298 (2007) 207). From this and the findings of the present inventors shown in FIG. 1 described above, the Mg doping efficiency is (1-101)> (11-20) ≈ (0001)> (1-100)> (11 It can be seen that there is a plane orientation dependency of −22).

  When the nonpolar plane is the (11-22) plane, the (0001) plane, the (11-20) plane, (1), and the doping efficiency of the p-type layer is higher than that of the (11-22) plane. It is preferable to form facet surfaces such as a (-100) plane and a (1-101) plane. Thereby, the resistance of the p-type layer can be reduced, and a semiconductor with low operating voltage and low power consumption and heat generation can be obtained. For the same reason, when the nonpolar plane is a (1-100) plane, the p-type layer has a higher doping efficiency than the (1-100) plane (0001) plane, (11-20) ) Surface, (1-101) surface, and other facet surfaces are preferably formed.

In the semiconductor of the present invention and the method for manufacturing the same, the p-type layer is formed of at least one of a group III nitride semiconductor and a group II oxide semiconductor. When the semiconductor of the present invention is used in a semiconductor light emitting device, a desired oscillation wavelength can be obtained by arbitrarily selecting the composition of the material for forming the p-type layer. The p-type layer is preferably formed from the group III nitride semiconductor. Examples of the group III nitride semiconductor include those having a composition of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). . The oscillation wavelength can also be controlled by changing the thickness of the p-type layer. For example, in In _z Ga _1-z N, the band gap energy can be set to a desired value using the following formula (phys. Stat. Sol. (B) 230, No. 2, R4-R6 (2002) ).
Eg (z) = 3.493-2.843z-2.5 (1-z)

  The semiconductor element of the present invention preferably further includes a p-type electrode directly stacked on the p-type layer, and the p-type layer has the facet surface at the interface with the p-type electrode. The method for manufacturing a semiconductor device of the present invention may further include a step of laminating a p-type electrode directly on the p-type layer, and in the laminating step, the p-type layer is disposed on the interface with the p-type electrode. The p-type electrode is preferably laminated so as to have a surface.

  In the semiconductor device and the method of manufacturing the same according to the present invention, in the portion of the upper surface of the p-type layer that contacts the p-type electrode, the area of the facet surface is the total area of the portion that contacts the p-type electrode (p-type electrode) The contact area is preferably 1 to 100%, more preferably 2 to 100%, and still more preferably 5 to 100%. The ratio of the facet surface to the p-type electrode contact area can be measured by, for example, a scanning electron microscope, an atomic force microscope, or the like. The ratio of the facet plane to the p-type electrode contact area can be increased, for example, by setting the formation conditions of the p-type layer to low pressure, high temperature, and high V / III ratio. The conditions for forming the p-type layer are the same as the conditions for forming the p-type layer in the semiconductor manufacturing method of the present invention.

  In the semiconductor element of the present invention, it is preferable that the semiconductor element is a semiconductor light emitting element. The semiconductor light-emitting device obtained by the present invention includes, for example, a substrate and an n-type layer and a p-type layer stacked on the main surface of the substrate, and the substrate main surface is a nonpolar surface, and the p The mold layer is formed of at least one of a group III nitride semiconductor and a group II oxide semiconductor, and the upper surface of the p-type layer includes a facet surface having a plane orientation different from that of the main surface of the substrate. . Examples of the n-type layer include an n-type buffer layer, an n-type cladding layer, and an n-type optical confinement layer. Since the light emitting layer is formed on the nonpolar surface, the semiconductor light emitting device obtained by the present invention has high light emission efficiency. The application of the semiconductor light emitting device obtained in the present invention is not particularly limited, and examples thereof include an image display device and an information storage / reproduction device.

  Next, the embodiment of the present invention will be described by taking the case where the semiconductor of the present invention is used for a semiconductor element as an example. However, the present invention is not limited by the following description. In the drawings, for convenience of explanation, the structure of each part may be simplified as appropriate, and the dimensional ratio of each part may differ from the actual case.

(Embodiment 1)
The cross-sectional view of FIG. 2 shows a configuration of an example of the semiconductor element of the present invention. The semiconductor element of this embodiment is a semiconductor light emitting element (inner stripe type semiconductor laser). As illustrated, the semiconductor light emitting device 100 includes an n-type substrate 101, an n-type buffer layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, a quantum well layer 105, a cap layer 106, and a p-type optical confinement layer 107. , A current confinement layer 301, a p-type cladding layer 108, and a p-type contact layer 109 are stacked. The n-type substrate 101 is made of n-type (11-22) GaN. The n-type buffer layer 102 is made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 1000 nm). The n-type cladding layer 103 is made of Si-doped n-type Al _0.07 Ga _0.97 N (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 2000 nm). The n-type optical confinement layer 104 is made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 100 nm). The quantum well layer 105 is formed of a two-period multiple quantum well (Multi-Quantum Well: MQW) structure including an In _0.2 Ga _0.8 N (thickness 3 nm) well layer and an undoped GaN barrier layer. The cap layer 106 is made of Mg-doped p-type Al _0.2 Ga _0.8 N. The p-type optical confinement layer 107 is made of Mg-doped p-type GaN (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 100 nm). The p-type cladding layer 108 is made of Mg-doped p-type Al _0.07 Ga _0.93 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 500 nm). The p-type contact layer 109 is made of Mg-doped p-type GaN (Mg concentration 2 × 10 ²⁰ cm ⁻³ , thickness 20 nm). The n-type substrate 101 is, for example, a surface having an appropriate inclination angle (for example, within ± 15 °) from the (11-22) surface or a high index surface (11-2n) surface such as a (11-22) surface ( n is an integer having an absolute value exceeding 2). In addition, the n-type substrate 101 has, for example, a (1-10n) plane (n is an integer having an absolute value exceeding 1) and an appropriate inclination angle (for example, within ± 15 °) from the (1-10n) plane. A non-polar surface such as a (1-100) surface or a (11-20) surface, a surface having an appropriate inclination angle (for example, within ± 15 °) from the non-polar surface, or the like may be used as the main surface of the substrate. . Furthermore, the n-type substrate 101 may be a heterogeneous substrate such as sapphire other than GaN, SiC, ZnO, GaAs, Si, or a template substrate in which a GaN layer is formed on the heterogeneous substrate. A p-type electrode 201 is provided on the laminated structure so as to be in contact with the upper part of the p-type contact layer. An n-type electrode 202 is provided below the stacked structure so as to be in contact with the bottom surface of the n-type substrate 101.

  The current confinement layer 301 is made of AlN. A portion of the current confinement layer 301 is removed to form an opening 302, and the opening 302 is filled with the p-type cladding layer 108 to form an opening buried portion.

  In the present embodiment, the upper surfaces of the p-type cladding layer 108 and the p-type contact layer 109 are facet surfaces (11) having a plane orientation different from that of the main surface of the substrate ((11-22) plane) above the opening 302. -20) Including plane and (0001) plane.

  The structure of the semiconductor element of the present invention is not limited to the structure shown in FIG. For example, in the present embodiment, the facet plane is a (11-20) plane and a (0001) plane. On the other hand, in the semiconductor element of the present invention, the facet plane may be a (1-100) plane or a (1-101) plane. In the present embodiment, the upper surfaces of the p-type cladding layer 108 and the p-type contact layer 109 on the current confinement layer 301 include the facet surface. On the other hand, the semiconductor device of the present invention may be configured such that part or all of the upper surface of another p-type layer such as the p-type optical confinement layer 107 includes the facet surface. In this embodiment, the n-type substrate 101 is used. On the other hand, a p-type substrate may be used in the semiconductor element of the present invention. In this case, only the point that the upper surface of the p-type layer includes a facet plane having a plane orientation different from that of the main surface of the substrate is left as it is, and the n-type layer and the p-type layer are exchanged. In the semiconductor element of the present invention, the composition, thickness, and the like of each layer may be changed as appropriate from the above description as long as they can function appropriately as a semiconductor element. The semiconductor element of the present invention may have a structure in which each component shown in FIG. 2 is appropriately omitted, or may have a structure in which other components are appropriately added.

  The method for manufacturing the semiconductor element shown in FIG. 2 is not particularly limited, but is as follows, for example.

  First, the n-type substrate 101 is prepared. Next, the n-type buffer layer 102, the n-type cladding layer 103, the n-type optical confinement layer 104, the quantum well layer 105, the cap layer 106, and the p-type optical confinement are formed on the n-type substrate 101. The layers 107 are stacked in the above order. This formation method is not particularly limited, and for example, a usual method such as a vapor deposition method, more specifically, a metal organic vapor phase epitaxy (MOVPE) method can be used. Conditions such as gas concentration and growth temperature at the time of forming each layer can be appropriately set with reference to conditions generally used in the vapor phase growth method, for example.

  Next, an amorphous layer made of AlN is formed on the upper surface of the p-type optical confinement layer 107. This amorphous layer is later crystallized to become the current confinement layer 301. The amorphous layer can be formed by, for example, the MOVPE method.

  In the present invention, the formation temperature of the non-crystalline layer is not particularly limited, but is preferably 200 to 700 ° C., more preferably 200 to 500 ° C. when the amorphous layer is formed by vapor deposition using AlN. If the formation temperature is too high, crystallization proceeds during the formation, making it difficult to form the amorphous layer. If the formation temperature is too low, it is difficult to form the amorphous layer. When the formation material of the amorphous layer is other than AlN, or when the formation method is other than the vapor phase growth method, the formation temperature is appropriately set according to the formation material, the formation method, and the like of the amorphous layer. do it.

Next, a part of the amorphous layer is removed to form the opening 302. Although this method is not particularly limited, etching is preferable and wet etching is more preferable from the viewpoint of simplicity and cost. Next, an example of the wet etching method will be described. First, after depositing 100 nm of SiO ₂ on the amorphous layer and applying a resist, a stripe pattern having a width of 1.5 μm is formed on the resist by photolithography. Next, after etching the SiO ₂ with buffered hydrofluoric acid using the resist as a mask, the resist is removed with an organic solvent, and further washed with water. Next, the amorphous layer is etched using the SiO ₂ as a mask. As the etching solution, a phosphoric acid / sulfuric acid mixed solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1 is used. Further, the non-crystalline layer in the region not covered with the SiO ₂ is removed by etching for 8.5 minutes in the solution kept at 90 ° C. to form a stripe-shaped opening 302.

In the wet etching, various conditions such as the type of etching solution, the liquid temperature, and the type of mask are not limited to those described above, and can be set as appropriate. For example, in the above description, a phosphoric acid / sulfuric acid mixed solution at 90 ° C. is used, but other etching solutions may be used as long as selective and efficient etching can be realized. In the phosphoric acid / sulfuric acid mixed solution, the etching rate can be adjusted by, for example, the blending amount of sulfuric acid and the liquid temperature. In the above description, since the p-type optical confinement layer 107 (GaN) immediately below the non-crystalline layer is a crystalline layer, the former etching rate is significantly higher than the latter etching rate. In addition, efficient etching is possible. Therefore, the composition of the etching solution, the solution temperature, and the like are appropriately set so that the amorphous layer can be etched efficiently and the etching rate does not unnecessarily etch the p-type optical confinement layer 107. It is preferable to do. From this viewpoint, the temperature of the etching solution is preferably 50 ° C. or higher and 200 ° C. or lower. In the above description, SiO ₂ is used as the etching mask for the non-crystalline layer. However, an organic material containing SiN _x or a resist may be used as long as the material is not affected by the etching solution.

  Next, the p-type cladding layer 108 is covered so as to cover the upper surface of the amorphous layer and the upper surface of the p-type optical confinement layer 107 exposed from the opening 302 (so as to bury the opening 302). Is formed (embedded regrowth). At this time, prior to starting the formation of the p-type cladding layer 107, the substrate temperature is raised to the formation temperature of the p-type cladding layer 107. When this formation temperature is sufficiently high, the amorphous layer is heat-treated and crystallized to become the current confinement layer 301 between the start of the temperature rise and the completion of the formation of the p-type cladding layer 108.

  The heat treatment (crystallization) of the amorphous layer and the formation of the p-type cladding layer may be separate steps. However, as described above, if the formation of the p-type cladding layer 108 and the heat treatment of the amorphous layer are performed simultaneously, it is not necessary to separately provide a heat treatment step of the amorphous layer in the manufacture of the semiconductor element and increase the number of steps. Therefore, it is preferable. The maximum temperature during the heat treatment of the amorphous layer is preferably 700 to 1300 ° C, more preferably 900 to 1300 ° C. Thereby, the non-crystalline layer can be suitably converted into a crystalline layer (the current confinement layer 301). When the material for forming the amorphous layer is other than AlN, the heat treatment temperature may be appropriately set according to the material for formation.

  Next, the p-type contact layer 109 is formed on the upper surface of the p-type cladding layer 108. Here, the formation conditions of the p-type cladding layer 108 (AlGaN) and the p-type contact layer 109 (GaN) are set to low pressure and high temperature as compared with the formation of the n-type AlGaN and the n-type GaN. The facet plane (11-20) plane and the (0001) plane can be formed on the opening 302. In the present embodiment, the step of forming the p-type cladding layer 108 and the p-type contact layer 109 corresponds to the “p-type layer forming step”. The formation conditions of the p-type cladding layer 108 (AlGaN) and the p-type contact layer 109 (GaN) are, for example, a pressure of 10 to 900 hPa, a temperature of 600 to 1300 ° C., preferably a pressure of 50 to 600 hPa, and a temperature of 700 to 1200 ° C. More preferably, the pressure is 100 to 400 hPa and the temperature is 800 to 1100 ° C.

  Next, a p-type electrode 201 is formed on the upper surface of the p-type contact layer 109, and an n-type electrode 202 is formed on the bottom surface of the n-type substrate 101. The formation conditions of these electrodes are not particularly limited, and can be set as appropriate with reference to the electrode formation conditions of general semiconductor elements. In this way, the semiconductor light emitting device 100 shown in FIG. 2 can be manufactured. If necessary, the semiconductor light emitting device 100 may be cleaved in a direction perpendicular to the stripe to form a chip. The length of the chip (element length) can be appropriately set depending on the characteristics desired for the semiconductor light emitting element.

  In the semiconductor light emitting device shown in FIG. 2, the formation conditions of the p-type cladding layer 108 and the p-type contact layer 109 are low pressure and high temperature, so that the facet surface (11-20) ) Plane and (0001) plane. However, the semiconductor light emitting device of the present invention is not limited to this, and the semiconductor light emitting device 200 shown in FIG. 3 is formed by setting the p-type cladding layer 108 and the p-type contact layer 109 to have a lower pressure and a higher temperature. As described above, a plurality of facet planes (11-20) and (0001) may be formed over the entire top surfaces of the p-type cladding layer 108 and the p-type contact layer 109. The conditions for forming the p-type cladding layer 108 and the p-type contact layer 109 in this case are, for example, a pressure of 10 to 400 hPa and a temperature of 800 to 1300 ° C., preferably a pressure of 10 to 200 hPa and a temperature of 1000 to 1300 ° C. Is a pressure of 10 to 100 hPa and a temperature of 1100 to 1300 ° C. The configuration shown in FIG. 3 is particularly effective for reducing the p-type contact resistance. In FIG. 3, the same parts as those in FIG.

  According to this embodiment, the resistance of the p-type cladding layer 108 and the p-type contact layer 109 can be reduced, the operating voltage is low, the power consumption and the heat generation are small, and the light emitting efficiency is high. 100 can be obtained. In the present embodiment, since the upper surface of the p-type contact layer 109 includes a plurality of facet planes (11-20) and (0001), the p-type contact resistance is reduced, resulting in less power consumption and heat generation. The semiconductor light emitting device 100 can be obtained. However, the semiconductor element of the present invention is not limited to this, and may include only one facet surface.

(Embodiment 2)
The cross-sectional view of FIG. 4 shows the configuration of another example of the semiconductor element of the present invention. The semiconductor device of this embodiment is a semiconductor light emitting device (ridge stripe type semiconductor laser). As shown, the semiconductor light emitting device 300 does not have the current confinement layer 301 between the p-type optical confinement layer 107 and the p-type cladding layer 108, and the p-type contact layer 109 and the p-type Except that the clad layer 108 is formed as a ridge 303 having a width of 1.5 μm and a height of about 0.42 μm, the configuration is the same as that of the semiconductor light emitting device 100 shown in FIG. In the semiconductor light emitting device 300 shown in FIG. 4, the current confinement layer 301 is not formed between the p-type optical confinement layer 107 and the p-type cladding layer 108, and the p-type contact layer 109 and the p-type cladding layer are formed. ₂ is etched with a chlorine (Cl ₂ ) -based dry etching apparatus to form the ridge portion 303 having a width of 1.5 μm and a height of about 0.42 μm, and is the same as the semiconductor light emitting device 100 shown in FIG. Can be manufactured.

  Next, examples of the present invention will be described together with comparative examples. The present invention is not limited or restricted by the following examples and comparative examples.

Example 1
The semiconductor light emitting device 100 shown in FIG. 2 was produced. As the n-type substrate 101, an n-type GaN (11-22) substrate having an n-type carrier Si concentration of about 1 × 10 ¹⁸ cm ⁻³ was used. A MOVPE apparatus was used to manufacture the element. A mixed gas of hydrogen and nitrogen was used as the carrier gas. As supply sources of Ga, Al, and In, trimethylgallium (TMG), trimethylammonium (TMA), and trimethylindium (TMIn) were used, respectively. Silane (SiH ₄ ) was used as the n-type dopant. Biscyclopentadienyl magnesium (Cp ₂ Mg) was used as the p-type dopant.

  First, the n-type buffer layer 102, the n-type cladding layer 103, the n-type optical confinement layer 104, the quantum well layer 105, the cap layer 106, the p-type optical confinement layer 107, the p-type cladding layer 108, and the current confinement layer 301 are formed. Growth of each layer formed from group III nitride was performed. Hereinafter, these steps are collectively referred to as an “active layer growth step”.

That is, first, after the n-type GaN (11-22) substrate 101 is put into the MOVPE apparatus, the n-type GaN (11-22) substrate 101 is heated while supplying NH ₃ under a reduced pressure of 400 hPa, and the growth temperature is increased. When reaching the above, the growth of each layer was started. Thereby, the n-type buffer layer 102 made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 0.1 μm), Si-doped n-type Al _0.07 Ga _0.93 N ( N-type cladding layer 103 formed from Si concentration 4 × 10 ¹⁷ cm ⁻³ and thickness 2 μm) and Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ and thickness 0.1 μm). N-type optical confinement layer 104, a two-period multiple quantum well (MQW) layer formed of an In _0.2 Ga _0.8 N (thickness 3 nm) well layer and an undoped GaN (thickness 10 nm) barrier layer 105, Mg doped p-type _Al 0.2 _{Ga 0.8} capping layer 106 formed from N, Mg-doped p-type GaN (Mg concentration 2 × ¹⁰ 19 ^{cm -3,} thickness 0.1 [mu] m) formed from It was successively deposited p-type light confinement layer 107. The GaN growth was performed at a substrate temperature of 950 ° C., a TMG supply rate of 58 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. AlGaN growth was performed at a substrate temperature of 950 ° C., a TMA supply rate of 49 μmol / min, a TMG supply rate of 58 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. InGaN MQW growth was performed at a substrate temperature of 760 ° C., a TMG supply rate of 8 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. The TMIn supply rate was 48 μmol / min for the well layer and 3 μmol / min for the barrier layer.

Next, the substrate temperature was lowered to about 400 ° C., and an amorphous AlN layer (later crystallized to become the current confinement layer 301) was deposited on the p-type optical confinement layer 107. The supply amounts of TMA and NH ₃ during the deposition of the amorphous AlN layer were 36 μmol / min and 0.36 mol / min, respectively, and the deposited film thickness was 0.1 μm.

  Next, a part of the amorphous AlN layer was removed by etching to form a stripe-shaped opening 302 extending in the <1-100> direction. Hereinafter, this process is referred to as a “stripe formation process”.

That is, first, SiO ₂ was deposited to a thickness of 100 nm on the amorphous AlN layer to form a SiO ₂ layer. After applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 1.5 μm was formed on the resist by photolithography. Next, the SiO ₂ layer was etched with buffered hydrofluoric acid using the resist as a mask. Thereafter, the resist was removed with an organic solvent and washed with water. The amorphous AlN layer was not etched or damaged in each step of buffered hydrofluoric acid, organic solvent, and water washing. Next, the amorphous AlN layer was etched using the SiO ₂ layer as a mask. As an etching solution, a solution in which phosphoric acid and sulfuric acid were mixed at a volume ratio of 1: 1 was used. The AlN layer in the region not covered with the SiO ₂ mask was removed by etching in the solution kept at 90 ° C. for 8.5 minutes. As a result, the opening 302 was formed. Thereafter, the SiO ₂ layer used as a mask was removed with buffered hydrofluoric acid. In this way, the stripe forming step could be performed.

  Next, the amorphous AlN layer was converted into a crystalline layer (current confinement layer) 301 by heat treatment. Thereafter, the p-type cladding layer 108 was laminated so as to fill the opening 302 formed in the stripe forming step so as to form an opening buried portion, and a p-type contact layer 109 was further deposited. Hereinafter, these steps are collectively referred to as a “p-type cladding layer regrowth step”.

That is, first, the semiconductor wafer formed by the stripe forming process was put into a MOVPE apparatus. Subsequently, the inside of the MOVPE apparatus was depressurized to 130 hPa, and the temperature was raised to 1000 ° C. with an NH ₃ supply rate of 0.36 mol / min. After the substrate temperature reaches 1000 ° C., the p-type cladding layer 108 formed from Mg-doped p-type Al _0.07 Ga _0.93 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 0.5 μm). Deposited. Thereafter, a p-type contact layer 109 made of Mg-doped p-type GaN (Mg concentration 1 × 10 ²⁰ cm ⁻³ , thickness 0.02 μm) was deposited. The p-type AlGaN and p-type GaN are deposited under a lower pressure and a higher temperature than the formation of the n-type AlGaN and the n-type GaN, and the p-type cladding layer 108 and the p-type contact layer 109 The crystal surface being deposited is covered with a (11-20) facet plane and a (0001) facet plane. In this way, the p-type cladding layer regrowth step could be performed.

  The n-type electrode 202 is formed on the back surface (bottom surface) of the n-type GaN (11-22) substrate 101 of the LD wafer thus obtained, and the p-type electrode 201 is formed on the top surface of the p-type contact layer 109, respectively. Formed with. Hereinafter, this process is referred to as an “electrode formation process”. The ratio of the faceted surface to the p-type electrode contact area was about 1%. Then, the sample (structure) after the electrode forming step was cleaved in a direction perpendicular to the longitudinal direction of the opening embedded portion (stripe) to obtain the semiconductor light emitting device 100. The element length was 500 μm.

(Example 2)
The point that the current confinement layer 301 is not formed between the p-type optical confinement layer 107 and the p-type clad layer 108, and the p-type contact layer 109 and the p-type clad layer 108 are made of chlorine (Cl ₂ ). 2 except that a ridge portion 303 having a width of 1.5 μm and a height of about 0.42 μm was produced by etching using a dry etching apparatus of the same type as the semiconductor light emitting device 100 shown in FIG. The semiconductor light emitting device 300 shown in FIG.

(Comparative example)
The deposition conditions of the p-type AlGaN and the p-type GaN are the same as those during the formation of the n-type AlGaN and the n-type GaN, so that the p-type cladding layer 108 and the p-type contact layer 109 are being deposited. The semiconductor shown in FIG. 5 is the same as the semiconductor light emitting device 100 shown in FIG. 2 of Example 1 except that the crystal surface is covered with the same (11-22) plane as the main surface of the substrate. A light-emitting element 400 was manufactured.

(Evaluation)
The semiconductor light emitting devices obtained in Examples 1 and 2 and the comparative example were each fused to a heat sink, and the light emission characteristics were examined. As a result, the semiconductor light emitting devices of Examples 1 and 2 oscillated at a current density of 3.0 kA / cm ² , a voltage of 4.0 V, and a center wavelength of 450 nm. On the other hand, the semiconductor light emitting device of the comparative example oscillated at a current density of 4.0 kA / cm ² and a center wavelength of 450 nm, but the threshold voltage was as high as 6.0V.

100, 200, 300, 400 Semiconductor light emitting device 101 n-type substrate 102 n-type buffer layer 103 n-type cladding layer 104 n-type optical confinement layer 105 quantum well layer 106 cap layer 107 p-type optical confinement layer 108 p-type cladding layer 109 p Type contact layer 201 p-type electrode 202 n-type electrode 301 current confinement layer 302 opening 303 ridge

Claims (20)

A substrate, and a p-type layer stacked on the main surface of the substrate,
The substrate main surface is a nonpolar surface,
The p-type layer is formed of at least one of a group III nitride semiconductor and a group II oxide semiconductor, and an upper surface of the p-type layer includes a facet surface having a plane orientation different from that of the main surface of the substrate. A semiconductor. 2. The semiconductor according to claim 1, wherein the main surface of the substrate is a (11-22) plane. The semiconductor according to claim 1, wherein the main surface of the substrate is a (1-100) plane. The facet plane is at least one plane selected from the group consisting of (11-20) plane, (0001) plane, (1-100) plane, and (1-101) plane, and the main surface of the substrate 4 is a (1-100) plane, the facet plane is not a (1-100) plane. The semiconductor according to claim 1, wherein the facet plane is not a (1-100) plane. The p-type layer _is formed of a III group nitride semiconductor having a composition of _{In x Al y Ga 1-x} -y N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) The semiconductor according to any one of claims 1 to 4, wherein A semiconductor device comprising the semiconductor according to claim 1. And a p-type electrode laminated directly on the p-type layer,
The semiconductor device according to claim 6, wherein the p-type layer has the facet surface at an interface with the p-type electrode. The area of the facet surface in a portion in contact with the p-type electrode in the upper surface of the p-type layer is 1 to 100% with respect to the area of the entire portion in contact with the p-type electrode. Item 8. The semiconductor device according to Item 7. It is a semiconductor light emitting element, The semiconductor element as described in any one of Claim 6 to 8 characterized by the above-mentioned. An image display device comprising the semiconductor element according to claim 9. An information storage / reproducing apparatus comprising the semiconductor element according to claim 9. Including a step of forming a p-type layer from at least one of a group III nitride semiconductor and a group II oxide semiconductor on the main surface of a substrate having a nonpolar plane as a main surface. In the p-type layer forming step, A method of manufacturing a semiconductor, wherein the p-type layer is formed as a semiconductor including a facet surface having an upper surface different from the main surface of the substrate and doped with a p-type dopant. 13. The method of manufacturing a semiconductor according to claim 12, wherein the main surface of the substrate is a (11-22) plane. 13. The method of manufacturing a semiconductor according to claim 12, wherein the substrate main surface is a (1-100) plane. The facet plane is at least one plane selected from the group consisting of (11-20) plane, (0001) plane, (1-100) plane, and (1-101) plane, and the main surface of the substrate 15 is a (1-100) plane, the facet plane is not a (1-100) plane. The method of manufacturing a semiconductor according to claim 12, wherein the facet plane is not a (1-100) plane. In the p-type layer forming step, from the group III nitride semiconductor having a composition of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) to the p The method for manufacturing a semiconductor according to claim 12, wherein a mold layer is formed. In the said p-type layer formation process, the formation conditions of the said p-type layer are the pressure of 10-900 hPa, and the temperature of 600-1300 degreeC, The manufacturing of the semiconductor as described in any one of Claim 12-16 characterized by the above-mentioned. Method. The method for manufacturing a semiconductor element according to any one of claims 6 to 9, wherein the semiconductor is manufactured by the manufacturing method according to any one of claims 12 to 17. Laminating a p-type electrode directly on the p-type layer,
19. The method of manufacturing a semiconductor element according to claim 18, wherein in the stacking step, the p-type electrode is stacked so that the p-type layer has the facet surface at an interface with the p-type electrode. The p-type layer so that the area of the facet surface is 1 to 100% of the entire area of the p-type electrode in contact with the p-type electrode in the part in contact with the p-type electrode. 20. The method of manufacturing a semiconductor device according to claim 19, wherein:

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