JP2011069938A5 - - Google Patents
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- JP2011069938A5 JP2011069938A5 JP2009219938A JP2009219938A JP2011069938A5 JP 2011069938 A5 JP2011069938 A5 JP 2011069938A5 JP 2009219938 A JP2009219938 A JP 2009219938A JP 2009219938 A JP2009219938 A JP 2009219938A JP 2011069938 A5 JP2011069938 A5 JP 2011069938A5
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- JP
- Japan
- Prior art keywords
- solder resist
- low
- edge portion
- viscosity
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
気泡が残らないようにするために、低粘度のソルダーレジストを使用する方法が考えられる。しかし、はんだ付けする部分２０及びはんだ付けが不要な配線パターン２１からなる導体配線を形成した絶縁性基板１（図３（ａ））の基板全面を覆うように、低粘度のソルダーレジスト３の膜を形成すると、はんだ付けが不要な配線パターン２１のエッジ部４をソルダーレジスト３で十分に覆うことができない場合がある（図３（ｂ））。その結果、フォトマスク１１を介して、パターン露光を実施し（図３（ｃ））、現像及びポストキュアした後、本来はんだが付着すべきではないエッジ部４が露出し（図３（ｄ））、はんだが付着してしまうという問題が生じる。このエッジ部４が露出する問題は、低粘度のソルダーレジストを使用して、導体配線の厚みが３５μｍ以上と厚くなった場合にも生じる。
In order to prevent bubbles from remaining, a method using a low-viscosity solder resist can be considered. However, the film of the low-viscosity solder resist 3 is formed so as to cover the entire surface of the insulating substrate 1 (FIG. 3A) on which the conductor wiring composed of the soldering portion 20 and the wiring pattern 21 that does not require soldering is formed. In some cases, the edge portion 4 of the wiring pattern 21 that does not require soldering cannot be sufficiently covered with the solder resist 3 (FIG. 3B). As a result, pattern exposure is performed through the photomask 11 (FIG. 3C), and after development and post-curing, the edge portion 4 where the solder should not adhere is exposed (FIG. 3D). ), A problem that solder adheres occurs. The problem that the edge portion 4 is exposed also occurs when a low- viscosity solder resist is used and the thickness of the conductor wiring is as thick as 35 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009219938A JP5249890B2 (en) | 2009-09-25 | 2009-09-25 | Method for forming solder resist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009219938A JP5249890B2 (en) | 2009-09-25 | 2009-09-25 | Method for forming solder resist |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011069938A JP2011069938A (en) | 2011-04-07 |
| JP2011069938A5 true JP2011069938A5 (en) | 2012-02-09 |
| JP5249890B2 JP5249890B2 (en) | 2013-07-31 |
Family
ID=44015299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009219938A Active JP5249890B2 (en) | 2009-09-25 | 2009-09-25 | Method for forming solder resist |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5249890B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5723259B2 (en) * | 2011-11-17 | 2015-05-27 | 三菱製紙株式会社 | Dry film resist thinning method |
| JP6434328B2 (en) * | 2015-02-04 | 2018-12-05 | 新光電気工業株式会社 | WIRING BOARD, ELECTRONIC COMPONENT DEVICE, AND ITS MANUFACTURING METHOD |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0562894A (en) * | 1991-09-03 | 1993-03-12 | Sharp Corp | Forming method for fine pattern |
| JPH05273766A (en) * | 1992-03-26 | 1993-10-22 | Matsushita Electric Works Ltd | Circuit board |
| JP2004214253A (en) * | 2002-12-27 | 2004-07-29 | Mitsubishi Paper Mills Ltd | Method of forming metal pattern |
| EP2247170B1 (en) * | 2008-01-30 | 2014-10-22 | Mitsubishi Paper Mills Limited | Method for electroconductive pattern formation |
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2009
- 2009-09-25 JP JP2009219938A patent/JP5249890B2/en active Active
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