JP2011066626A - A/d conversion apparatus, and ic chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the area of the entire circuit so that an IC (Integrated Circuit) chip, etc. having both functions of a pipeline type A/D conversion apparatus and ΔΣ type A/D conversion apparatus may be easily mounted on small communication equipment. <P>SOLUTION: An A/D conversion apparatus is configured by dependently connecting a plurality of steps of a stage including a subtractor 1, etc., a sample hold circuit S&H_1, etc., an A/D conversion apparatus AD1, etc., a D/A converter DA1, etc. The A/D conversion apparatus can execute different A/D conversion processing, by switching a first operation mode for executing pipeline type A/D conversion processing and a second operation mode for executing ΔΣ type A/D conversion processing, and shares the subtractor, the sample hold circuit and the A/D conversion apparatus in at least one stage among a plurality of stages, in the first operation mode and the second operation mode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an A / D converter that can be used as both a pipelined A / D converter and a ΔΣ A / D converter, and an IC (Integrated Circuit) chip having the A / D converter.

Conventionally, WCDMA (Wideband Code Division Multiple Access) communication systems and GSM (Global System for Mobile communications) communication systems exist as mobile phone standards. In recent years, there is a mobile phone that can perform communication using both communication methods.
FIG. 7 is a diagram comparing the specifications of the A / D converter used in the baseband receiver for WCDMA and the specifications of the A / D converter used in the baseband receiver for GSM. As shown in FIG. 7, the WCDMA A / D converter and the GSM A / D converter differ greatly in frequency band, input dynamic range, and S / N. In addition, in the A / D converter for WCDMA, a pipeline type A / D converter is widely used in order to realize a frequency band of MHz with low power consumption. On the other hand, in the A / D converter for GSM, a ΔΣ A / D converter is widely used to realize a high input dynamic range.

Here, the basic operation of a pipeline type A / D converter, which is a conventional WCDMA A / D converter, will be described with reference to FIG. FIG. 8 is a diagram showing a circuit configuration of a pipeline type A / D converter. FIG. 8 shows an example of a circuit configuration of an 8-bit output pipeline type A / D converter.
The pipeline type A / D converter 80 is configured by a plurality of stages S81 to S87 being cascade-connected. The stage S81 has an A / D converter AD81 and a D / A converter DA81. Each of the stages S82 to S86 includes a subtracter 81 and the like, a sample hold circuit S & H_81 and the like, an A / D converter AD82 and the like, and a D / A converter DA82 and the like. The stage S87 has a subtractor 86, a sample hold circuit S & H_86, and an A / D converter AD87.

  The analog input signal input to the pipeline type A / D converter 80 is input to the A / D converter AD81 in the stage S81 and the subtracter 81 in the subsequent stage S82. A 1.5-bit digital output signal is obtained from the A / D converter AD81, and this digital output signal is input to the digital adder circuit 840 and also to the D / A converter DA81. The analog output signal from the D / A converter DA81 is given to the subtractor 81 as a voltage to be subtracted by the subtractor 81. In the subtracter 81, the analog output signal of the D / A converter DA81 is subtracted from the analog input signal input to the pipeline type A / D converter 80. The output signal from the subtractor 81 is input to the sample hold circuit S & H_81, the voltage is doubled, and then input to the A / D converter AD82 and the subtracter 82 of the subsequent stage S83. A 1.5-bit digital output is obtained from the A / D converter AD82, and this digital output signal is input to the digital adder circuit 840 and the D / A converter DA82.

  Thereafter, the same processing is performed in stages S83 to S87. Thus, 1.5-bit digital data is output from the A / D converters AD81 to AD87 to the digital adder circuit 840, respectively. The digital adder circuit 840 shifts and adds these digital output signals and outputs 8-bit digital data. The 8-bit digital data thus obtained finally becomes an output value after A / D conversion.

Next, the basic operation of a ΔΣ A / D converter, which is a conventional GSM A / D converter, will be described with reference to FIG. FIG. 9 is a diagram showing a circuit configuration of a ΔΣ modulator used in a ΔΣ A / D converter. In FIG. 9, a circuit configuration of a second-order discrete ΔΣ modulator is shown as an example.
In the ΔΣ modulator 90, two stages S91 and S92 are cascade-connected. Each of the stages S91 and S92 includes a subtracter 91 and a sample and hold circuit S & H_91, and a subtractor 92 and a sample and hold circuit S & H_92.

  The analog input signal input to the ΔΣ modulator 90 is input to the subtracter 91 of the stage S91 and subjected to subtraction processing, and then input to the sample hold circuit S & H_91 which is an integrator. The output signal of the sample hold circuit S & H_91 is input to the subtracter 92 of the stage S92 and subjected to the subtraction process, and then input to the sample hold circuit S & H_92 which is an integrator. The output signal of the sample hold circuit S & H_92 is input to the A / D converter AD91, and a PWM (pulse width modulation) signal is output. The digital output signal of the A / D converter AD91 is converted into an analog signal by the D / A converter DA91, and the output signal is fed back to the stages S91 and S92. A voltage value to be subtracted in the subtracters 91 and 92 of the stages S91 and S92 is determined by the feedback signal.

The PWM signal output from the A / D converter AD91 is input to a digital filter (not shown) to obtain digital data. The digital data obtained in this way is finally an output value subjected to A / D conversion.
By the way, as described above, in recent years, there is a mobile phone capable of performing communication using both WCDMA and GSM communication systems. In the WCDMA / GSM integrated IC corresponding to both of these communication methods, there is basically a problem that two A / D converters having different specifications are required and the circuit scale becomes large. In order to solve such a problem, for example, Patent Document 1 discloses an invention of switching to a pipeline type A / D converter or a ΔΣ type A / D converter by switching an integrated circuit group while sharing a capacitor. Has been.

JP 2008-35040 A

However, in the invention described in Patent Document 1, since the pipeline type A / D converter and the ΔΣ type A / D converter share only the capacitor, the area of the entire circuit is still large. In order to make it possible to easily mount an IC chip or the like having both functions of a pipeline type A / D converter and a ΔΣ type A / D converter in a small communication device, it is possible to reduce the area of the entire circuit. This is an important issue.
The present invention has been made in view of the above-described problems, and is an A / D converter that can be used both as an A / D converter with a greatly reduced area and as a ΔΣ modulator in a ΔΣ A / D converter. And an IC chip having an A / D converter.

In order to solve the above problems, the present invention provides an A / D having a configuration in which a plurality of stages including a subtractor, a sample-and-hold circuit, an A / D converter, and a D / A converter are cascade-connected. A conversion device having a switching unit for switching between a first operation mode for executing pipeline A / D conversion processing and a second operation mode for executing ΔΣ A / D conversion processing; The subtractor, the sample hold circuit, and the A / D converter are shared in at least one of the plurality of stages in the first operation mode and the second operation mode. An A / D converter characterized by this is proposed.
In other words, not only the capacitors that make up the sample-and-hold circuit, but also basic circuits such as operational amplifiers and A / D converters are shared to execute pipeline-type A / D conversion processing and ΔΣ-type A / D conversion processing. The scale of the entire circuit in the possible A / D converter can be greatly reduced.

  Further, the stage shared in the first operation mode and the second operation mode may be a stage including a final stage among the plurality of stages. In the pipeline type A / D converter, since the input voltage is doubled in the sample and hold circuit, the influence on the overall characteristics is larger in the preceding stage, and the influence on the overall characteristics is smaller in the subsequent stage. Therefore, by sharing the circuit in the stage including the last stage, there is an effect that the influence of the error of the pipeline type A / D converter is small.

  In the first operation mode, the switching unit subtracts an output signal from the D / A converter from an output signal of the sample-and-hold circuit in the previous stage, and the sampling and holding circuit includes: The output signal from the subtractor is sampled and held, the A / D converter performs A / D conversion processing on the output signal from the sample hold circuit, and the D / A converter is the A / D converter. Output signal from the D / A converter, and in the second operation mode, the subtracter subtracts the output signal from the D / A converter from the input signal, and the sample hold circuit Samples and holds the output signal from the subtractor, the A / D converter performs A / D conversion on the output signal from the sample and hold circuit, and the D / A converter The output signal from the D converter to output to the subtracter by D / A conversion, may be adapted to switch between the time the first operation mode and the second mode of operation.

Further, the sample hold circuit and the subtractor are configured by a plurality of capacitors, a plurality of switches, and an operational amplifier, and the switching unit switches the at least one switch to switch the first The operation mode and the second operation mode may be switched. By sharing not only the capacitors that make up the sample-and-hold circuit, but also basic circuits such as operational amplifiers and A / D converters, pipeline-type and ΔΣ-type A / D can be achieved with pipeline-type A / D converters. A converter can be realized.
In addition, the present invention proposes an IC chip comprising a baseband receiving unit having the above A / D conversion device. With this configuration, the IC chip can be significantly reduced in size, so that it can be easily mounted on a small mobile phone or the like.

  As described above, according to the present invention, not only the capacitor constituting the sample and hold circuit, but also the basic circuit such as an operational amplifier and the A / D converter are shared, so that the pipeline type A / D conversion process can be performed. The scale of the entire circuit in the A / D conversion apparatus capable of executing the ΔΣ A / D conversion process can be greatly reduced.

It is the schematic which shows the structure of the A / D converter which concerns on this embodiment. It is a figure which shows the detailed structure of stage S6 and S7. A circuit configuration when the A / D converter 10 is in the WCDMA mode, the subtractor 5 and the sample hold circuit S & H_5 of the stage S6 are in the sample phase, and the subtractor 6 and the sample hold circuit S & H_6 of the stage S7 is in the hold phase is shown. FIG. A circuit configuration when the A / D converter 10 is in the WCDMA mode, the subtracter 5 and the sample hold circuit S & H_5 of the stage S6 are in the hold phase, and the subtracter 6 and the sample hold circuit S & H_6 of the stage S7 is in the sample phase is shown. FIG. A circuit configuration when the A / D converter 10 is in the GSM mode, the subtracter 5 and the sample hold circuit S & H_5 of the stage S6 are in the sample phase, and the subtracter 6 and the sample hold circuit S & H_6 of the stage S7 are in the hold phase is shown. FIG. A circuit configuration when the A / D converter 10 is in the GSM mode, the subtracter 5 and the sample hold circuit S & H_5 of the stage S6 are in the hold phase, and the subtractor 6 and the sample hold circuit S & H_6 of the stage S7 is in the sample phase is shown. FIG. It is a figure which compares the specification of the A / D converter used for the baseband receiving part for WCDMA, and the specification of the A / D converter used for the baseband receiving part for GSM. It is a figure which shows an example of the circuit structure of a general pipeline type A / D converter. It is a figure which shows an example of the circuit structure of the delta-sigma modulator used for a general delta-sigma type A / D converter.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure referred below, an equivalent part is shown with the same code | symbol.
(Configuration of A / D converter)
First, the configuration of the A / D conversion device according to the present embodiment will be described with reference to FIG. FIG. 1 is a schematic diagram illustrating a configuration of an A / D conversion device according to the present embodiment. In the A / D converter 10, seven stages S1, S2, S3, S4, S5, S6, and S7 are connected in cascade, and a pipeline A / D converter is realized by the stages S1 to S7. A ΔΣ modulator of the ΔΣ A / D converter is realized by S7. Further, the configurations of the stages S1 to S7 are obtained by adding a new D / A converter DA7 to the conventional pipeline type A / D converter illustrated in FIG. That is, the stage S1 includes an A / D converter AD1 and a D / A converter DA1, and the stages S2 to S7 include a subtractor 1 and the like, a sample hold circuit S & H_1, and the A / D converter AD2 and the like, respectively. And a D / A converter DA2.

  The A / D conversion device 10 includes switches Wa, Wb, Wc, Wd, Ga, Gb, and Gc. The switches Wa, Wb, Wc, and Wd are switches that are turned on when the A / D converter 10 operates in the WCDMA mode, that is, as a pipelined A / D converter. The switches Ga, Gb, and Gc This is a switch that is turned on when the D converter 10 operates in the GSM mode, that is, as the ΔΣ modulator of the ΔΣ A / D converter.

  Among these switches, the A / D converter 10 is switched to the WCDMA mode or the GSM mode mainly by the switches Wa, Wd, and Ga. That is, when the switches Wa and Wd are turned off and the switch Ga is turned on, the stages S1 to S5 are disconnected from the entire configuration, and the A / D converter 10 is substantially configured only by the stages S6 and S7. Operates as a vessel. More specifically, the switches Wa and Ga are provided on the input signal line to the A / D converter 10, and the switch Wa guides the WCDMA signal input to the A / D converter 10 to the stage S1. The switch Ga is a switch for guiding the GSM signal input to the A / D converter 10 to the stage S6. The switch Wd is provided on the line from the sample hold circuit S & H_4 of the stage S5 to the subtractor 5 of the stage S6, and guides an output signal from the sample hold circuit S & H_4 of the stage S5 to the subtracter 5 of the stage S6. It is a switch.

  The switches Wb and Wc are on the line from the D / A converter DA5 of the stage S5 to the subtracter 5 of the stage S6, and from the D / A converter DA6 of the stage S6 to the subtracter 6 of the stage S7, respectively. The switches are provided above and are used to input the output signals from the D / A converters DA5 and DA6 to the subtractor 5 and the subtractor 6 in the subsequent stage to be subtracted, respectively. The switches Gb and Gc are provided on the lines from the new D / A converter DA7 to the subtracter 5 of the stage S6 and the subtracter 6 of the stage S7, respectively. This is a switch for feeding back an output signal from the DA 7 to the subtracter 5 and the subtractor 6 to make a signal to be subtracted.

  Further, the mechanism in the case where the A / D converter 10 according to the present embodiment operates as a pipeline type A / D converter or a ΔΣ modulator is the same as the conventional A / D converters illustrated in FIGS. 8 and 9. It is. That is, when operating as a pipeline type A / D converter, in each of the stages S1 to S7, the subtractor 1 or the like subtracts the output signal of the D / A converter DA1 or the like of the preceding stage from the input signal. The signal subjected to the subtraction processing is doubled in voltage in the sample hold circuit S & H_1 and the like and input to the A / D converter AD2 in the same stage and the subtracter in the subsequent stage. The 1.5-bit digital output obtained from the A / D converter AD2 or the like is input to the digital adder circuit 140 and shift-added, and the obtained 8-bit digital data is finally output by the A / D converter 10. The output value is A / D converted.

  In the operation of the A / D converter 10 as the ΔΣ modulator, in stages S6 and S7, the subtractor 5 and the subtracter 6 subtract the output signal of the D / A converter DA7 from the input signal. The subtracted signals are input to A / D converters AD6 and AD7 via sample and hold circuits S & H_5 and S & H_6, respectively, and A / D converted. Further, the PWM signal output from the A / D converter AD7 of the stage 7 is a signal that is ΔΣ modulated by the A / D converter 10, and this PWM signal is input to a digital filter (not shown). Thus, the final output value of A / D conversion is obtained.

  As described above, the A / D conversion device 10 according to the present embodiment shares not only the capacitor constituting the sample hold circuit but also the basic circuit such as the operational amplifier and the A / D converter in two different A / D conversion modes. Therefore, pipeline-type and ΔΣ-type A / D converters can be realized with the circuit scale of the pipeline-type A / D converter. The D / A converter DA7 is a circuit that operates only in the GSM mode. However, if the output from the A / D converter AD7 is, for example, about 1 to 2 bits, a simple logic circuit is sufficient. The effect on the overall area is negligible.

In this example, the circuit is shared based on the circuit configuration of the pipeline type A / D converter so that the last stage S6 and stage S7 also operate as a secondary ΔΣ modulator. Another two consecutive stages may be shared. However, in the pipeline type A / D converter, the input voltage is doubled in the sample-and-hold circuit, and the influence on the overall characteristics is greater in the preceding stage, and the influence on the overall characteristics is less in the subsequent stage. Therefore, by sharing the circuit in the last stage as in this example, there is an advantage that the influence of the error of the pipeline type A / D converter is small.
Further, when the circuit is shared so that the A / D converter 10 operates as an nth-order (n is an integer of 1 or more) ΔΣ modulator, it is configured to share n consecutive stages. That's fine.

(Detailed configuration of stages S6 and S7)
Next, the detailed configuration of the stages S6 and S7 will be described with reference to FIG. FIG. 2 is a diagram showing a detailed configuration of the stages S6 and S7.
The subtractor 5 and the sample and hold circuit S & H_5 of the stage S6 are composed of a CAP (capacitor) group and a switch group CS1, and an operational amplifier OP1. Further, the subtractor 6 and the sample hold circuit S & H_6 of the stage S7 are composed of a CAP group and a switch group CS2, and an operational amplifier OP2.

  In the WCDMA mode, WCDMA ON control signals 201a and 201b are input to stages S6 and S7. In the GSM mode, GSM ON control signals 202a and 202b are input to the stages S6 and S7. In accordance with these control signals, the combination of switches that are turned on in the switch group CS1 and the switch group CS2 changes. As a result, in the subtracter 5 and the sample hold circuit S & H_5, and in the subtractor 6 and the sample hold circuit S & H_6. The overall configuration changes, and each is switched to a pipeline type A / D converter circuit and a ΔΣ modulator circuit.

  More specifically, in the WCDMA mode, the CAP group and switch group CS1, and the CAP group and switch group CS2 operate as follows. That is, the CAP group and the switch group CS1 sample the output signal of the sample hold circuit S & H_4 and the output signal of the D / A converter DA5 in the sample phase for sampling the signal, and in the hold phase for holding the sampled signal. After the sampled output signal of the sample and hold circuit S & H_4 is doubled, a signal obtained by subtracting the output signal of the D / A converter DA5 is output to the operational amplifier OP1. The CAP group and the switch group CS2 sample the output signal of the sample hold circuit S & H_5 and the output signal of the D / A converter DA6 in the sample phase, and sample the output signal of the sample hold circuit S & H_5 in the hold phase. After being doubled, a signal obtained by subtracting the output signal of the D / A converter DA6 is output to the operational amplifier OP2.

  In the GSM mode, the CAP group and switch group CS1, and the CAP group and switch group CS2 operate as follows. That is, the CAP group and the switch group CS1 sample the GSM input signal input to the A / D converter 10 and the output signal of the D / A converter DA7 in the sample phase, and sample the GSM input in the hold phase. A signal obtained by subtracting the output signal of the D / A converter DA7 from the signal is output to the operational amplifier OP1. Further, the CAP group and the switch group CS2 sample the output signal of the sample hold circuit S & H_5 and the output signal of the D / A converter DA7 in the sample phase, and from the sampled output signal of the sample hold circuit S & H_5 in the hold phase. A signal obtained by subtracting the output signal of the D / A converter DA7 is output to the operational amplifier OP2.

(Specific circuit configuration of stages S6 and S7)
Next, specific circuit configurations of the stages S6 and S7 will be described with reference to FIGS. 3 and 4 are diagrams showing circuit configurations of stages S6 and S7 when the A / D conversion apparatus 10 is in the WCDMA mode. FIG. 3 shows a circuit configuration when the subtracter 5 and the sample and hold circuit S & H_5 of the stage S6 are in the sample phase, and the subtracter 6 and the sample and hold circuit S & H_6 of the stage S7 are in the hold phase, and FIG. The circuit configuration in the case where the device 5 and the sample and hold circuit S & H_5 are in the hold phase and the subtracter 6 and the sample and hold circuit S & H_6 in the stage S7 are in the sample phase is shown. That is, the A / D conversion apparatus 10 implements the processes in the stages S6 and S7 in the WCDMA mode by alternately executing the respective phases realized by the circuit configurations shown in FIGS.

  5 and 6 are diagrams showing circuit configurations of stages S6 and S7 when the A / D converter 10 is in the GSM mode. FIG. 5 shows a circuit configuration when the subtracter 5 and the sample and hold circuit S & H_5 of the stage S6 are in the sample phase, and the subtracter 6 and the sample and hold circuit S & H_6 of the stage S7 are in the hold phase, and FIG. 6 shows the subtraction of the stage S6. The circuit configuration in the case where the device 5 and the sample and hold circuit S & H_5 are in the hold phase and the subtracter 6 and the sample and hold circuit S & H_6 in the stage S7 are in the sample phase is shown. That is, the A / D conversion apparatus 10 implements the processes in the stages S6 and S7 in the GSM mode by alternately executing the phases realized by the circuit configurations shown in FIGS.

  Here, in the circuits shown in FIGS. 3 to 6, the following points are common. First, as input sampling clocks, there are WΦ1, WΦ2, GΦ1, GΦ2, Φ1, and Φ2. Further, WΦ1 and WΦ2, GΦ1 and GΦ2, and Φ1 and Φ2 are in an antiphase relationship with each other. WΦ1 and WΦ2 operate only in WCDMA mode. In GSM mode, in principle, both of them fall to 'low' at the same time (in negative logic (PMOS (Positive-channel Metal-Oxide Semiconductor) switch) becomes 'high') . However, the switches SW33 and SW42 to be described later remain ‘high’ (in the case of negative logic, ‘low’) in the GSM mode. GΦ1 and GΦ2 operate only in the GSM mode, and both simultaneously fall to 'low' in the WCDMA mode (or 'high' if negative logic). Φ1 and Φ2 operate in both the WCDMA mode and the GSM mode.

  Further, the following switches exist as switches that operate according to these sampling clocks. That is, the switches SW31, SW32, and SW33 operate according to the clock WΦ1, and the switches SW41, SW42, and SW43 operate according to the clock WΦ2. The switches SW51 and SW52 operate according to the clock GΦ1, and the switches SW61 and SW62 operate according to the clock GΦ2. The switches SW11 and SW12 operate according to the clock Φ1, and the switches SW21 and SW22 operate according to the clock Φ2.

The switches W1, W2, W3, W4, W5, W6, and W7 are always ON in the WCDMA mode, and are always OFF in the GSM mode. The switches G1, G2, and G3 are always OFF in the WCDMA mode, and are always ON in the GSM mode.
Further, the values of the capacitors C1, C2, C3, C4, C5, C6, and C7 have a relationship of C1 + C2 = C3 + C4 + C5, C6 = 2C7. The transfer function of the ΔΣ modulator can be determined by setting the values of the capacitors C1 to C7 to appropriate ratios.

Based on the above, the operation of stages S6 and S7 in each mode will be described below.
(Operations of stages S6 and S7 in WCDMA mode)
First, referring to FIG. 3, the A / D converter 10 is in the WCDMA mode, the subtracter 5 and the sample hold circuit S & H_5 in FIG. 1 at the stage S6 are in the sample phase, and the subtracter 6 and the sample in the stage S7 in FIG. An operation when the hold circuit S & H_6 is in the hold phase will be described. In the case of this example, for the sample clock, the Φ1 phase and WΦ1 phase switches are turned on, and the Φ2 phase and WΦ2 phase switches are turned off. The switch Wp (p = 1, 2, 3, 4, 5, 6, 7) is turned on, and the switch Gq (q = 1, 2) is turned off. Further, FIG. 3 shows a state in which an output signal from DA6 of stage S6 is input to capacitor C7 of stage S7 and connected so as to operate as a subtracter (subtracter 6 in FIG. 1).

Further, in FIG. 3 and FIG. 4 described later, the capacitors C1 and C2 and the capacitors C3 to C5 are connected in parallel by the switches W1 to W6, respectively.
In FIG. 3, the WCDMA signal output from the sample hold circuit S & H_4 of the stage S5 in FIG. 1 is selected as the input signal when the switch Wa is turned on. The WCDMA signal from the sample and hold circuit S & H_4 is sampled by capacitors C1 and C2 and capacitors C3 to C5 connected in parallel by switches W1 to W6 (solid line 30). That is, this realizes the sample phase in the subtracter 5 and the sample hold circuit S & H_5 in FIG.

  At the same time, the charge charged in the capacitor C6 by the operational amplifier OP2 is held and input to the A / D converter AD7 (solid line 31). The output from the operational amplifier OP2 is fed back to the inverting input terminal via the capacitor C6 (broken line 32). The charge charged in the capacitor C6 is the charge sampled in the capacitor C6 in the phase described in detail later in FIG. 4, and corresponds to the output signal from the sample hold circuit S & H_5 in FIG. 1 of the stage S6. To do. This will be described in detail later. At this time, the output signal of the D / A converter DA6 is applied to the capacitor C7 (solid line 33). As described above, the values of the capacitors C6 and C7 have a relationship of C6 = 2C7. Accordingly, in the operational amplifier OP2, the output signal of the sample hold circuit S & H_5 in FIG. A process of subtracting the output signal of the converter DA6 is executed. That is, the hold phase in the subtracter 6 and the sample hold circuit S & H_6 in FIG.

  Next, referring to FIG. 4, the A / D converter 10 is in the WCDMA mode, the subtracter 5 and the sample hold circuit S & H_5 in FIG. 1 of the stage S6 are in the hold phase, and the subtractor 6 in FIG. The operation when the sample hold circuit S & H_6 is in the sample phase will be described. In the case of this example, for the sample clock, the Φ1 phase and WΦ1 phase switches are turned OFF, and the Φ2 phase and WΦ2 phase switches are turned ON. As in FIG. 3, the switch Wp is turned on and the switch Gq is turned off. FIG. 4 shows a state in which an output signal from DA5 of stage S5 is input to capacitors C3 to C5 of stage S6 and connected so as to operate as a subtracter (subtracter 5 in FIG. 1).

As in FIG. 3, as the input signal, when the switch Wa is turned on, the WCDMA signal output from the sample hold circuit S & H_4 of the stage S5 in FIG. 1 is selected. Further, when the switches SW11 and SW12 are turned OFF and the switch SW22 is turned ON, the charges charged in the capacitors C1 and C2 and the capacitors C3 to C5 are held in the operational amplifier OP1 and are supplied to the A / D converter AD6. Input (solid line 40). When the switch SW21 is turned on, the output from the operational amplifier OP1 is fed back to the inverting input terminal via the capacitors C1 and C2 (broken line 41). The charges charged in the capacitors C1 and C2 and the capacitors C3 to C5 are charges sampled in the capacitors C1 and C2 and the capacitors C3 to C5 in the phase described with reference to FIG. This corresponds to the output signal from the sample and hold circuit S & H_4 of the stage S5. At this time, the output signal of the D / A converter DA5 is applied to the capacitors C3 to C5 (solid line 42). As described above, since the values of the capacitors C1 to C5 have the relationship of C1 + C2 = C3 + C4 + C5, the operational amplifier OP1 doubles the output signal of the sample hold circuit S & H_4 in FIG. A process of subtracting the output signal of the converter DA5 is executed. In other words, the hold phase in the subtracter 5 and the sample hold circuit S & H_5 in FIG.
At the same time, when the switch SW42 is turned on, the output signal of the operational amplifier OP1 is sampled in the capacitor C6 (solid line 43). That is, this realizes the sample phase in the subtracter 6 and the sample hold circuit S & H_6 of the stage S7 in FIG.

(Operations of stages S6 and S7 in GSM mode)
Next, referring to FIG. 5, the A / D converter 10 is in the GSM mode, the subtracter 5 and the sample hold circuit S & H_5 in FIG. 1 of the stage S6 are in the sample phase, the subtractor 6 in FIG. The operation when the sample and hold circuit S & H_6 is in the hold phase will be described. In this example, for the sample clock, the Φ1 phase and GΦ1 phase switches are turned on, and the Φ2 phase and GΦ2 phase switches are turned off. Further, the switch Wp is turned off and the switch Gq is turned on. In addition, both WΦ1 and WΦ2 fall to “low” at the same time (in principle, “high” if negative logic (PMOS switch)). However, the switches SW33 and SW42 exceptionally remain “high” (“low” if negative logic) (the same applies to FIG. 6 described later). The A / D converter AD6 is OFF in the GSM mode and does not operate. In FIG. 5, output signals from DA7 of stage S7 are input to capacitor C3 of stage S6 and capacitor C4 of stage S7, and connected so as to operate as subtracter 5 and subtracter 6 in FIG. 1, respectively. It shows the state that was done.

  As the input signal, the GSM signal input to the A / D conversion device 10 is selected when the switch Ga is turned ON. This GSM signal is sampled by the capacitor C1 through the switch SW11 (solid line 50). Further, the output signal from the D / A converter DA7 is sampled by the capacitor C3 (broken line 51). The output of the operational amplifier OP1 is fed back to the inverting input terminal via the capacitor C6 (broken line 55). That is, as a result, the sample and hold circuit S & H_5 in FIG. 1 functions as an integrator, and the sample phase in the subtracter 5 and the sample and hold circuit S & H_5 in FIG.

  At the same time, the charges charged in the capacitors C2, C4, and C7 by the operational amplifier OP2 are held and input to the A / D converter AD7 (solid line 52). The output from the operational amplifier OP2 is fed back to the inverting input terminal via the capacitor C7 (dashed line 53). The charges charged in the capacitors C2 and C4 are the charges sampled in the capacitors C2 and C4 in the phase described in detail later with reference to FIG. 6, and the charges from the sample hold circuit S & H_5 in FIG. This corresponds to the output signal. This will be described in detail later. At this time, the output signal of the D / A converter DA7 is applied to the capacitor C4 (solid line 54). As a result, the operational amplifier OP2 executes a process of subtracting the output signal of the D / A converter DA7 from the output signal of the sample hold circuit S & H_5 of FIG. That is, the hold phase in the subtracter 6 and the sample hold circuit S & H_6 in FIG.

  Next, referring to FIG. 6, the A / D converter 10 is in the GSM mode, the subtracter 5 and the sample hold circuit S & H_5 in FIG. 1 of the stage S6 are in the hold phase, and the subtractor 6 in FIG. An operation when the sample hold circuit S & H_6 is in the sample phase will be described. In this example, for the sample clock, the Φ1 phase and GΦ1 phase switches are turned OFF, and the Φ2 phase and GΦ2 phase switches are turned ON. As in FIG. 5, the switch Wp is turned off and the switch Gq is turned on. The A / D converter AD6 is OFF in the GSM mode and does not operate. In FIG. 6, the output signals from DA7 of stage S7 are input to capacitor C3 of stage S6 and capacitor C4 of stage S7, and are connected so as to operate as subtracter 5 and subtracter 6 in FIG. 1, respectively. It shows the state that was done.

  As in FIG. 5, the GSM signal to be input to the A / D conversion device 10 is selected as the input signal when the switch Ga is turned on. Further, when the switches SW11 and SW12 are turned off and the switch SW22 is turned on, the electric charges charged in the capacitors C1, C3, and C6 are held in the operational amplifier OP1 (solid line 60). The output from the operational amplifier OP1 is fed back to the inverting input terminal via the switch SW42 and the capacitor C6 (solid line 61). The charges charged in the capacitors C1 and C3 are the charges sampled in the capacitors C1 and C3 in the phase described with reference to FIG. 5, and are respectively obtained from the GSM input signal and the D / A converter DA7. This corresponds to the output signal. At this time, the output signal of the D / A converter DA7 is applied to the capacitor C3 (solid line 62). As a result, the operational amplifier OP1 executes a process of subtracting the output signal of the D / A converter DA7 from the GSM input signal. In other words, the hold phase in the subtracter 5 and the sample hold circuit S & H_5 in FIG.

At the same time, when the switch SW21 is turned ON, the output signal of the operational amplifier OP1 is sampled in the capacitor C2 (broken line 63). Further, the output of the D / A converter DA7 is sampled in the capacitor C4 (broken line 64). The output of the operational amplifier OP2 is fed back to the inverting input terminal via the capacitor C7 (dashed line 65). In other words, the sample hold circuit S & H_6 in FIG. 1 functions as an integrator, and the sample phase in the subtractor 6 and the sample hold circuit S & H_6 in FIG.
Each of the capacitors C1 to C7 shown in FIG. 3 to FIG. 6 is shown as one capacitor in each figure. However, in an actual circuit, one capacitor having a necessary capacity is provided as in the figure. Alternatively, in an actual circuit, each of the capacitors C1 to C7 having a necessary capacity may be realized by connecting a plurality of capacitor groups having small capacities in parallel.

(Summary)
As described above, according to the present invention, not only the capacitor constituting the sample and hold circuit, but also the basic circuit such as an operational amplifier and the A / D converter are shared, so that the pipeline type A / D conversion process can be performed. The scale of the entire circuit in the A / D conversion apparatus capable of executing the ΔΣ A / D conversion process can be greatly reduced.

10 A / D converters S1, S2, S3, S4, S5, S6, S7 Stages AD1, AD2, AD3, AD4, AD5, AD6, AD7 A / D converters DA1, DA2, DA3, DA4, DA5, DA6, DA7 D / A converter S & H_1, S & H_2, S & H_3, S & H_4, S & H_5, S & H_6 Sample hold circuit 140 Digital adder circuit Wa, Wb, Wc, Wd switch Ga, Gb, Gc switch CS1, CS2 CAP group and switch group OP1, OP2 operational amplifier W1, W2, W3, W4, W5, W6, W7 switches G1, G2, G3 switches SW31, SW32, SW33 Switches that operate according to the clock WΦ1 SW41, SW42, SW43 Switches that operate according to the clock WΦ2 SW51, SW52 Switches SW61 and SW62 that operate according to the lock GΦ1 Switches SW11 and SW12 that operate according to the clock GΦ2 Switches SW21 and SW22 that operate according to the clock Φ1 Switches C1, C2, C3, C4, and C5 that operate according to the clock Φ2 , C6, C7 capacitors

Claims (5)

An A / D conversion apparatus having a configuration in which a plurality of stages including a subtractor, a sample hold circuit, an A / D converter, and a D / A converter are connected in cascade.
A switching unit that switches between a first operation mode for executing pipeline-type A / D conversion processing and a second operation mode for executing ΔΣ-type A / D conversion processing;
Sharing the subtractor, the sample hold circuit, and the A / D converter in at least one of the plurality of stages in the first operation mode and the second operation mode. An A / D converter characterized by the above.   2. The stage according to claim 1, wherein a stage shared in the first operation mode and the second operation mode is a stage including a final stage among the plurality of stages. / D converter. The switching unit is
In the first operation mode,
The subtracter subtracts the output signal from the D / A converter from the output signal of the sample hold circuit in the previous stage, and the sampling hold circuit samples and holds the output signal from the subtractor, The A / D converter performs A / D conversion processing on the output signal from the sample hold circuit, the D / A converter performs D / A conversion processing on the output signal from the A / D converter, and
In the second operation mode,
The subtracter subtracts the output signal from the D / A converter from the input signal, the sample hold circuit samples and holds the output signal from the subtractor, and the A / D converter A / D conversion processing is performed on the output signal from the sample hold circuit, and the D / A converter performs D / A conversion processing on the output signal from the A / D converter and outputs it to the subtractor. The A / D conversion apparatus according to claim 1, wherein the A / D conversion apparatus switches between the first operation mode and the second operation mode. The sample-and-hold circuit and the subtractor include a plurality of capacitors, a plurality of switches, and one operational amplifier.
The A / according to any one of claims 1 to 3, wherein the switching unit switches between the first operation mode and the second operation mode by switching at least one of the switches. D converter.   An IC chip comprising a baseband receiving unit having the A / D conversion device according to claim 1.

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