KR20080052270A - Delta sigma modulator for multi-bit - Google Patents

Abstract

A multi-bit delta sigma modulator is provided to be applied for a multi-bit high speed operation by delaying a feedback signal as much as one clock using a delayer and a differential delayer. A multi-bit delta sigma modulator includes a first integrator(301), a second integrator(303), an analog digital converter(305), a delayer(309), and a differential delayer(311). The first integrator integrates an input signal. The second integrator receives an input of the signal feedbacked from the differential delayer, and compensates for the delayed signal component. The analog digital converter converts the integrated signal into a digital signal. The delayer delays the signal outputted from the analog digital converter. The differential delayer differentiates and delays the signal outputted from the analog digital converter.

Description

Delta Sigma modulator for multi-bit

The present invention relates to a multi-bit delta sigma modulator.

The present invention is derived from the research conducted as part of the IT new growth engine core technology development project of the Ministry of Information and Communication and the Ministry of Information and Communication Research and Development. [Task Management Number: 2005-S-073-02, Title: Nano-device-based circuit design technology Development].

Delta sigma modulators, which have been developed since the 1960s, have been studied a lot by the development of wireless communication.

In particular, delta-sigma converters capable of wideband multi-bit processing without reducing the signal-to-noise ratio have been studied in recent years. Its use extends to a wide range of fields such as wireless communications and radar.

1 is a diagram schematically showing the structure of a conventional secondary delta sigma modulator.

Referring to FIG. 1, the delta sigma modulator includes a first integrator 101, a second integrator 103, an analog digital converter (ADC) 105, and a digital analog converter (DAC) ( 107).

The delta sigma modulator is a circuit that can minimize the quantization noise generated in the process of converting an analog signal to a digital signal in a low frequency band, which is widely used in a general analog digital modulator. In the case of such a sigma modulator, the higher the over sampling ratio (OSR), the better the reduction characteristic of the quantization noise (q).

However, such a structure requires an analog block having low distortion characteristics in order to satisfy the distortion characteristics of the system when the oversampling ratio (OSR) is low. Especially in broadband applications, the analog circuit part must have both high speed and low distortion characteristics, which is very difficult by design.

2 is a diagram schematically illustrating a structure of a delta sigma modulator having a conventional low distortion characteristic.

Referring to FIG. 2, the sigma delta sigma modulator includes a first integrator 201, a second integrator 203, an analog to digital converter 205, and a digital to analog converter 209. It further includes scrambler logic 207.

This low distortion delta sigma modulator has a structure in which the input analog signal u is directly input to the analog-to-digital converter 205. In this case, the first integrator 201 and the second integrator 203 can process only quantization noise, and thus have excellent input signal dependent distortion characteristics.

The scrambler logic 207 is a circuit added to improve the device characteristics of the DAC and various nonlinear characteristics of the process that may occur in the DAC when the circuit is directly implemented. This scrambler logic 207 has a delay component as a digital circuit.

However, when such a low distortion delta sigma modulator also processes a multi-bit signal, a fast signal feedback is required to remove the analog input signal (u) input to the first integrator 201 and thus there is no delay digital. Translator 205 or scrambler logic 207 is required.

That is, during one clock period, the input of the analog-to-digital converter 205 must be able to pass both the analog-to-digital converter 205 scrambler logic 207 and the first integrator.

In this case, if there is a delay component during signal conversion in the analog-to-digital converter 205 and the scrambler logic 207, it is difficult to operate at high speed in a multi-bit structure.

Therefore, there has been a need for a structure of a delta sigma modulator with low distortion characteristics and suitable for multi-bit high speed operation.

An object of the present invention is to provide a delta sigma modulator having low distortion characteristics and suitable for multi-bit high speed operation.

It is also an object of the present invention to provide a delta sigma modulator suitable for multi-bit high speed operation by delaying a feedback signal by one clock using a delay and a differential delay.

In order to achieve the above objects, according to an aspect of the present invention, the first integrator for integrating an input signal, an analog-to-digital converter for converting the integrated signal into a digital signal, delaying the signal output from the analog-to-digital converter A delta sigma modulator including a delay and a derivative delay for differentially delaying a signal output from the analog-to-digital converter can be provided.

In the preferred embodiment, the delay and derivative delay may be characterized in that the delay and differential delay of the signal output from the analog to digital converter to feed back to the digital analog converter. The apparatus may further include a second integrator that receives an input of a signal fed back from the differential delayer and compensates for the delayed signal component.

In addition, the signal input to the first integrator may be characterized in that it comprises a signal sum of the signals fed back from the delay and derivative delay. In addition, the sum of the signals fed back from the delay and the derivative delay may be characterized in that the analog-to-digital converter is converted into an analog signal and input to the first integrator.

The analog-to-digital converter may be input by adding the input signal of the first integrator, the output signal of the first integrator, the difference signal of the signal of the differential delay unit, and the output signal of the second integrator. The second integrator may include a signal output from the first integrator as an input. In addition, the second integrator may include an input of a difference signal between the differential delay unit and the output signal of the first integrator.

According to another aspect of the present invention, a first integrator receiving an analog input signal, a second integrator receiving the sum of the signal input from the first integrator and the signal input from the second digital analog converter, the first integrator The sum of the output signal and the analog input signal of the third digital analog converter, the second integrator, and the third digital analog converter to amplify the sum of the signal output from the second digital analog converter and the signal input from the second digital analog converter The analog-to-digital converter for converting, the delayer for delaying the output signal of the analog-to-digital converter, the derivative delayer for delaying the delay, the signals output from the delayer and the derivative delayer are summed and converted into an analog signal and the converted signal is First digital analog input to the first integrator It may call and converts the new arc signal output from the differential analog delay and providing a delta sigma modulator and a second digital-to-analog converter to input the converted signal to the second integrator.

According to the present invention, it is possible to provide a delta sigma modulator having low distortion characteristics and suitable for multi-bit high speed operation.

In addition, the present invention provides a delta sigma modulator suitable for multi-bit high speed operation by delaying a feedback signal by one clock using a delay and a differential delay.

3 is a diagram illustrating a structure of a delta sigma modulator to which the present invention is applied.

Referring to FIG. 3, the delta sigma modulator includes a first integrator 301, a second integrator 303, an analog to digital converter 305, a first to digital analog converter 313, a second to digital analog converter 315, and A third digital analog converter 307, a delay unit 309, differential delay units 309 and 311, and scrambler logic 317 are included.

The first integrator 301 has a function of integrating the difference between the analog input signal u and the feedback signal. In this case, the feedback signal is a signal output through the first digital-to-analog converter 313 by adding the signals of the delayers 309 and the derivative delayers 309 and 311.

In this way, the signal e1 input to the first integrator 301 and the output signal x1 are

[Equation 1]

Is derived as:

Where Q (z) is quantization noise and Y (z) is output signal. z is the value of the variable in the z-transformation.

Looking at the above equation, since the modulator output term of the output signal x1 (z) of the integrator is differentiated, it can be expected that the magnitude of the signal component will be greatly reduced.

This reduced signal component also significantly reduces the nonlinear nature of the integrator. Therefore, the influence of signal distortion can be reduced.

The second integrator 303 integrates the difference between the output signal x1 of the first integrator 301 and the feedback signal output from the second digital-to-analog converter 315 to integrate the input signal e2.

In this case, the signal e2 input to the second integrator 303 includes only quantization noise.

[Equation 2]

Accordingly, the second integrator 303 processes only quantization noise so that signal distortion does not occur.

The third digital-to-analog converter 307 amplifies the same signal e2 as the signal input to the second integrator and inputs the same to the analog-to-digital converter 305.

In the third digital-to-analog converter 307, since the input signal does not include the analog input signal component u, distortion due to the input signal does not occur.

The analog-to-digital converter 305 receives an input signal by adding an output signal x2 of the second integrator 303, an output x3 of the third digital analog converter 307, and an analog input signal u to receive the input signal. It is in charge of outputting.

At this time, the output signal is fed back to the initial input stage, and the feedback path is divided into two paths: a path passing only the delay unit 309 and a path passing through the differential delay units 309 and 311.

The differential group delay (309, 311) is a signal input to the Z ^-1 components of the reference numeral 311 according to the feedback path of the phase diagram, because this formula Y-YZ ^-1 signal outputted from the reference numeral 311 is a YZ ^-1 (1-Z ^-1 ), which means that the derivative delay factor is fed back.

The scrambler logic 317 is a circuit added to improve device characteristics that may occur when the circuit is directly implemented, or various nonlinear characteristics in the process. This scrambler logic 317 has a delay component as a digital circuit.

In the circuit configured as described above, the feedback components have both delay and derivative delay components, so the feedback signal has a clock cycle time until it is input to the digital-to-analog converter, so that even if a delay occurs in the scrambler logic Can be processed. Therefore, even if the multi-bit configuration with low distortion characteristics, regardless of the conversion delay time of the scrambler or analog-to-digital converter.

4 is a block diagram of a delta sigma modulator according to an exemplary embodiment of the present invention.

Referring to FIG. 4, this is a circuit implementing a second delta sigma modulator using a switched capacitor circuit as an exemplary embodiment of the present invention. For reference, the present invention may be implemented in other types of circuits such as continuous time circuits in addition to the switched capacitors as shown in the drawing.

Referring to this figure, a first integrator 401, a second integrator 403, a third digital analog converter 407, an analog to digital converter 405, a digital differentiator 409 and a scrambler logic 411 It can be seen that the basic configuration is the same.

The integrators 401 and 403 and the third digital-to-analog converter 407 are implemented using op amps, and the signal subtractor and adder of FIG. 3 is a switched capacitor coupled to the front end of each op amp. do.

Since the basic operation of this drawing is the same as that described with reference to FIG. 3, the operation of the integrator and the third digital-to-analog converter will be omitted, and the relationship between the feedback signal and the clock will be described.

Looking at the drawings it can be seen that the number of 1 or 2 is marked on each switch. Each of these numbers represents the clock phase of the circuit in which the switch operates. That is, the switch labeled 1 operates when the clock phase is 1, and the switch labeled 2 operates when the clock phase is 2. Each clock phase is indicated at the bottom of the figure.

Here, looking at the switch operation of the figure to identify the timing problem, which is one of the characteristics of the present invention, the input signal q-in input to the analog-to-digital converter 405 is a charge charged in the capacitors (411, 413, 415) The capacitors 411, 413, 415 are discharged when the clock phase is 2, and are connected to the respective integrators and the digital analog converter when the clock phase is 1. The analog-to-digital converter input node thus connected is connected to the analog-to-digital converter 405 by a switch 417 to which the q-in signal is input when the clock phase is 1, and the signal input to the connection node is connected to the clock phase 1 signal. At the end, it is converted into digital signal and output. Thereafter, the scrambler logic 411 operates at the clock phase 2, and the signals output at the next clock phase 1 and the clock phase 2 are fed back and input again to the digital-to-analog converter.

In this circuit, since the scrambler logic 411 operates at the time of the clock phase 2 and the analog-to-digital converter 405 operates at the time of the clock phase 1, the operation time delay of the analog-to-digital converter or the scrambler logic ( The operation delay of 411 significantly alleviates the clock timing problem in which the circuit malfunctions.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

1 is a diagram showing the structure of a conventional secondary delta sigma modulator.

2 is a simplified diagram illustrating a structure of a conventional delta sigma modulator having low distortion characteristics.

3 is a diagram illustrating a structure of a delta sigma modulator to which the present invention is applied.

4 is a block diagram of a delta sigma modulator according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

301: first integrator

303: second integrator

305: analog to digital converter

313: first digital to analog converter

315: second digital to analog converter

307: third digital to analog converter

309: delay

309, 311: derivative delay

317: Scrambler Logic

Claims (9)

A first integrator for integrating the input signal; An analog-digital converter for converting the integrated signal into a digital signal; A delay unit for delaying a signal output from the analog-to-digital converter; Derivative delayer for differentially delaying the signal output from the analog-to-digital converter Delta sigma modulator comprising a. The method of claim 1, The delay unit and the derivative delay unit respectively delay and differential delay the signal output from the analog-to-digital converter to feed back to the digital-to-analog converter. Delta sigma modulator characterized in that. The method of claim 1, A second integrator that receives an input of a feedback signal from the differential delayer to compensate for the delayed signal component Delta sigma modulator characterized in that it further comprises. The method of claim 1, The signal input to the first integrator includes a sum of signals fed back from the delayer and the derivative delayer; Delta sigma modulator characterized in that. The method of claim 4, wherein The sum of the signals fed back from the delay unit and the derivative delay unit is converted into an analog signal by a digital-to-analog converter and input to the first integrator Delta sigma modulator characterized in that. The method of claim 3, The analog-to-digital converter receives the input signal of the first integrator, the difference signal between the output signal of the first integrator and the signal of the differential delay and the output signal of the second integrator Delta sigma modulator characterized in that. The method of claim 3, The second integrator comprises a signal output from the first integrator as an input Delta sigma modulator characterized in that. The method of claim 3, The second integrator comprises as an input a difference signal between the differential delay and the output signal of the first integrator Delta sigma modulator characterized in that. A first integrator receiving an analog input signal; A second integrator receiving the sum of the signal input from the first integrator and the signal input from the second digital-to-analog converter; A third digital analog converter for amplifying a sum of signals output from the first integrator and signals input from the second digital analog converter; An analog-to-digital converter that adds both the output signal of the second integrator and the third digital-to-analog converter and the analog input signal to perform analog-to-digital conversion; A delay delayer and a delay derivative derivative delayer for delaying the output signal of the analog-to-digital converter; A first digital analog converter that adds the signals output from the delay unit and the derivative delay unit into an analog signal and inputs the converted signal to the first integrator; A second digital analog converter which converts the signal output from the differential delay unit into an analog signal and inputs the converted signal into the second integrator Delta sigma modulator comprising a.

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