JP2009124507A - Delta-sigma type a/d converter, communication apparatus, and analog/digital conversion method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delta-sigma type A/D converter capable of increasing the number of low-noise bandpass bands while suppressing power consumption low. <P>SOLUTION: The delta-sigma type A/D converter includes a signal generating means which samples input signals in different timing to generate a first signal and a second signal which are orthogonal with each other, and at least one bandpass filter means which inputs the first signal and the second signal to perform filtering thereon. The bandpass filter means includes: a first integration means for integrating the first signal; a second integration means for integrating the second signal; a first feedback means for feeding an output of the first integration means back to an input of the second integration means using a variable feedback coefficient; and a second feedback means for feeding an output of the second integration means back to an input of the first integration means using a variable feedback coefficient. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an AD converter, and more particularly, to a delta-sigma type AD converter using a complex bandpass filter, a communication apparatus, and an analog-digital conversion method.

  The delta-sigma type AD converter is an AD converter that converts an analog signal into a digital signal by delta-sigma modulation. The delta-sigma type AD converter has advantages in that a higher resolution can be obtained and a chip area can be reduced as compared with other types of AD converters such as a sequential conversion method and a flash conversion method. . Therefore, the delta-sigma type AD converter is used as an AD converter for a wireless communication apparatus that performs wireless communication.

  An example of a conventional delta-sigma type AD converter is shown in FIG. 7 (see Non-Patent Document 1). The delta-sigma type AD converter 10 includes multipliers 11a and 11b that generate orthogonal I-channel and Q-channel signals, delay elements 15a, 15b, 19a, and 19b that delay and output an input signal, Amplitude ratio between adders 14a, 14b, 18a, 18b that feed back and add the outputs of the elements 15a, 15b, 19a, 19b, and an input signal and an integrator (consisting of an adder and a delay element) Amplifiers 13a, 13b, 17a, and 17b, a determination circuit 20 that quantizes the outputs of the delay elements 19a and 19b, and a multiplication circuit 21 that multiplies the output of the determination circuit 20 by a signal of 1/4 of the sample frequency. The subtracters 12a, 12b, which feed back the output of the determination circuit 20 and subtract from the input signal in the previous stage of the adders 14a, 14b, 18a, 18b, 6a, configured to include a 16b, and. In the upper stage, the multiplier 11a sequentially multiplies the input signal by a bit stream of {1, 0, −1, 0} and outputs it, so that an I channel signal is generated. In the lower stage, the multiplier 11b sequentially multiplies the input signal by the bit stream of {0, 1, 0, −1} and outputs the Q channel signal.

  FIG. 8 is an explanatory diagram showing a case where the configuration of the conventional delta-sigma type AD converter shown in FIG. 7 is configured by an actual circuit, and FIG. 9 is a clock input to the circuit shown in FIG. It is explanatory drawing shown about the change of the phase of a signal. In the clock signal shown in FIG. 9, signal 1 indicates the timing for sampling the I-channel and Q-channel signals, and signal 2 indicates the timing for performing integration processing on the I-channel and Q-channel signals. The signal X is a signal for controlling the inversion operation of the reference signal Vref for performing multiplication in the multipliers 11a and 11b, and the signal Z is a cosine (Cos) for generating I channel and Q channel signals. The processing division of a signal and a sine (Sin) signal is shown. Further, the switches shown in FIG. 8 are switched when the clock signals 1, 2, X and Z shown in FIG. 9 and the output Y of the determination circuit 20 are inputted. The numbers and alphabets in the vicinity of the switch correspond to the clock signals 1, 2, X and Z and the output Y of the determination circuit 20, respectively.

The clock signal shown in FIG. 9 is input to each switch of the circuit of FIG. 8 to perform arithmetic processing on the signal. At the timing when the clock signal 1 is HIGH, the sampled signal is stored as an electric charge in the capacitor C _1, and the corresponding integral value (the signal stored as an electric charge in the capacitor C _i or the capacitor C _q ) is simultaneously stored in the capacitor C _1. Moved to ₂ . Which capacitor's charge moves to the capacitor C ₂ depends on the state of the clock signal Z at the timing when the clock signal 1 is HIGH. If the clock signal Z becomes a HIGH (in a period of 9 (1) or (5)), the charge of the capacitor _{C i} is moved to the capacitor _{C 2,} if the clock signal Z becomes a LOW ( During the period of 3 or (7) in FIG. 9), the electric charge of the capacitor _{C q} moves to the capacitor _{C 2.}

Then, at the timing when the clock signal 2 is HIGH, the charges stored in the capacitors C ₁ and C ₂ move to the capacitor C _i or the capacitor C _q , and the integration operation is completed. Whether the charge is transferred to the capacitor C _i or the capacitor C _q depends on the state of the clock signal Z at the timing when the clock signal 2 becomes HIGH. If the clock signal Z becomes a HIGH (in the period (2) or (6) in FIG. 9), the charge moves to the capacitor _{C i,} the clock signal Z is if a LOW (in FIG. 9 ( In the period 4) or (8)), the charge moves to the capacitor _Cq .

  FIG. 10 is an explanatory diagram showing a waveform of an output signal from the delta sigma type AD converter 10 shown in FIG. 9 in a graph. The horizontal axis of the graph shown in FIG. 10 shows DC (Direct Current) at the left end, half the sampling frequency at the right end, and the input waveform is simulated near ¼ of the sampling frequency. As shown in FIG. 10, the configuration is such that the minimum value of the quantization noise comes near the frequency of the output signal.

  When actually used as an AD converter, a signal can be taken out in the vicinity of DC by outputting the output Y of the circuit shown in FIG. 8 as it is. In other words, the signal can be extracted near DC by omitting the XNOR circuit on the output side.

  Thus, the circuit shown in FIG. 8 can digitize a signal in the vicinity of a quarter of the sampling frequency with low noise. Further, the mixer of the input stage can be turned off by changing the clock signal of FIG. 9 as shown in FIG. In this case, it operates as a delta sigma type AD converter capable of digitizing an input signal near DC with low noise. FIG. 12 is an explanatory diagram showing the output waveform in a graph when the clock signal shown in FIG. 11 is input to the delta sigma type AD converter 10 shown in FIG.

  From the above, with the circuit configuration shown in FIG. 8, it is possible to create a delta-sigma type AD converter that can digitize an analog signal with low noise in two bands of DC and 1/4 of the sampling frequency.

  By further increasing the number of bands in which analog signals can be digitized with low noise, AD signals can be converted from analog signals to digital signals while keeping the clock signal constant. And is expected to be useful for delta-sigma modulation.

Bang-Sup Song, “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.30, NO.12, pp1309-1315, DECEMBER 1995.

  Therefore, using the delta-sigma type AD converter to further increase the number of low-noise bandpass bands can be easily realized by increasing the number of delays in the loop of the integrator.

  However, increasing the number of delays in the loop of the integrator means increasing the number of amplifiers, resulting in a problem that leads to an increase in power consumption. In addition, the circuit configuration becomes a redundant circuit configuration for dealing with the band that requires the most delay among all the bandpass bands, and an operation with a high-speed clock that is not essential is required. As a result, it is not suitable for obtaining low power consumption and a small circuit scale.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a novel device capable of further increasing the number of low-noise bandpass bands while keeping power consumption low. Another object of the present invention is to provide an improved delta-sigma type AD converter, communication apparatus, and analog-digital conversion method.

  In order to solve the above-described problem, according to an aspect of the present invention, a delta-sigma type AD converter is provided that samples an input signal at different timings, and first and second signals orthogonal to each other. And a signal calculation means for calculating a signal generated by the signal generation means, wherein the signal calculation means integrates a first signal generated by the signal generation means. Means, a second integrating means for integrating the second signal generated by the signal generating means, and a second coefficient that multiplies the output of the first integrating means by a predetermined coefficient and feeds back to the input of the second integrating means. And a second feedback means for multiplying the output of the second integrating means by a predetermined coefficient and feeding back to the input of the first integrating means. AD conversion There is provided.

  According to this configuration, the signal generation unit samples the input signal at different timings to generate the first signal and the second signal that are orthogonal to each other, and the first integration unit is generated by the signal generation unit. 1 is integrated, the second integrating means integrates the second signal generated by the signal generating means, and the first feedback means multiplies the output of the first integrating means by a predetermined coefficient to Feedback is made to the input of the second integrating means, and the second feedback means multiplies the output of the second integrating means by a predetermined coefficient and feeds back to the input of the first integrating means. As a result, integration processing is performed on the first signal and the second signal orthogonal to each other, and the integration result is fed back to the partner signal, thereby reducing power consumption without making a redundant configuration, It becomes possible to further increase the number of low-noise bandpass bands.

  The signal generation means includes a first capacitor for storing charges corresponding to the sampled first signal or the second signal, respectively, and the signal calculation means includes the first signal stored in the first capacitor. A second capacitor that integrates and accumulates charges corresponding to, a third capacitor having a capacitance that is a predetermined coefficient multiple of the capacitance of the second capacitor, and a second signal stored in the first capacitor. A fourth capacitor for integrating and storing corresponding charges, a fifth capacitor having a capacitance that is a predetermined coefficient multiple of the capacitance of the fourth capacitor, a second capacitor, a third capacitor, and a fourth capacitor And a sixth capacitor and a seventh capacitor for temporarily accumulating charges and voltages accumulated in the fifth capacitor, the first capacitor, the sixth capacitor, and the The charge stored in the capacitor is distributed to the second capacitor and the third capacitor, or the fourth capacitor and the fifth capacitor at a predetermined ratio corresponding to a predetermined coefficient, and stored in the sixth capacitor. The charge and the charge accumulated in the seventh capacitor are fed back to the second capacitor and the third capacitor, or the fourth capacitor and the fifth capacitor, and accumulated in the third capacitor and the fifth capacitor. Each of the generated charges may be fed back to the other signal input.

  The capacitances of the third capacitor and the fifth capacitor may be variable. As a result, the band pass band can be changed by changing the capacitance of the capacitor.

  The processing timing of the first signal and the second signal may be reversible. As a result, as a result, the band pass band can be changed by changing the processing timing of the first signal and the second signal.

  The sampling period in the signal generating means may be variable. As a result, by changing the sampling period, bandpass bands can be added or changed for signals of various frequencies.

  In order to solve the above problems, according to another aspect of the present invention, there is provided a communication apparatus comprising the delta sigma type AD converter.

  In order to solve the above problem, according to another aspect of the present invention, a signal generation step of sampling an input signal at different timings to generate a first signal and a second signal orthogonal to each other; A first integration step for integrating and outputting the first signal generated in the signal generation step; a second integration step for integrating and outputting the second signal generated in the signal generation step; A first feedback step that multiplies the output of the integration step by a predetermined coefficient and feeds it back to the input of the second integration step; and a first integration step that multiplies the output of the second integration step by a predetermined coefficient. There is provided a second feedback step of feeding back to the input of the analog-to-digital conversion method.

  According to this configuration, the signal generation step samples the input signal at different timings to generate the first signal and the second signal orthogonal to each other, and the first integration step is generated by the signal generation step. 1 signal is integrated and output, the second integration step integrates and outputs the second signal generated in the signal generation step, and the first feedback step outputs a predetermined signal to the output of the first integration step. The coefficient is multiplied and fed back to the input of the second integration means, and the second feedback step multiplies the output of the second integration step by a predetermined coefficient and feeds back to the input of the first integration step. As a result, integration processing is performed on the first signal and the second signal orthogonal to each other, and the integration result is fed back to the partner signal, thereby reducing power consumption without making a redundant configuration, It becomes possible to further increase the number of low-noise bandpass bands.

  As described above, according to the present invention, a new and improved delta-sigma type AD converter, communication device, which can further increase the number of low-noise bandpass bands while suppressing power consumption, And an analog-digital conversion method can be provided.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  First, in order to further increase the number of low-noise band-pass bands, a method of performing feedback using respective integrated values of I-channel signals and Q-channel signals will be examined. FIG. 13 is an explanatory diagram showing a delta-sigma type AD converter that attempts to increase the number of low-noise bandpass bands by performing feedback using respective integrated values of the I-channel signal and the Q-channel signal. is there.

  In FIG. 13, the output of the decision circuit 20a that quantizes the output signal of the I channel and the output of the decision circuit 20b that quantizes the output signal of the Q channel are fed back and subtracted from the input signal, respectively. The configuration is the same as that shown in FIG. 7 is different from FIG. 7 in that the integrator shown in FIG. 7 is a complex resonator 21 in FIG. By using the complex resonator 21, a bandpass band different from that in FIG. 7 can be generated.

  FIG. 14 is an explanatory diagram for explaining the configuration of the complex resonator 21 in the delta sigma type AD converter shown in FIG. As shown in FIG. 14, the complex resonator 21 includes integrators 22a and 22b and capacitors 25a, 25b, 26a, and 26b. The integrator 22a includes an amplifier 23a and a capacitor 24a. Similarly, the integrator 22b includes an amplifier 23b and a capacitor 24b.

  In the complex resonator 21 shown in FIG. 14, the outputs of the integrators 22a and 22b are stored in the feedback capacitors 25a and 25b for the own channel and the feedback capacitors 26a and 26b for the other channels, respectively. Then, it is integrated with the input of the complex resonator 21 at the next timing.

となる。すなわち、ｃ、ｄの値を変化させることで伝達関数を変化させることができ、従ってバンドパス帯域を変化させることができる。 FIG. 15 is an explanatory diagram showing the configuration of the complex resonator 21 shown in FIG. 14 in a block diagram. As shown in FIG. 15, the transfer function H of the whole resonator has a capacity of c for feedback capacitors 26 a and 26 b for other channels and a capacity of feedback capacitors 25 a and 25 b for own channels.

It becomes. That is, the transfer function can be changed by changing the values of c and d, and therefore the bandpass band can be changed.

  Therefore, it is considered that the bandpass band can be changed by applying the complex resonator 21 shown in FIG. 14 to the delta-sigma type AD converter shown in FIG. The complex resonator 21 shown in FIG. 14 cannot be applied to the delta-sigma type AD converter shown in FIG. This is because the complex resonator 21 shown in FIG. 14 uses the I-channel signal and the Q-channel signal sampled simultaneously, whereas the delta-sigma type AD converter shown in FIG. This is because I channel signals and Q channel signals sampled at different timings are used.

  Therefore, in one embodiment of the present invention, a delta-sigma type AD converter that changes the bandpass band by performing feedback using the I-channel signal and the Q-channel signal that are sampled mutually at different timings. Will be described.

  First, before describing a delta-sigma type AD converter according to an embodiment of the present invention, how to perform feedback uses I-channel signals and Q-channel signals sampled at different timings. The bandpass bandwidth can be changed.

なお、複素平面上においては、横軸（Ｘ）がＩチャネルに、縦軸（Ｙ）がＱチャネルに、それぞれ該当する。 When the input signal is a sine wave having a constant amplitude, the position of the nth sampled signal on the complex plane is (Xn, Yn), and the position of the n−1th sampled signal on the complex plane is (Xn). −1, Yn−1), where the position on the complex plane of the (n−2) th sampled signal is (Xn−2, Yn−2), Equation 2 below is established.

On the complex plane, the horizontal axis (X) corresponds to the I channel, and the vertical axis (Y) corresponds to the Q channel.

  If the input signal is subjected to mixer processing like a delta sigma type AD converter as shown in FIG. 7, the I channel signal and the Q channel signal are sampled alternately. Therefore, at the time of sampling, only one of the I channel signal and the Q channel signal is sampled, and when the X component is known at the nth sample timing, the Y component is unknown. In other words, when the X component is known at the nth sample timing, the (n-1) th Y component and the (n-2) th X component are known, and the Y component is known at the nth sample timing. In this case, the (n-1) th X component and the (n-2) th Y component are known.

In addition, θ shown in Equation 2 above indicates the amount of phase advance per sample. Here, since mixing is performed at a quarter of the sample frequency, the amount of phase advance per sample can be obtained from the difference between the quarter of the sampling frequency and the frequency of the input sine wave. it can. Assuming that the sampling frequency is fs and the frequency of the input sine wave is fc, θ is obtained by the following Equation 3.

Here, when the determinant expressed by Equation 2 is solved, Xn and Yn are as shown in Equation 4 below.

As described above, when the X component is known at the nth sample timing, the (n-1) th Y component and the (n-2) th X component are known, and the Y component is found at the nth sample timing. If it is known, since the (n-1) th X component and the (n-2) th Y component are known, feedback using a complex resonator is possible only with the information obtained with the configuration shown in FIG. Become. By feeding back the above Xn and Yn, it is possible to perform feedback so that the band pass band becomes fc. The transfer function H of the complex resonator at that time is as shown in Equation 5 below.

For example, when the band of 3/8 of the sampling frequency fs is desired to be a band pass band, if 3fs / 8 is substituted for fc in Equation 3, θ becomes as shown in Equation 6 below.

となるようなフィードバックを行えばよいことが分かる。 Therefore, when it is desired to set the band of 3/8 of the sampling frequency fs as a band pass band, θ = π / 4 is substituted into Equation 4,

It can be seen that it is sufficient to provide feedback such that

  Based on the above discussion, a delta-sigma type AD converter according to an embodiment of the present invention will be described. FIG. 1 is an explanatory diagram for explaining the configuration of a delta-sigma AD converter 100 according to an embodiment of the present invention. Hereinafter, the configuration of a delta-sigma type AD converter 100 according to an embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, a delta-sigma AD converter 100 according to an embodiment of the present invention includes multipliers 111a, 111b, 111c, and 111d that generate I-channel and Q-channel signals that are orthogonal to each other, and an input. Delay elements 115a, 115b, 119a, and 119b that delay and output signals; adders 114a, 114b, 118a, and 118b that feed back and add the outputs of the delay elements; an input signal; one delay element; Amplifiers 113a, 113b, 117a, and 117b that determine the amplitude ratio between the integrator and the integrator configured with the adder, the determination circuit 120 that quantizes the output of the integrator, and the output of the determination circuit 120 are fed back. Subtractors 112a, 112b for subtracting from the input signal before the adders 114a, 114b, 118a, 118b, The multipliers 122a, 122b, 123a, and 124b that multiply the outputs of the delay elements 115a, 116b, the delay elements 115a, 115b, 119a, and 119b and feed back to the integrator inputs of the other channels, respectively, and the output of the determination circuit 120 And a delay element 125 that performs a difference from the input signal with a delay of n timings.

  In the delta sigma type AD converter 100 shown in FIG. 1, in the upper stage, the multiplier 111a multiplies the input signal by the bit stream of {1, 0, −1, 0} in order, and outputs it. A channel signal is generated. On the other hand, in the lower stage, the multiplier 111b sequentially multiplies the input signal by the bit stream of {0, 1, 0, −1} and outputs the Q channel signal.

  As described above, the amplifiers 113a, 113b, 117a, and 117b determine the amplitude ratio between the input signal and the integrator. In this embodiment, the input is multiplied by 0.5 in the first stage and output. In the next stage, an amplifier that doubles the input and outputs is used. In the present invention, the amplification factor of the amplifier is not limited to this example.

  An integrator composed of a combination of an adder and a delay element integrates and outputs an I-channel or Q-channel input signal. In the delta sigma AD converter 100 shown in FIG. 1, the adder 114a and the delay element 115a constitute one integrator. Similarly, the adder 114b and the delay element 115b, the adder 118a and the delay element 119a, and the adder 118b and the delay element 119b constitute one integrator, respectively. The output of the subsequent-stage integrator is input to the determination circuit 120, and the input of the subsequent-stage integrator that is input in analog is digitized and output. The output data quantized by the determination circuit 120 is obtained by alternately outputting a DC signal divided into an I channel and a Q channel.

  The conventional delta sigma type AD converter 10 shown in FIG. 7 and the delta sigma type AD converter 100 shown in FIG. 1 respectively output the outputs of the delay elements 115a, 115b, 119a, and 119b to other channels. The difference is that multipliers 122a, 122b, 123a, and 124b that multiply the input of the integrator by a predetermined magnification and feedback and a delay element 125 that delays the output of the determination circuit 120 by a predetermined n timing are added.

  The multipliers 122a and 123a perform feedback from the Q channel signal to the I channel signal by multiplying the input signal by a predetermined magnification. When feedback is performed, feedback is performed by multiplying by −2 sin θ so as to correspond to the above Equation 4. Actually, the multipliers 122a and 123a multiply by 2 sin θ, and the adders 114a and 118a subtract the outputs of the multipliers 122a and 123a from the outputs of the amplifiers 113a and 117a, so that −2 sin θ corresponds to Equation 4. To achieve feedback. On the other hand, the multipliers 122b and 123b perform feedback from the I channel signal to the Q channel signal. When feedback is performed, the feedback is performed by multiplying by 2 sin θ so as to correspond to the above Equation 4.

  Thus, by feeding back the signal of the other channel multiplied by 2 sin θ or −2 sin θ and the signal of the own channel delayed by one sample and performing addition or subtraction by the adder, the equation shown in the above equation 4 Can be realized.

  The delay element 125 delays the output of the determination circuit 120 by a predetermined n timings, and the output of the delay element 125 is input to the subtractors 112a, 112b, 116a, and 116b, and a difference from the input signal is performed. Here, n is a value represented by n = (θ / π). As described above, when 3/8 of the sampling frequency fs is desired to be a band pass band, n = 4 is obtained by substituting θ = π / 4. It can be seen that a delay is required at 125.

  The configuration of the delta sigma type AD converter 100 according to the embodiment of the present invention has been described above with reference to FIG. Next, a circuit configuration of the delta sigma type AD converter 100 according to the embodiment of the present invention will be described.

FIG. 2 is an explanatory diagram illustrating a circuit configuration of the delta-sigma AD converter 100 according to the embodiment of the present invention. Compared with the conventional delta sigma type AD converter 10 shown in FIG. 7, the delta sigma type AD converter 100 according to one embodiment of the present invention shown in FIG. The difference is that a capacitor (2 sin θ · C _i ) for feeding back to the signal and a capacitor (2 sin θ · C _q ) for feeding back the Q channel signal to the I channel signal are added.

The capacitance ratio of the capacitor 2 sin θ · C _i and the capacitor C _i is configured to be 2 sin θ: 1. Similarly, the capacitance ratio between the capacitor 2 sin θ · C _q and the capacitor C _q is also set to 2 sin θ: 1. By setting the capacitance ratio in this way, the charge stored in the capacitor C ₁ is distributed to the capacitors 2 sin θ · C _i and the capacitor C _i , and to the capacitors 2 sin θ · C _q and the capacitor C _q so that 2 sin θ: 1. It is done. Then, the capacitor 2sinθ · _{C i,} and the charge stored in the capacitor 2sinθ · _{C q} are each fed back to the capacitor corresponding to the other channels, the capacitor _C i, the charge stored in _{C q,} the own channel, respectively Is fed back to the capacitor corresponding to the above, the mathematical expression shown in the mathematical expression 4 is satisfied. As shown in the above equation 4 and FIG. 1, when feedback is performed from the Q channel to the I channel, it is necessary to multiply by −2 sin θ. Therefore, in FIG. 2, the charge on the I channel side is represented by the Q channel. The circuit is configured to feed back to the side.

  The clock signal input to the circuit shown in FIG. 2 is the same as the clock signal input to the conventional delta sigma type AD converter 10 shown in FIG. When the clock signal shown in FIG. 9 is input, the delta sigma type AD converter 100 according to the embodiment of the present invention operates. The switches shown in FIG. 2 are switched by inputting the clock signals 1, 2, X and Z shown in FIG. 9 and the output Y of the delay element 125, respectively. The numbers and alphabets in the vicinity of the switch correspond to the clock signals 1, 2, X and Z and the output Y of the delay element 125, respectively.

Thus, the feedback ratio of the integral value of the I channel and the Q channel could be achieved. However, the ratio of the charge amount to the sampled signal remains 1: 1. Therefore, in the delta-sigma type AD converter 100 according to the embodiment of the present invention shown in FIG. 2, a capacitor ( ₂ sin θ · C ₂ ) for feeding back the output of the integrator is further added. The capacitor ₂ sin θ · C ₂ is configured such that the capacitance ratio with the capacitor C ₂ is ₂ sin θ: 1.

The capacitor ₂ sin θ · C ₂ causes the movement of the charge from the capacitor ₂ sin θ · C ₂ simultaneously with the movement of the electric charge stored in the capacitor C ₂ to the capacitors C _i and C _q , so that a desired feedback is obtained. be able to.

  The operation of the circuit shown in FIG. 2 will be described in more detail by comparing the operation of the conventional sigma-delta AD converter 10 shown in FIG.

Similar to the conventional sigma-delta AD converter 10 shown in FIG. 8, the sigma-delta AD converter 100 shown in FIG. 2 has a timing when the clock signal 1 becomes HIGH ((1) in FIG. (3), (5), or a period of (7)), the sampled signals are stored as electric charges in the capacitor C _1, is stored as a corresponding integral value (charge in the capacitor C _i or capacitor C _q simultaneously signal) is moved to the capacitor C _2. Which electric charge of the capacitor moves to the capacitor C ₂ is dependent on the state of the clock signal Z at the time when the clock signal 1 becomes HIGH. If the clock signal Z becomes a HIGH (in a period of 9 (1) or (5)), the charge of the capacitor _{C i} is moved to the capacitor _{C 2,} if the clock signal Z becomes a LOW ( in the period (3) or (7) in FIG. 9), the electric charge of the capacitor _{C q} moves to the capacitor _{C 2.} Further, at the timing when the clock signal 1 becomes HIGH, electric charge is accumulated in the capacitor ₂ sin θ · C ₂ .

Then, at the timing when the clock signal 2 is HIGH, the charges stored in the capacitors C ₁ , C ₂ and ₂ sin θ · C ₂ are transferred to the capacitors C _i , 2 sin θ · C _i or the capacitors C _q , 2sin θ · C _q . Moving. Which set of capacitors the charge is transferred to depends on the state of the clock signal Z at the timing when the clock signal 2 is HIGH. If the clock signal Z is HIGH (in the period (2) or (4) in FIG. 9), the charge moves to the capacitor C _i and the capacitor 2 sin θ · C _i , and the clock signal Z can be LOW. For example, during the period (4) or (8) in FIG. 9, the charge moves to the capacitor C _q and the capacitor 2 sin θ · C _q .

Further, at the timing when both the clock signal 1 and the clock signal Z are HIGH (in the period (1) or (5) in FIG. 9), the charge stored in the capacitor 2 sin θ · C _q on the i-channel side is Move to the circuit on the q channel side. That is, the charges corresponding to the I-channel and Q-channel signals sampled one cycle before the clock signal 1 move to the circuits corresponding to the other channels, respectively, so that the right side in the two equations of Equation 4 described above The first term can be realized.

  In this way, a switched capacitor filter having a bandpass characteristic is formed by repeating the movement and release of charges in each capacitor. And the band pass band can be arbitrarily changed by changing the value of θ.

  For example, when 3/8 of the sampling frequency fs is desired to be a band pass band. θ is θ = π / 4, and the value of 2sinθ is 2sin (π / 4) = √2. Therefore, by configuring the circuit so that the capacitance ratio of the capacitor becomes √2: 1, it is possible to realize a delta sigma type AD converter in which a band of 3/8 of the sampling frequency fs is a band pass band. it can.

  For example, when it is desired to set a band of 1/8 of the sampling frequency fs as a band pass band. θ is θ = −π / 4, but the value of 2sinθ is also 2sin (−π / 4) = √2. Therefore, by configuring the circuit so that the capacitance ratio of the capacitor becomes √2: 1, it is possible to realize a delta-sigma type AD converter in which a band of 1/8 of the sampling frequency fs is a bandpass band. it can.

  The circuit configuration of the delta sigma type AD converter 100 according to the embodiment of the present invention has been described above with reference to FIG.

  FIG. 3 is an explanatory diagram showing, in a graph, an output when a frequency of 3/8 of the sampling frequency fs is given as an input signal in the delta sigma type AD converter 100 according to the embodiment of the present invention. As shown in FIG. 3, it can be seen that the quantization noise is reduced in the signal band to achieve the purpose.

  Next, it is shown that another band pass band can be achieved with the same circuit configuration. FIG. 4 is an explanatory diagram showing another example of the clock signal input to the delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIG. In the clock signal shown in FIG. 4, the phase of the clock signal Z is reversed as compared with FIG. Therefore, the band pass band is the opposite side of the band pass band achieved by inputting the clock signal of FIG. 9 to the delta sigma type AD converter 100. Here, the opposite side refers to the opposite side with the same absolute value when viewed from the carrier frequency.

  FIG. 5 is an explanatory diagram showing, in a graph, an output when a frequency that is 1/8 of the sampling frequency fs is given as an input signal in the delta sigma type AD converter 100 according to the embodiment of the present invention. As shown in FIG. 5, it can be seen that the quantization noise is reduced in the signal band and the purpose is achieved.

  FIG. 6 shows a state in which a signal having a frequency of 1/8 of the sampling frequency fs is multiplied by an output when the frequency of 3/8 of the sampling frequency fs shown in FIG. It is explanatory drawing explaining the spectrum of this. A desired signal can be obtained by passing such a signal through a low-pass filter. The same applies to the output when a frequency of 1/8 of the sampling frequency fs shown in FIG. 5 is given as an input signal.

Further, in the delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIG. 2, the capacitor ₂ sin θ · C ₂ , the capacitor ₂ sin θ · C _i , and the capacitor 2 sin θ · C _q are not used. The circuit configuration is the same as that of the conventional delta-sigma type AD converter 10 shown in FIG. Therefore, it can be seen that the delta sigma type AD converter 100 according to one embodiment of the present invention shown in FIG. 2 operates as a bandpass delta sigma converter corresponding to a frequency of 1/4 of the sampling frequency fs and DC. . Therefore, the delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIGS. 1 and 2 includes four bandpass bands of frequencies corresponding to 1/4 of the sampling frequency fs, DC, and ± θ. It can correspond to. The delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIGS. 1 and 2 changes the sampling frequency by changing the clock frequency of the input clock signal, so that the bandpass band It is also clear that can be changed.

  The delta sigma type AD converter 100 according to the embodiment of the present invention has been described above.

  In FIG. 1 and FIG. 2, two pairs of amplifiers and complex resonators are provided. This facilitates comparison with the conventional delta-sigma type AD converter 10 shown in FIG. For this reason, two are provided, and the present invention is not limited to this example. There may be one complex resonator or three or more complex resonators. Further, the clock signals input to the delta sigma type AD converter 100 shown in FIG. 2 are exactly opposite in phase to the clock signal 1 and the clock signal 2, but there are two clock signals 1 and 2. In order not to be HIGH, the LOW period of the clock signal 2 may be longer than the HIGH period of the clock signal 1.

(Modification)
Hereinafter, various modifications of the delta-sigma type AD converter according to the embodiment of the present invention will be described.

In the circuit configuration of the delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIG. 2, by adding a capacitor or changing the capacitor to a variable capacitor, Changes can be made. Specifically, in the circuit configuration of the delta sigma type AD converter 100 shown in FIG. 2, the capacitor ₂ sin θ · C ₂ , the capacitor ₂ sin θ · C _i , and the capacitor 2 sin θ · C _q may be variable capacitors, or may correspond to different θ. By switching and using capacitors having the capacity to be parallel, a delta-sigma type AD converter having passbands at different θ, that is, different frequencies can be configured.

  1 and 2 include multipliers 111a and 111b that multiply a signal having a frequency that is ¼ of the sampling frequency fs by an input signal. The multipliers 111a and 111b may be separated from the delta sigma type AD converter.

  Note that the delta sigma type AD converter 100 according to the embodiment of the present invention shown in FIGS. 1 and 2 may be used in a communication apparatus that performs network communication. By using the delta sigma type AD converter 100 according to an embodiment of the present invention for a communication apparatus that performs network communication, it is possible to have a plurality of passband positions while suppressing power consumption, thereby reducing power consumption. Communication efficiency can be improved while suppressing.

  Alternatively, the I-channel signal and the Q-channel signal may be reversed and delta-sigma modulation may be performed by the delta-sigma type AD converter 100 to convert the analog signal into a digital signal. The band pass band can be changed by switching the I channel signal and the Q channel signal and inputting them.

  As described above, according to an embodiment of the present invention, by using a combination of switch control, capacitor capacitance control, and clock control, power consumption is kept low, and a plurality of passband positions are provided. It is possible to realize a delta-sigma type AD converter that can perform this. As a result, communication processing and signal processing can be realized by a single circuit using a plurality of frequency channels.

  In addition, in order to perform time division processing on the I channel signal and the Q channel signal using the same circuit. The circuit scale is small, and the occurrence of IQ imbalance can be suppressed. Therefore, as compared with the conventional complex bandpass delta sigma AD converter, it is possible to achieve small size, low power consumption, low cost, and low distortion, and it can be easily created.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in FIG. 1, feedback from the delay element 125 to the subtractors 112a, 112b, 116a, and 116b is performed. However, in the present invention, feedback to the subtractors 112a, 112b, 116a, and 116b is not limited to this example. The feedback may be performed by a method other than the delay element 125. In FIG. 2, the feedback is performed from the delay element delayed by 3 clocks, but the present invention is not limited to such an example, and the feedback may be performed by other methods.

  The present invention relates to an AD converter, and is particularly applicable to a delta-sigma type AD converter using a complex bandpass filter, a communication device, and an analog-digital conversion method.

It is explanatory drawing explaining the structure of the delta-sigma type AD converter 100 concerning one Embodiment of this invention. It is explanatory drawing explaining the circuit structure of the delta-sigma type AD converter 100 concerning one Embodiment of this invention. In delta sigma type AD converter 100 concerning one embodiment of the present invention, it is an explanatory view showing an output at the time of giving a frequency of 3/8 of sampling frequency fs as an input signal with a graph. It is explanatory drawing shown about another example of the clock signal input into the delta-sigma type AD converter 100 concerning one Embodiment of this invention. In the delta sigma type AD converter 100 concerning one embodiment of the present invention, it is an explanatory view showing an output at the time of giving a frequency of 1/8 of sampling frequency fs as an input signal with a graph. It is explanatory drawing explaining the spectrum of the state converted into DC signal. It is explanatory drawing explaining the conventional delta-sigma type AD converter. It is explanatory drawing explaining the circuit structure of the conventional delta sigma type AD converter. FIG. 9 is an explanatory diagram illustrating an example of a clock signal input to the delta sigma type AD converter illustrated in FIG. 8. It is explanatory drawing which shows the waveform of the output signal from the delta-sigma type AD converter 10 shown in FIG. 9 with a graph. FIG. 9 is an explanatory diagram illustrating another example of a clock signal input to the delta-sigma type AD converter illustrated in FIG. 8. FIG. 13 is an explanatory diagram illustrating, in a graph, an output waveform when the clock signal illustrated in FIG. 11 is input to the delta sigma type AD converter illustrated in FIG. 8. It is explanatory drawing which shows the delta-sigma type AD converter which tries to increase the number of the low noise band pass bands by performing feedback using the integration value of each of the I channel signal and the Q channel signal. It is explanatory drawing explaining the structure of the complex resonator 21 in the delta-sigma type AD converter shown in FIG. 3 is an explanatory diagram showing a configuration of a complex resonator 21 in a block diagram. FIG.

Explanation of symbols

100 Delta sigma type AD converter 111a, 111b, 111c, 111d, 122a, 122b, 123a, 124b Multiplier 112a, 112b, 116a, 116b Subtractor 113a, 113b, 117a, 117b Amplifier 114a, 114b, 118a, 118b Adder 115a, 115b, 119a, 119b delay element 120 determination circuit 125 delay element

Claims (8)

A delta-sigma type AD converter,
Signal generating means for sampling an input signal at different timings to generate a first signal and a second signal orthogonal to each other;
Signal calculating means for calculating a signal generated by the signal generating means;
The signal calculation means comprises:
First integrating means for integrating the first signal generated by the signal generating means;
Second integrating means for integrating the second signal generated by the signal generating means;
First feedback means for multiplying the output of the first integration means by a predetermined coefficient and feeding back to the input of the second integration means;
Second feedback means for multiplying the output of the second integration means by a predetermined coefficient and feeding back to the input of the first integration means;
A delta-sigma type AD converter, comprising: The signal generating means includes
A first capacitor for respectively storing charges corresponding to the sampled first signal or the second signal;
The signal calculation means includes
A second capacitor and a third capacitor for integrating and storing charges corresponding to the first signal stored in the first capacitor;
A fourth capacitor and a fifth capacitor for integrating and storing charges corresponding to the second signal stored in the first capacitor;
A sixth capacitor and a seventh capacitor that temporarily store charges and voltages stored in the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor;
With
The charges stored in the first capacitor, the sixth capacitor, and the seventh capacitor are the second capacitor and the third capacitor, or the fourth capacitor and the charge at a ratio corresponding to the predetermined coefficient. To the fifth capacitor,
Feeding back the charge accumulated in the sixth capacitor and the charge accumulated in the seventh capacitor to the second capacitor and the third capacitor, or the fourth capacitor and the fifth capacitor;
2. The delta-sigma type AD converter according to claim 1, wherein charges accumulated in the third capacitor and the fifth capacitor are fed back to the other signal input, respectively.   The delta-sigma type AD converter according to claim 2, wherein capacitances of the third capacitor and the fifth capacitor are variable.   2. The delta-sigma type AD converter according to claim 1, wherein processing timings of the first signal and the second signal can be reversed.   2. The delta-sigma type AD converter according to claim 1, wherein a sampling period in the signal generation means is variable.   2. The delta-sigma type AD converter according to claim 1, wherein the predetermined coefficient is 2 sin [theta] ([theta] is a phase advance amount per sample in the signal generating means).   A communication apparatus comprising the delta-sigma type AD converter according to claim 1. A signal generation step of sampling the input signal at different timings to generate a first signal and a second signal orthogonal to each other;
A first integration step of integrating and outputting the first signal generated in the signal generation step;
A second integration step of integrating and outputting the second signal generated in the signal generation step;
A first feedback step of multiplying the output of the first integration step by a predetermined coefficient and feeding back to the input of the second integration step;
A second feedback step of multiplying the output of the second integration step by a predetermined coefficient and feeding back to the input of the first integration step;
An analog-to-digital conversion method comprising:

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