JP2011066223A5 - - Google Patents
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- JP2011066223A5 JP2011066223A5 JP2009215861A JP2009215861A JP2011066223A5 JP 2011066223 A5 JP2011066223 A5 JP 2011066223A5 JP 2009215861 A JP2009215861 A JP 2009215861A JP 2009215861 A JP2009215861 A JP 2009215861A JP 2011066223 A5 JP2011066223 A5 JP 2011066223A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- conductor layer
- conductor
- layers
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Description
ここで、前記回路基板は、導電体層と絶縁体層とを交互に積層して構成された回路基板ユニットを複数積層して構成され、隣接する２つの回路基板ユニットの最表面の導電体層に形成されたコアビアランド同士がコアビアを介して接続され、
前記一方の導電体層に形成された外部接続パッドと前記他方の導電体層に形成されたビアランドとは、前記２つの回路基板ユニットのコアビアランドを含むビアランド、および、前記コアビアを含むビアを介して接続され、
前記回路基板ユニットのそれぞれにおいて、前記導電体層のうちの前記最表面の反対の面の導電体層に、固定電位が供給される基準プレーンが、前記コアビアランドに対向するように形成されていることが好ましい。
また、前記回路基板ユニットのそれぞれにおいて、前記コアビアランドを除くビアランドの全てが、前記コアビアランドの中心位置から水平面内でずらして配置されていることが好ましい。
また、前記基準プレーンが形成される導電体層、および、該基準プレーンが形成される導電体層と前記一方の導電体層との間の導電体層のビアランドが、その中心が、前記外部接続パッドの中心に対して同一の水平方向に、前記一方の導電体層から垂直方向に離れるほど大きくずれるように配置されていることが好ましい。
Here, the circuit board is formed by laminating a plurality of circuit board units constituted by alternately laminating conductor layers and insulator layers, and the outermost conductor layer of two adjacent circuit board units. The core via lands formed on each other are connected through the core vias,
The external connection pads formed on the one conductor layer and the via lands formed on the other conductor layer include via lands including the core via lands of the two circuit board units and vias including the core vias. Connected,
In each of the circuit board units, a reference plane to which a fixed potential is supplied is formed on the conductor layer opposite to the outermost surface of the conductor layers so as to face the core via land. Is preferred.
Further, in each of the circuit board units, it is preferable that all of the via lands except the core via lands are arranged so as to be shifted in a horizontal plane from the center position of the core via lands.
Further, the conductor layer in which the reference plane is formed, and the via land of the conductor layer between the conductor layer in which the reference plane is formed and the one conductor layer, the center of which is the external connection It is preferable that they are arranged in the same horizontal direction with respect to the center of the pad so as to be largely displaced as they are separated from the one conductor layer in the vertical direction.
Claims (6)
前記他方の導電体層、および、前記中間導電体層のうちの前記一方の導電体層の直上の導電体層を除く導電体層の少なくとも１つに、固定電位が供給される基準プレーンが、前記外部接続パッドの上空域内で前記外部接続パッドに対向するように形成されていることを特徴とする回路基板。 An external connection pad formed on one conductor layer and a via land formed on the other conductor layer above the one conductor layer, which is configured by alternately laminating conductor layers and insulator layers. Are via lands formed in one or more intermediate conductor layers therebetween, and via connection structures that transmit signals by being connected via vias between adjacent conductor layers. ,
A reference plane to which a fixed potential is supplied to at least one of the other conductor layers and a conductor layer excluding the conductor layer immediately above the one of the intermediate conductor layers, A circuit board, wherein the circuit board is formed to face the external connection pad in an air space above the external connection pad.
前記一方の導電体層に形成された外部接続パッドと前記他方の導電体層に形成されたビアランドとは、前記２つの回路基板ユニットのコアビアランドを含むビアランド、および、前記コアビアを含むビアを介して接続され、The external connection pads formed on the one conductor layer and the via lands formed on the other conductor layer include via lands including the core via lands of the two circuit board units and vias including the core vias. Connected,
前記回路基板ユニットのそれぞれにおいて、前記導電体層のうちの前記最表面の反対の面の導電体層に、固定電位が供給される基準プレーンが、前記コアビアランドに対向するように形成されていることを特徴とする請求項１記載の回路基板。In each of the circuit board units, a reference plane to which a fixed potential is supplied is formed on the conductor layer opposite to the outermost surface of the conductor layers so as to face the core via land. The circuit board according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009215861A JP2011066223A (en) | 2009-09-17 | 2009-09-17 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009215861A JP2011066223A (en) | 2009-09-17 | 2009-09-17 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2011066223A JP2011066223A (en) | 2011-03-31 |
| JP2011066223A5 true JP2011066223A5 (en) | 2012-11-01 |
Family
ID=43952161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009215861A Pending JP2011066223A (en) | 2009-09-17 | 2009-09-17 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2011066223A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8541693B2 (en) | 2010-03-31 | 2013-09-24 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
| JP6218481B2 (en) | 2012-09-27 | 2017-10-25 | 三菱電機株式会社 | Flexible substrate, substrate connection structure, and optical module |
| WO2016075730A1 (en) * | 2014-11-10 | 2016-05-19 | 株式会社日立製作所 | Substrate structure for high-speed signal transmission |
| WO2023100853A1 (en) * | 2021-11-30 | 2023-06-08 | 京セラ株式会社 | Wiring substrate, electronic device, and electronic module |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002100901A (en) * | 2000-09-25 | 2002-04-05 | Mitsubishi Electric Corp | Multilayer planar waveguide |
| JP3990301B2 (en) * | 2003-02-28 | 2007-10-10 | 日本特殊陶業株式会社 | Wiring board |
| JP4508540B2 (en) * | 2003-03-04 | 2010-07-21 | 京セラ株式会社 | Wiring board and electronic device |
| JP2005019483A (en) * | 2003-06-24 | 2005-01-20 | Hitachi Ltd | Through-hole structure, wiring board, and electronic device |
| JP5155582B2 (en) * | 2007-03-30 | 2013-03-06 | 京セラ株式会社 | Wiring board and electronic device |
-
2009
- 2009-09-17 JP JP2009215861A patent/JP2011066223A/en active Pending
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