JP2011066207A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a termination structure provided with a JTE layer greatly deteriorates in breakdown voltage since a level and a defect present in an interface between a semiconductor layer and an insulating film or a fine amount of an external impurity in the insulating film or entering from outside up to the semiconductor interface through the insulating film becomes a generation source for a leakage current and a high current due to breakdown. <P>SOLUTION: The semiconductor device includes an n<SP>-</SP>-type semiconductor layer 2 formed on an n<SP>+</SP>-type semiconductor substrate 1, a first electrode 3 formed thereupon and functioning as a Schottky electrode, a GR layer 4 composed of a first p-type semiconductor layer formed at an end 3E of the first electrode 3 and a surface of the n<SP>-</SP>-type semiconductor layer 2 at a periphery thereof, a JTE layer 5 composed of a second p-type semiconductor layer formed on a bottom part 9B and a side face 9S of a groove 9 arranged in a ring shape at a circumference of the GR layer 4 apart from the GR layer 4 on a surface 2S of the n<SP>-</SP>-type semiconductor layer 2, and increasing in impurity concentration with depth up to a prescribed depth, and an insulating film 7 provided so as to cover the GR layer 4 and JTE layer 5. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a high voltage semiconductor device.

  A conventional power device includes a p-type semiconductor layer and an n-type semiconductor layer formed by ion implantation or impurity diffusion in the surface of a semiconductor substrate, an insulating film formed on the surfaces of the p-type semiconductor layer and the n-type semiconductor layer, and Electrode. In the corner portion (electrode end portion) of the electrode of the power device having such a basic configuration, electric field concentration is likely to occur, and in order to alleviate the electric field concentration, at a position in contact with the electrode terminal portion, An impurity region (hereinafter referred to as a GR (Guard Ring) layer (guard ring layer)) is formed in the semiconductor layer. Further, in order to reduce the electric field concentration generated at the corner portion (electrode end portion) of the GR layer in the direction toward the inside of the semiconductor layer, the surface of the semiconductor layer outside the GR layer is contacted with or separated from the GR layer. Thus, another impurity region (hereinafter referred to as a JTE (Junction Termination Extension) layer) is formed.

Here, FIG. 10 is a longitudinal sectional view showing an electrode termination structure of the conventional power semiconductor device described in Patent Document 1, and more specifically, a shot having a GR layer and a plurality of JTE layers as the termination structure. The longitudinal cross-sectional structure of a key barrier diode is shown. As shown in FIG. 10, a first electrode 3P as a Schottky electrode is formed on the surface of an n ⁻ type semiconductor layer 2P on an n ⁺ type semiconductor substrate 1P. Then, a GR layer 4P made of the first p-type semiconductor layer is formed on the same layer 2P from the surface of the n ⁻ -type semiconductor layer 2P so as to surround the first electrode 3P in a ring shape in contact with the end of the first electrode 3P. It is formed toward the inside. Further, a plurality of JTE layers 5P made of the second p-type semiconductor layer are separated from the GR layer 4P and around the GR layer 4P from the surface of the n ⁻ type semiconductor layer 2P toward the inside of the same layer 2P. It is formed so as to be positioned in a ring shape. A second electrode 6P is formed as an ohmic electrode on the back surface of the n ⁺ type semiconductor substrate 1P. The insulating film 7P is formed on a part of the electrode 3P including the end of the first electrode 3P, on the surface of the portion of the GR layer 4P that protrudes outward from the end of the first electrode 3P, and on each JTE layer. It is formed on the surface of 5P and on the surface of n ⁻ type semiconductor layer 2P.

  As described above, the termination structure of FIG. 10 relaxes the electric field concentration at the GR layer 4P for relaxing the electric field at the end of the first electrode 3P and at the end (corner) 4PE of the GR layer 4P. A plurality of JTE layers 5P.

Such a semiconductor device having a termination structure composed of the GR layer 4P and the JTE layer 5P can obtain a breakdown voltage close to the ideal breakdown voltage calculated from the thickness of the n ⁻ -type semiconductor layer 2P and the impurity concentration.

JP 2003-101039 A

However, in the termination structure provided with the JTE layer 5P as shown in FIG. 10, the level or defect existing in the interface 8P between the n ⁻ type semiconductor layer 2P and the insulating film 7P, or the interface 8P from the insulating film 7P is formed. Either a small amount of foreign impurities entering through the interface or a small amount of foreign impurities entering from the outside to the interface 8P through the insulating film 7P becomes a source of leakage current and a yield point, and the breakdown voltage is greatly increased. There was a case where it deteriorated.

  The present invention has been made to solve such problems, and suppresses deterioration of breakdown voltage due to the effects of defects, levels and foreign impurities existing on the surface of the first conductivity type semiconductor layer. An object of the present invention is to provide a semiconductor device withstand voltage.

  A semiconductor device according to a subject of the present invention includes a first conductivity type semiconductor layer, an electrode formed on a main surface of the semiconductor layer, an end portion of the electrode in the main surface of the semiconductor layer, and the electrode A second conductivity type guard ring layer formed from a portion located immediately below the peripheral portion of the end portion toward the inside of the semiconductor layer and surrounding the electrode; and spaced apart from the guard ring layer Then, at least one formed from a portion located outside the peripheral portion of the end portion of the main surface of the semiconductor layer toward the inside of the semiconductor layer so as to surround the guard ring layer. An impurity concentration increases as the depth increases to a predetermined depth from the bottom of the at least one groove toward the inside of the semiconductor layer, and is formed so as to surround the guard ring layer. At least one The second conductivity type JTE layer, and an insulating film formed on the main surface of the semiconductor layer so as to cover the surface of the guard ring layer and the surface of the at least one JTE layer. It is characterized by that.

  According to the subject of the present invention, the JTE layer whose impurity concentration increases as the depth increases to a predetermined depth is formed in the region immediately below the bottom of the groove formed on the surface of the first conductivity type semiconductor layer. The electric field strength applied to the surface of the first conductivity type semiconductor layer when a voltage is applied can be reduced. Moreover, according to the subject matter of the present invention, even if the charged state of the surface of the first conductivity type semiconductor layer changes, the surface of the first conductivity type semiconductor layer in which no groove is formed is compared with the bottom of the JTE layer. Therefore, the fluctuation of the electric field intensity distribution at the end of the JTE layer can be suppressed. Further, when the JTE layer is formed by the ion implantation method, it is not necessary to perform multi-stage ion implantation, and the JTE layer may be formed shallowly, so that the semiconductor device of the present invention can be manufactured more easily.

1 is a top view schematically showing a semiconductor device according to a first embodiment of the present invention. 1 is a longitudinal sectional view showing a semiconductor device according to a first embodiment of the present invention. It is an impurity profile figure which shows the impurity concentration distribution of the depth direction in the JTE layer of the semiconductor device which concerns on Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on the modification 1 of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on the modification 2 of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on the modification 3 of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on the modification 4 of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on the modification 5 of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which concerns on a prior art.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

(Embodiment 1)
In the present embodiment, a structure of a Schottky barrier diode and a manufacturing method thereof will be described as an example of a semiconductor device according to the present invention.

  Here, FIG. 1 is a top view showing the semiconductor device according to the present embodiment. FIG. 2 is a longitudinal sectional view with respect to the broken line A1-A2 of the top view 1. Hereinafter, each cross-sectional view of the semiconductor device described in this embodiment mode represents a vertical cross-sectional view regarding the disconnection A1-A2 in the top view 1 of the semiconductor device. In FIG. 1, for convenience of illustration, illustration of the insulating film 7 and the groove 9 disposed corresponding to each JTE layer 5 shown in FIG. 2 is omitted.

The termination structure of the Schottky barrier diode shown in FIG. 2 includes (1) an n ⁻ type semiconductor layer (corresponding to a first conductivity type semiconductor layer) 2 formed on the upper surface of the n ⁺ type semiconductor substrate 1, and ( 2) a first electrode 3 functioning as a Schottky electrode formed on the main surface 2S of the n ⁻ type semiconductor layer 2; and (3) a first electrode 3 within the main surface 2S of the n ⁻ type semiconductor layer 2. n from the position portion 2SP immediately below the end perimeter portion and the end portion 3E positioned immediately below the 3E ^- toward the interior of the type semiconductor layer 2, are formed so as to surround the first electrode 3 in a ring shape A GR layer 4 composed of a first p-type (corresponding to the second conductivity type) semiconductor layer, and (4) an n ⁻ -type semiconductor layer 2 so as to surround the GR layer 4 so as to be spaced apart from the GR layer 4. phosphorus toward the interior of the type semiconductor layer 2 ^- from a part located on an outer side than the peripheral portion of the end portion 3E among the main surface 2S n A plurality of grooves 9 which are formed in Jo, (5) for each groove 9, from both parts of the bottom 9B and the side surface 9S of the groove 9 n ^- toward the interior of the type semiconductor layer 2, the GR layer 4 A plurality of JTE layers 5 made of a second p-type semiconductor layer formed in a ring shape so as to surround, and (6) a surface 2SP of the GR layer 4 and a surface of each JTE layer 5 so as to cover the surface. An insulating film 7 provided on the upper surface of the end portion 3E of one electrode 3 and on the main surface 2S of the n ⁻ type semiconductor layer 2 located outside the end portion 3E; and (7) an n ⁺ type semiconductor substrate. And a second electrode 6 functioning as an ohmic electrode formed on the back surface of the first electrode.

  As shown in the top view of FIG. 1, the GR layer 4 entirely surrounds the end 3 </ b> E (FIG. 2) of the first electrode 3 in a ring shape, and is a ring formed separately from the GR layer 4. Each of the plurality of JTE layers 5 in the shape surrounds the first electrode 3 and the GR layer 4 as a whole. Note that the shape of the GR layer 4 is not limited to a ring shape, and may be, for example, a quadrilateral shape. In short, it is sufficient that the GR layer 4 surrounds the entire periphery of the end portion of the first electrode 3. Similarly, the shape of each groove 9 and each JTE layer 5 immediately below it is not limited to the ring shape which is an example. In short, each groove 9 and each JTE layer 5 immediately below it are the first electrode 3 and It suffices to have a shape that can surround the GR layer 4 as a whole. These points are equally established in each modified example described later.

The surface of the GR layer 4 is in contact with the back surface of the end 3E of the first electrode 3 formed on the main surface 2S of the n ⁻ type semiconductor layer 2 so that the first electrode 3 can be applied when a reverse voltage is applied. It functions as a GR for alleviating electric field concentration occurring at the end 3E (particularly at its corner).

Each JTE layer 5 is formed immediately below the bottom portion 9B and the side surface 9S of the corresponding groove 9 and is disposed so as to be spaced apart from the GR layer 4 and in a ring shape around the GR layer 4. . A plurality of grooves 9 are formed in the main surface 2S located outside the GR layer 4 of the n ⁻ type semiconductor layer 2, and the JTE layer 5 is formed in each groove 9. Each JTE layer 5 is arranged to be separated from each other.
FIG. 3 shows the concentration distribution of the second conductivity type impurity in the depth direction from the bottom of the groove 9 of each JTE layer 5 to the inside of the n ⁻ type semiconductor layer 2 in the semiconductor device of the present embodiment of the present invention ( It is the figure which showed the impurity profile. In FIG. 3, the profile indicated by the solid line (A) is an example of the profile of the JTE layer 5 of the semiconductor device of this embodiment, and the profile indicated by the dotted line (B) is formed by a multi-stage ion implantation process. It is an example of a box type profile. Here, the impurity concentration immediately below the bottom of the groove 9 is set to the same value in both profiles in order to ensure the breakdown voltage at the bottom 9B and the side surface 9S or the main surface 2S of the groove 9.

  The JTE layer 5 functions as a JTE for alleviating electric field concentration occurring at the end (corner portion) of the GR layer 4 when a reverse voltage is applied. Therefore, the formation of a plurality of JTE layers 5 as shown in FIG. 2 increases the electric field relaxation effect at the end of the GR layer 4. Of course, even when the number of the grooves 9 and the JTE layers 5 located immediately below them is one, the electric field relaxation effect at the end of the GR layer 4 can be obtained. The number of layers 5 may be set to be one. This point is also valid in each modification described later.

One of the features of the present embodiment is that the JTE layer 5 is also formed in the portion of the n ⁻ type semiconductor layer 2 located immediately below the side surface 9S of the groove 9. In the case of having this feature point, in contrast to the case where the JTE layer is not formed immediately below the side surface 9S of the groove 9, the JTE layer 5A that is adjacent to and faces the GR layer 4 among the plurality of JTE layers 5 is used. Since the area in the longitudinal section of the layer increases, the electric field concentration applied to the end of the GR layer 4 is widened and uniformed, so that the effect of further reducing the electric field concentration at the end of the GR layer 4 can be obtained. . Moreover, since the JTE layer 5 corresponding to the portion immediately below the side surface 9S of each groove 9 is formed for all the grooves 9, the electric field concentration generated in the corner portion 5E of each JTE layer 5 is also adjacent. There is also an effect that the JTE layers 5 are relaxed by widening the electric field distribution.

In the present embodiment, the position of the bottom portion 5B of the portion of the JTE layer 5 formed immediately below the bottom portion 9B of the groove 9 is deeper as viewed from the main surface 2S than the position of the bottom portion 4B of the GR layer 4. Thus, the thickness of the portion of the JTE layer 5 formed immediately below the bottom portion 9B of the groove 9 is set. By adopting this structure, the bottom 5B of the deeper JTE layer 5 and its peripheral part attract the electric field around the GR layer 4 toward the bottom 5B side of the JTE layer 5, so that the electric field distribution around the GR layer 4 is n ⁻ type. As a result, the semiconductor layer 2 is more biased in the internal direction. As a result, there is an effect that the electric field strength at the main surface 2S of the n ⁻ type semiconductor layer 2 can be reduced.

In the structure of the conventional JTE 5P shown in FIG. 10, electric field concentration occurs at the end (corner) 5PE of each JTE layer 5P generated when a reverse voltage is applied, and the n ⁻ -type semiconductor layer 2P is affected by the influence. An electric field is also generated at the interface 8P between the main surface of the insulating film 7P and the insulating film 7P.

In contrast, in the present embodiment, since the JTE layer 5 is formed immediately below the groove 9, the electric field concentration portion (corner portion) 5 E at the end of the JTE layer 5 and the main part of the n ⁻ -type semiconductor 2. The distance from the surface 2S is set longer than in the case of FIG. In this characteristic structure, the electric field strength applied to the main surface 2S of the n ⁻ type semiconductor layer 2 when a reverse voltage is applied can be made smaller than in the case of FIG. As a result, even if there are defects, interface states, and a small amount of impurities that enter the interface 8 through the insulating film 7 at the interface 8 between the main surface 2S of the n ⁻ type layer 2 and the insulating film 7. Since the electric field strength at the main surface 2S of the n ⁻ -type semiconductor layer 2 is sufficiently small, the above defects and the like cannot be a source of leakage current and a yield point. For this reason, it is possible to realize a semiconductor device having an ideal withstand voltage with suppressed withstand voltage deterioration.

In the present embodiment, since the groove 9 is provided, the thickness 10 of the insulating film 7 on the bottom portion 9B of the groove 9 is the main surface 2S of the n ⁻ type semiconductor layer 2 where the groove 9 is not formed. It is set to be thicker than the thickness 11 of the upper insulating film 7. With this structure, the distance from the bottom 9B of the groove 9 where the JTE layer 5 is formed to the surface 7S of the insulating film 7 is made larger than the distance from the main surface 2S of the n ⁻ type semiconductor layer 2 to the surface 7S of the insulating film 7. Can be set longer. For this reason, impurities entering from the outside through the insulating film 7 are difficult to reach the JTE layer 5 located immediately below the bottom 9B of the groove 9, and the interface 8J between the JTE layer 5 and the insulating film 7 is caused by impurities from the outside. It becomes difficult to be contaminated. As a result, it is possible to provide a highly reliable semiconductor device with little deterioration in breakdown voltage even after long-term use.

In other words, the effect of the present embodiment can reduce the electric field strength at the corner portion 5E at the end of the JTE layer 5 caused by the surface charge existing on the main surface 2S of the n ⁻ type semiconductor layer 2. .

The so-called turnover phenomenon, in which the breakdown voltage significantly deteriorates after breakdown occurs at the ideal breakdown voltage of the semiconductor device, changes in the charged state of the main surface 2S of the n ⁻ type semiconductor layer 2 due to breakdown, and the p-type semiconductor This occurs due to a change in the electric field strength distribution of the GR4 or JTE layer 5 as a layer. However, in this embodiment, n ^- even if the charged state of the type semiconductor layer 2 of the main surface 2S is changed, n ^- if the bottom 5B of the type semiconductor layer 2 of the main surface 2S and JTE layer 5 is shown in FIG. 9 and Since it is farther in comparison, fluctuations in the electric field strength distribution at the end of the JTE layer 5 can be suppressed. Therefore, in this embodiment mode, it is possible to provide a highly reliable semiconductor device that can be used repeatedly without causing a turnover phenomenon even when breakdown occurs.

Here, as the depth T of the groove 9 in which the JTE layer 5 is formed increases, the main surface of the n ⁻ -type semiconductor layer 2 due to the influence of the electric field concentration portion generated at the ends of the GR layer 4 and the JTE layer 5. The electric field strength at 2S is reduced. However, if the depth T of the groove 9 becomes too deep, the original effect that the JTE layer 5 relaxes the electric field concentration of the GR layer 4 is diminished. Therefore, it is desirable that the depth T of the groove 9 where the electric field relaxation effect is remarkably exhibited is generally within a range of 1/3 or more to 2 times or less of the thickness of the GR layer 4.

Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIG. 4 showing a cross-sectional view of the semiconductor device during the manufacturing process. Here, a method for manufacturing a Schottky barrier diode using 4H—SiC (silicon carbide) as the n ⁺ type semiconductor substrate 1 will be described.

First, in the first step, a substrate having an n ⁻ type semiconductor layer 2 formed on an n ⁺ type semiconductor substrate 1 is prepared (see FIG. 4A). For example, the n ⁺ type semiconductor substrate 1 is a 4H—SiC (silicon carbide) substrate having a resistivity of 0.02 Ω · cm. As the n ⁻ type semiconductor layer 2, an n type impurity having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm is employed. The impurity concentration and thickness of the n ⁻ type semiconductor layer 2 differ depending on the design breakdown voltage of the semiconductor device.

In the next second step, the mask 12 formed on the main surface 2S of the n ⁻ -type semiconductor layer 2 is patterned to form a ring-shaped opening in the mask 12, and then dry etching is performed to form the opening. A plurality of ring-shaped grooves 9 corresponding to the above are formed (see FIG. 4B). For example, the depth of the groove 9 is 0.3 μm.

In the next third step, after the mask 12 is removed and a new mask 13 is patterned to form the opening of the ring-shaped groove 9 formed on the main surface of the n ⁻ type semiconductor layer 2. Then, p-type impurities are ion-implanted so as to have the impurity profile shown in FIG. Next, by etching the vicinity of the surface of the injection portion, a plurality of JTE layers 5 corresponding to the bottom portion 9B and the side surface 9S of each groove 9 are formed (see FIG. 4C).

Here, the ion implantation in the third step and the subsequent etching will be described in detail. As ion implantation, for example, ion implantation of p-type impurity aluminum is performed with an acceleration voltage of 350 keV and a single acceleration voltage (one step). Under such ion implantation conditions, as shown in FIG. 3, the impurity concentration gradually increases from directly below the bottom portion 9B of the implanted trench 9 toward the inside of the n ⁻ type semiconductor layer 2, and from just below the bottom portion of the trench. An implanted impurity profile having an impurity concentration of 1 × 10 ¹⁸ cm ^{−3 at the} maximum value is formed at a position of 0.35 μm. As the etching after ion implantation, a region of 0.1 μm is removed by etching from the surface of the implanted region toward the inside of the n ⁻ type semiconductor layer.

This etching is performed for the purpose of independently adjusting the impurity concentration immediately below the bottom portion 9B of the groove 9 and the maximum impurity concentration. For example, in one-step ion implantation, the impurity concentration and the maximum impurity concentration on the surface of the implantation region (that is, directly below the bottom 9B of the groove 9) cannot be adjusted independently, but etching at a desired depth after one-step ion implantation. By performing the above, both the impurity concentration immediately below the bottom portion 9B of the groove 9 and the maximum impurity concentration can be set to a desired range.
In the present embodiment, by such a method, the impurity concentration immediately below the bottom 9B of the groove 9 becomes 2 × 10 ¹⁷ cm ⁻³ after etching after ion implantation, and n ⁻ Impurity concentration gradually increases toward the inside of the type semiconductor layer 2, and an implanted impurity profile having an impurity concentration of 1 × 10 ¹⁸ cm ^{−3 at a} maximum value of 1 × 10 ¹⁸ cm ⁻³ is provided at a position of 0.25 μm deep from the bottom 9B of the trench 9. The JTE layer 5 can be formed.

In the next fourth step, the mask 13 is removed, a new mask 14 is patterned, a ring-shaped opening is formed at a position separated from the JTE layer 5, and p-type impurities are ion-implanted. Te, n ^- from the main surface 2S of the type semiconductor layer 2 n ^- toward the inside of the type semiconductor layer 2, to form a ring-shaped GR layer 4 (see FIG. 4 (d)). For example, the dose was set to 1.25 × 10 ¹³ cm ⁻² , the acceleration voltage was divided into 10 to 700 keV, and aluminum was implanted as a p-type impurity. A GR layer 4 having a box-type profile with a thickness of 0.8 μm and a concentration of 5 × 10 ¹⁷ cm ⁻³ is formed, and the impurity concentration of the GR layer 4 is higher than the impurity concentration of the JTE layer 5.

  In the next fifth step, after removing the mask 14, activation annealing is performed on the impurities implanted into the GR layer 4 and the JTE layer 5. For example, the activation anneal was performed at a temperature of 1700 ° C. for 10 minutes. The process diagram is not shown.

In the next sixth step, a second electrode 6 made of nickel that functions as an ohmic electrode is formed on the back surface of the n ⁺ type semiconductor substrate 1, and then the main surface 2S and GR of the n ⁻ type semiconductor layer 2 are formed. A first electrode 3 made of titanium or nickel that functions as a Schottky electrode is formed on a part of the layer 4 (see FIG. 4E). An outer end 3 </ b> E of the first electrode 3 is in contact with the GR layer 4.

In the next seventh step, on the edge 3E of the outer periphery of the first electrode 3, on the surface of the GR layer 4, on the surface of the JTE layer 5, and on the main surface 2S of the n ⁻ type semiconductor layer 2, An insulating film 7 is formed (see FIG. 4F).

  Through the above steps, the semiconductor device shown in FIG. 2 is completed.

  The greater the number of JTE layers 5, the more effective the suppression of breakdown voltage degradation. In the example, it was effective and sufficient that the number of the JTE layers 5 was 3 to 4. Even if the number of the JTE layers 5 was further increased, the actual effect was almost the same as that when the number of the JTE layers 5 was 3 to 4.

  Further, for example, the width W5 of each JTE layer 5 is 5 μm, and the distance from the end of the JTE layer 5 to the end of the next JTE layer 5 is 3 μm. The width W4 of the GR layer 4 is 10 μm, and the distance d from the end of the GR layer 4 to the end of the next adjacent JTE layer 5A is 2 μm.

  In the semiconductor device of this embodiment, the p-type semiconductor layers of the GR layer 4 and the JTE layer 5 both contain p-type impurities. For example, the impurity concentration of the GR layer 4 is set to be higher than the impurity concentration of the JTE layer 5. However, the impurity concentrations of the GR layer 4 and the JTE layer 5 may be similar.

Note that the JTE layer 5 having a box-type profile is formed without making the impurity concentration distribution in the depth direction of the JTE layer 5 of the present embodiment of the present invention a distribution in which the impurity concentration increases as the depth increases. In order to obtain the same breakdown voltage, it is necessary to increase the number of acceleration voltage stages (acceleration voltage types) and to increase the thickness of the JTE layer. For example, an acceleration voltage is divided into multiple stages of 40~700keV a box type to the bottom 9B JTE layer 5 having a thickness of approximately 2 × 10 ¹⁷ cm ^-3 impurity concentration at 0.7μm directly below the portion of the groove 9 Compared with the case of the profile, the maximum acceleration voltage is reduced by half according to the profile of the present invention. For this reason, the depth from the bottom 9B of the groove 9 to the maximum impurity concentration is as thin as half or less of the thickness of the JTE layer in the box type profile.

In the case of a box-type profile, there are problems that a multi-stage acceleration voltage is required and it takes a long time to switch the acceleration voltage, and that the implantation time is long because impurity implantation is required under high acceleration voltage conditions. .
In contrast, in the impurity implantation profile in the depth direction of the JTE layer 5 according to the present embodiment of the present invention, the maximum acceleration voltage is reduced from 700 keV to 350 keV, compared to the box type profile, and the number of acceleration voltage stages. Is reduced from six stages to one stage, the effect of shortening the implantation time and improving the throughput of the implantation process can be obtained.

Further, the impurity concentration just below the bottom portion 9B of the groove 9 may be larger or smaller than the impurity concentration of the box type profile as long as the breakdown voltage of the JTE layer end portion 5E can be secured. Such control can be performed by controlling the etching amount in the third step. The impurity profile of the JTE layer 5 only needs to have an impurity concentration inside the n ⁻ type semiconductor layer 2 that is higher than the impurity concentration immediately below the bottom 9B of the trench.

Further, in order to adjust the electric field intensity generated at the bottom 9B and the side surface or main surface 2S of the groove 9, the concentration gradient of a part of the impurity profile in the JTE layer 5 is made more gentle, or the impurity concentration is lower than the maximum impurity concentration. A second impurity concentration peak may be provided.
Further, the acceleration voltage for impurity implantation does not have to be one stage, and may be a plurality of stages. In addition to etching, the impurity profile can be adjusted by increasing the number of stages of acceleration voltage. In particular, by performing two-stage implantation in combination with a second acceleration voltage that is lower than the acceleration voltage for forming the maximum impurity concentration, impurities near the surface of the JTE layer 5 can be obtained without performing etching after ion implantation. The concentration gradient can be made gentle, and the electric field strength on the surface of the JTE layer 5 can be further reduced. Further, the impurity concentration in the vicinity of the depth that becomes the surface of the JTE layer 5 after etching is made uniform in the depth direction so that the impurity concentration in the vicinity of the surface of the JTE layer 5 subjected to etching after ion implantation does not fluctuate due to etching variations. Two-stage injection may be performed.

It should be noted that the maximum impurity concentration in the JTE layer 5 of the present embodiment of the present invention should be higher than the impurity concentration of the box type profile having the same breakdown voltage, but when the maximum impurity concentration in the JTE layer 5 is too high. May cause electric field concentration at the end portion 5E of the JTE layer, and the breakdown voltage may be reduced. Therefore, the maximum impurity concentration in the JTE layer 5 is desirably 2 to 6 times the impurity concentration of the box type profile having the same breakdown voltage. In the JTE layer 5 of the present embodiment, as shown in FIG. 3, the maximum impurity concentration is 1 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the box-type profile shown is 5 × 10 ¹⁷ cm ⁻³ . It is about double.

  In addition, the distribution of impurities in the depth direction in the JTE layer 5 of the present embodiment of the present invention is a distribution in which the impurity concentration increases as the depth increases to a predetermined depth as a whole. As described above, the impurity concentration does not continuously increase monotonously until reaching the deepest portion, and there is a portion where the impurity concentration decreases in the depth direction toward the boundary in the deepest portion of the JTE layer 5. Needless to say.

(Modification 1)
FIG. 5 is a longitudinal sectional view showing a configuration of a semiconductor device according to Modification 1 of Embodiment 1 (FIG. 2). The only difference between the semiconductor device shown in FIG. 5 and the semiconductor device shown in FIG. 2 is that no JTE layer is formed immediately below the side surface 9S of each groove 9, and only the bottom 9B of each groove 9 ^The only difference is that the JTE layer 5 is formed only in the -type semiconductor layer 2. Other structures are the same as the corresponding structures shown in FIG. 2, and detailed descriptions of other reference numerals are omitted.

Also in the present modification, as in the first embodiment, the distance from the electric field concentration portion (corner portion) of each JTE layer 5 to the surface 2S of the n ⁻ type semiconductor layer 2 where the groove 9 is not formed. However, since it becomes larger than that of the structure of the conventional example of FIG. 10, the electric field intensity at the surface 2S of the n ⁻ type semiconductor layer 2 can be reduced as compared with the conventional example of FIG.

(Modification 2)
FIG. 6 is a longitudinal sectional view showing a configuration of a semiconductor device according to Modification 2 of Embodiment 1 (FIG. 2). The only difference between the semiconductor device shown in FIG. 6 and the semiconductor device shown in FIG. 2 is that the n ⁻ -type semiconductor layer at the bottom of the groove 9P located farthest from or outside the GR layer 4 among the plurality of grooves 9 The depth TP from the surface 2S of No. 2 is deepest in comparison with the depth T at the bottom of the other grooves 9a, 9b, 9c (TP> T). The other structure is the same as the corresponding structure of the semiconductor device of FIG. 2, and therefore, the effects described in the first embodiment can be obtained in the same way in the present modification.

In each JTE layer 5, the thickness from the bottom of the corresponding groove 9 to the bottom 5B, 5BP of each JTE layer is set to be the same as in the first embodiment. The bottom 5BP of the JTE layer 5P formed at the bottom of the most distant groove 9P and the bottom of the side surface is located at the deepest place than any of the bottom 4B of the RG layer 4 and the bottom 5B of the other JTE layers 5. is doing. Therefore, in the JTE layer 5P, compared with the other JTE layers 5, the electric field concentration portion (corner portion) of the same layer 5P is farthest from the surface 2S of the n ⁻ type semiconductor layer 2 and from the outside. The electric field strength on the surface 2S of the n ⁻ type semiconductor layer 2 in the vicinity of the groove 9P at the outermost periphery that is most susceptible to the influence of the impurities can be further reduced as compared with the case of the first embodiment.

As a further modification of this modification, the depth of the bottom of the groove 9 in which the JTE layer 5 is formed immediately below the groove 9 is farther than the groove 9 located near the GR layer 4. You may set the depth of the bottom part of each groove | channel 9a, 9b, 9c, 9P so that it may become so deep that it becomes nine. That is, the depth of the bottom of each groove 9a, 9b, 9c, 9P shown in FIG. 6 is (depth of the bottom of the groove 9a) <(depth of the bottom of the groove 9b) <(depth of the bottom of the groove 9c). It is corrected so that the relationship of “depth” <(depth of the bottom of the groove 9P) is satisfied. In such a further modified embodiment, the electric field concentration portion of the JTE layer 5 (corner portion), to the extent that the JTE layer 5 is positioned farther than GR layer 4, n ^- type semiconductor layer 2 As a result, the electric field strength on the surface 2S of the n ⁻ -type semiconductor layer 2 becomes smaller as the position of the surface 2S moves away from the surface 2SP of the GR layer 4 as a result. The effect to say is acquired. Regarding the manufacturing method, the groove 9 having a deeper bottom can be formed by further repeating the second step described above.

(Modification 3)
FIG. 7 is a longitudinal sectional view showing a configuration of a semiconductor device according to Modification 3 of Embodiment 1 (FIG. 2). The only difference between the semiconductor device shown in FIG. 7 and the semiconductor device shown in FIG. 2 is that one JTE layer 5 is formed so that all the grooves 9 are connected to one JTE layer 5. In the point. That is, in the structure of FIG. 7, a part of the JTE layer 5 is formed from the surface 2SA of the n ⁻ type semiconductor layer 2 located between the adjacent grooves 9 toward the inside of the n ⁻ type semiconductor layer 2. A part of such a JTE layer 5 is combined with the other part of the JTE layer 5 formed from the bottom of each of the adjacent grooves 9 and the lower part of the side surface, so that one JTE layer 5 shown in FIG. Is formed. Other structures are the same as the corresponding structures in the first embodiment, and therefore, the effects of the first embodiment described above can be exhibited similarly.

According to the present modification, in particular, the JTE layer 5 that is a p-type semiconductor layer is also formed immediately below the surface 2SA of the n ⁻ -type semiconductor layer 2 between the adjacent grooves 9. A new effect is obtained that the capacity can be adjusted.

  The JTE structure described in the first embodiment can also be applied to a semiconductor device having a GR layer structure that is different from the GR layer 4 in the first embodiment. It describes as the modifications 4 and 5. Needless to say, the effects described in the first embodiment can be obtained in both of the fourth and fifth modifications.

(Modification 4)
FIG. 8 is a longitudinal sectional view showing a configuration of a semiconductor device according to Modification 4 of Embodiment 1 (FIG. 2). The semiconductor device shown in FIG. 8 is different from the semiconductor device shown in FIG. 2 in that the end portion 3AE and the peripheral portion 2SP of the first electrode 3A are formed with a p-type GR layer 4A in a region immediately below the end portion 3AE. Further, it is disposed in the guard ring layer groove 9a1. Because of this structure, a part of the insulating film 7A extends to the inside of the groove 9a1 and covers the entire end peripheral portion 2SPA. The impurity concentration profile of the GR layer 4 is the same as that of the JTE layer 5 described in detail in the first embodiment. Other structures are the same as the corresponding structures in the first embodiment.

  As described above, the impurity concentration profile of the GR layer 4 does not have to be a box-type profile, and the depth is increased to a predetermined depth as in the JTE layer 5 described in detail in the first embodiment (FIG. 3). An impurity profile in which the impurity concentration increases can be used. In this case, the impurity concentration of the GR layer 4 in contact with the end portion 3AE of the first electrode 3A is set lower than the maximum impurity concentration in the GR layer 4 (same as the maximum impurity concentration of the JTE layer 5). . When the impurity profiles of the GR layer 4 and the JTE layer 5 are made the same, the maximum impurity concentration, the spacing between the JTE layers, and the like may be controlled so that the electric field does not concentrate on the end portion 3AE of the first electrode 3A.

  By making the impurity concentration profile of the GR layer 4 the same as the impurity profile of the JTE layer 5, in the manufacturing process described in the first embodiment, the ring-shaped groove corresponding to the JTE layer 5 and the GR layer 4 in the second process. Then, the impurity region may be implanted by forming an opening region corresponding to the JTE layer 5 and the GR layer 4 in the mask 13 in the third step. By doing so, there is no need for the fourth step of implanting ions only in the GR layer 4, so that the throughput is improved.

According to this modification, the distance between the electric field concentration portion (corner portion) of the GR layer 4A and the surface 2S of the n ⁻ type semiconductor layer 2 is larger than that in the case of FIG. 2, and in addition, directly above the GR layer 4A. Since the thickness of the insulating film 7A can be increased, the electric field strength of the surface 2S of the n ⁻ type semiconductor layer 2 around the GR layer 4A can be reduced, and the area around the GR layer 4A can be reduced. It is also possible to suppress breakdown voltage degradation due to levels and defects on the surface 2S of the n ⁻ type semiconductor layer 2.

(Modification 5)
FIG. 8 is a longitudinal sectional view showing a configuration of a semiconductor device according to Modification 5 of Embodiment 1 (FIG. 2). The only difference between the semiconductor device shown in FIG. 8 and the semiconductor device shown in FIG. 2 is that the third layer surrounding the first electrode 3 in a ring shape is in contact with the end 3E of the first electrode 3 in the GR layer 4B. The p-type semiconductor layer (corresponding to the second GR layer) 15 is disposed. The impurity concentration of the third p-type semiconductor layer 15 is set higher than the impurity concentration of the GR layer 4B. Other structures are the same as the corresponding structures shown in FIG. The third p-type semiconductor layer 15 has a function of relaxing the electric field concentration at the corner portion of the end portion 3E of the first electrode 3.

(Appendix)
Note that the termination structure according to the subject of the present invention is applicable to other power semiconductor devices such as power MOSFETs in addition to the Schottky diodes shown in the first embodiment and the modifications thereof.

  Further, regarding the impurity conductivity type in the present invention, when n-type is defined as the first conductivity type, p-type is defined as the second conductivity type, and conversely, p-type is defined as the first conductivity type. The n-type becomes the second conductivity type.

  While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

1 n ⁺ type semiconductor substrate, 2 n ⁻ type semiconductor layer, 3 first electrode, 4 GR layer, 5 JTE layer, 6 second electrode, 7 insulating film, 8 n ⁻ type semiconductor layer and insulating film interface, 9 groove.

Claims (9)

A first conductivity type semiconductor layer;
An electrode formed on the main surface of the semiconductor layer;
The semiconductor layer is formed from the portion located immediately below the end portion of the electrode and the peripheral portion of the end portion toward the inside of the semiconductor layer in the main surface of the semiconductor layer, and so as to surround the electrode. A second conductivity type guard ring layer;
Formed from the portion of the main surface of the semiconductor layer located outside the peripheral portion of the end toward the inside of the semiconductor layer so as to surround the guard ring layer while being spaced apart from the guard ring layer. And at least one groove,
The impurity concentration increases as the depth increases from the bottom of the at least one groove toward the inside of the semiconductor layer to a predetermined depth, and the at least one groove is formed so as to surround the guard ring layer. A second conductivity type JTE layer;
An insulating film formed on the main surface of the semiconductor layer so as to cover the surface of the guard ring layer and the surface of the at least one JTE layer;
Semiconductor device. The semiconductor device according to claim 1,
The bottom of the at least one JTE layer is deeper than the bottom of the guard ring layer when viewed from the main surface of the semiconductor layer,
Semiconductor device. The semiconductor device according to claim 1 or 2,
The at least one JTE layer is formed from the side surface of the at least one groove toward the inside of the semiconductor layer,
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The film thickness of the portion on the bottom of the at least one groove in the insulating film is the film thickness of the portion on the main surface where the at least one groove is not formed in the insulating film. Characterized by being thicker than,
Semiconductor device. A semiconductor device according to any one of claims 1 to 4,
A plurality of the at least one groove;
There are a plurality of the at least one JTE layer corresponding to each groove,
Of the plurality of grooves, the depth of the groove located farthest from the guard ring layer from the main surface is the deepest,
Semiconductor device. The semiconductor device according to claim 3 or 4, wherein
A plurality of the at least one groove;
One JTE layer is formed to connect to each of the plurality of grooves,
Semiconductor device. A semiconductor device according to claim 1,
The end portion of the electrode and the peripheral portion of the end portion are disposed in a groove for a guard ring layer in which the guard ring layer is formed immediately below.
Semiconductor device. The semiconductor device according to claim 7,
In the guard ring layer, the impurity concentration increases as the depth increases to a predetermined depth from the bottom of the groove for the guard ring layer toward the inside of the semiconductor layer,
Semiconductor device. A semiconductor device according to claim 1,
The guard ring layer is
The semiconductor layer is formed so as to surround the electrode from the portion located immediately below the end portion and the periphery of the end portion of the main surface of the semiconductor layer toward the inside of the guard ring layer, and It is characterized by comprising a second guard ring layer containing the second conductivity type impurity having a higher concentration than the impurity concentration of the guard ring layer.
Semiconductor device.

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