JP2011066146A - Semiconductor device, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device like a high-breakdown-voltage hybrid transistor which has small parasitic resistance and large current driving capability. <P>SOLUTION: A semiconductor layer 22 of a first conductivity type includes a base region 9 of the first conductivity type. An emitter region 10 of a second conductivity type is provided in the base region 9. In the semiconductor layer 22, an impurity layer 23 of the second conductivity type is provided adjacently to the base region 9 from a surface of the semiconductor layer 22 to a predetermined depth smaller than the thickness of the semiconductor layer 22. The impurity layer 23 is provided with a collector region 11 of the first conductivity type and a drain region 14 of the second conductivity type, apart from the region layer 9. On the surface of the semiconductor layer 22, a gate electrode 13 is provided on an end of the emitter region 10 and partially on the base region 9 and impurity layer 23, through the gate insulating film 12. The semiconductor device includes a first electrode 15 connected to the emitter region 10 and base region 9 in common, and a second electrode 16 connected to the collector region 11 and drain region 14 in common. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device formed on an SOI (Silicon on insulator) substrate and a plasma display device using the semiconductor device.

  In recent years, a silicon integrated circuit in which a lateral insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), which is an output driving device, and a control circuit composed of a low breakdown voltage transistor are mounted on a single chip on an SOI substrate, It is used as a thin display drive IC.

  FIG. 15 is a circuit diagram illustrating an example of an output unit of a display driving IC. As shown in FIG. 15, a 200V class high voltage IGBT 1, high voltage diode 2 and high voltage P-channel MOS transistor 3 are connected to the output terminal of the display driving IC to constitute an output power circuit unit. A level shift circuit 4 composed of a low breakdown voltage transistor is connected to the preceding stage of the output power circuit section. The high breakdown voltage IGBT 1 and the high breakdown voltage P-channel MOS transistor 3 have a function of charging and discharging a capacitive load from a plasma display device, for example. On the other hand, the high breakdown voltage diode 2 has a function of supplying a current from the GND when the potential of the output terminal becomes lower than the GND potential (ground potential).

  The pattern size of the circuit constituting such an output unit is considerably larger than the pattern size of the low voltage driving transistor constituting the internal circuit such as the level shift circuit 4 and the occupied area ratio on the chip is also large. Therefore, in recent years, attempts have been made to reduce the element area of the entire chip by forming a hybrid transistor in which different types of elements having different functions are formed in the same element formation region and integrated.

Ravishankar Sunkavalli and 1 other, "COMPARISON OF HIGH SPEED DI-LIGBT STRUCTURE", Solid-State Electronics, Vol. 41, 1997, pp. 1953-1956

However, the conventional hybrid transistor has the following problems. For example, in a hybrid transistor including an IGBT, a diode, and a P-channel MOS transistor, when a built-in diode including a P-type base region and an N ⁺ drain region operates in a forward direction in a driving state, an N ⁺ emitter region, an N ⁺ drain region, There are two types when the MOS transistor composed of the gate electrode is in the on state and when it is in the off state. When the MOS transistor is in an on state, there arises a problem that the forward current of the built-in diode is reduced. According to the present inventors, this mechanism is considered as follows.

When the MOS transistor is on, the surface of the base region below the gate insulating film is inverted to form a channel. FIG. 16 is a circuit diagram showing an equivalent circuit related to the diode forward characteristic at this time. As shown in FIG. 16, the built-in diode 121 and the channel resistor 119 are connected in parallel, and the parasitic resistance 120 in the drift region, which is the region of the N-type semiconductor layer between the channel end under the gate insulating film and the N ⁺ drain region. Are connected in series. When the built-in diode 121 operates in the forward direction, the emitter electrode (emitter region and base region) is set to the GND potential, and a negative voltage is applied to the N ⁺ drain region. As can be understood from the equivalent circuit of FIG. 16, in this case, only a voltage divided by the ratio of the channel resistance 119 and the parasitic resistance 120 in the drift region is applied to the built-in diode 121.

In the 200V breakdown voltage class element, the impurity concentration of the N-type semiconductor layer is set low and the length of the drift region is set long in order to increase the breakdown voltage. Therefore, the parasitic resistance 120 in the drift region becomes larger than the channel resistance 119. On the other hand, in the P-type base region, the channel resistance does not increase because there is no need to change the structure in order to increase the breakdown voltage. For this reason, the proportion of the parasitic resistance of the drift region in the overall resistance increases with the increase in the breakdown voltage of the element. For example, even if a potential of −1V is applied to the collector electrode 116 connected to the N ⁺ drain region, the forward voltage actually applied to the built-in diode 121 is about 0.13V. This voltage (potential difference) is considerably smaller than the built-in potential in the PN junction composed of the base region and the N-type semiconductor layer. For this reason, the diode 2 shown in FIG. 15 is not formed together with the IGBT in the IGBT formation region surrounded by the trench isolation, but the current driving capability is greatly increased in this structure as compared with the structure formed independently in other regions. descend. Further, if the current drive capability of the built-in diode 2 that is responsible for supplying a current from the GND when the potential at the output terminal is lower than the GND potential is low, the area of the output circuit section is increased in order to reduce the parasitic resistance. This is also a problem in terms of manufacturing cost of the integrated circuit as a whole.

  The present invention has been proposed in view of the above-described conventional circumstances, and an object thereof is to provide a structure of a semiconductor device such as a high voltage hybrid transistor having a small parasitic resistance and a large current driving capability.

  In order to solve the above problems, the present invention employs the following technical means. That is, the semiconductor device according to the present invention includes a first conductivity type semiconductor layer, and the semiconductor layer includes a first conductivity type base region. A second conductivity type emitter region is provided in the base region. The semiconductor device further includes a second conductivity type impurity layer on the semiconductor layer adjacent to the base region over a predetermined depth smaller than the thickness of the semiconductor layer from the surface. The impurity layer is provided with a first conductivity type collector region and a second conductivity type drain region spaced apart from the base region. On the surface of the semiconductor layer, a gate electrode is provided over the end of the emitter region, the base region, and part of the impurity layer via a gate insulating film. Furthermore, a first electrode electrically connected in common to the emitter region and the base region, and a second electrode electrically connected in common to the collector region and the drain region are provided.

  The semiconductor device may further include a first conductivity type buried impurity layer having an impurity concentration higher than that of the semiconductor layer in a semiconductor layer below the second conductivity type impurity layer. Depending on the thickness of the semiconductor layer, the buried impurity layer is not formed immediately below the collector region, so that the breakdown voltage can be further improved.

  Another semiconductor device according to the present invention includes a second conductivity type semiconductor layer, and the semiconductor layer includes a first conductivity type base region. A second conductivity type emitter region is provided in the base region. The semiconductor device further includes a first conductivity type collector region and a second conductivity type drain region provided in the semiconductor layer so as to be spaced apart from the base region. On the surface of the semiconductor layer, a gate electrode is provided via a gate insulating film over the end of the emitter region, the base region, and a part of the semiconductor layer between the base region and the collector region. . Furthermore, a first electrode electrically connected in common to the emitter region and the base region, and a second electrode electrically connected in common to the collector region and the drain region are provided. In addition, the first conductive layer is electrically connected to a part of the base region, passes through a part of the semiconductor layer below the gate electrode from the base region, and is provided in at least the semiconductor layer between the drain region and the gate electrode. An extended impurity region of the mold is provided. Note that the extended impurity region may be provided in the semiconductor layer between the gate electrode and the collector region.

  Still another semiconductor device according to the present invention includes a first portion and a second portion arranged adjacent to each other. The first portion includes a semiconductor layer, and the semiconductor layer includes a first conductivity type base region. A second conductivity type emitter region is provided in the base region. The first portion includes a second conductivity type impurity layer provided in the semiconductor layer adjacent to the base region. The second conductivity type impurity layer is provided with a first conductivity type collector region spaced from the base region. On the surface of the semiconductor layer, a gate electrode is provided via a gate insulating film over the end of the emitter region, the base region, and part of the second conductivity type impurity layer. Similarly to the first portion, the second portion includes the semiconductor layer, and the semiconductor layer includes a base region of the first conductivity type. A second conductivity type emitter region is provided in the base region. The second portion includes a first conductivity type impurity layer provided in the semiconductor layer adjacent to the base region. The first conductivity type impurity layer is provided with a second conductivity type drain region spaced apart from the base region. On the surface of the semiconductor layer, a gate electrode is provided over the end of the emitter region, the base region, and a portion of the first conductivity type impurity layer via a gate insulating film. The gate electrode is continuous with the gate electrode of the first portion. Furthermore, a first electrode electrically connected in common to the emitter region and the base region, and a second electrode electrically connected in common to the collector region and the drain region are provided. The first portion and the second portion are arranged along a direction different from the direction from the base region to the collector region or the direction from the base region to the drain region.

  Still another semiconductor device according to the present invention includes a first portion and a second portion arranged adjacent to each other. The first portion includes a second conductivity type semiconductor layer, and the semiconductor layer includes a first conductivity type base region. A second conductivity type emitter region is provided in the base region. The first portion includes a collector region of a first conductivity type provided in the semiconductor layer so as to be separated from the base region. On the surface of the semiconductor layer, a gate electrode is provided through a gate insulating film over the end of the emitter region, the base region, and a part on the semiconductor layer between the base region and the collector region. Yes. Similarly to the first portion, the second portion includes the second conductivity type semiconductor layer, and the semiconductor layer includes a first conductivity type base region. The second portion includes a drain region of a second conductivity type provided in the semiconductor layer so as to be separated from the base region. On the surface of the semiconductor layer, a gate electrode is provided over the base region and part of the semiconductor layer between the base region and the drain region with a gate insulating film interposed therebetween. The gate electrode is continuous with the gate electrode of the first portion. Furthermore, a first electrode electrically connected in common to the emitter region and the base region, and a second electrode electrically connected in common to the collector region and the drain region are provided. The first portion and the second portion are arranged along a direction different from the direction from the base region to the collector region or the direction from the base region to the drain region.

  As described above, even when the emitter region is not formed in the base region facing the collector region, the current driving capability of the built-in diode can be improved as in the above-described semiconductor devices.

  According to the present invention, even when the MOS transistor structure is in an ON state, the current capability of the built-in diode can be improved as compared with the conventional structure. That is, in the present invention, since the PN junction of the built-in diode can be arranged in the vicinity of the drain region, the voltage drop in the drift region can be reduced, and even when the MOS transistor structure is in the on state, The PN junction can be turned on with a lower forward voltage. In addition, since the diode current rises with a lower forward voltage, the current driving capability is improved as compared with the conventional structure.

  Further, in the configuration in which the emitter region is not provided in the base region facing the drain region, there is no emitter region for supplying carriers to the channel even when the MOS transistor structure is on. Therefore, the voltage drop in the drift region up to the PN junction of the built-in diode can be reduced, and the PN junction is turned on with a lower forward voltage even when the MOS transistor structure is on. be able to. As a result, the current drive capability of the built-in diode is improved as compared with the conventional structure.

The top view which shows the semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the semiconductor device in the 1st Embodiment of this invention The figure which shows the current-voltage characteristic of the built-in diode of the semiconductor device in the 1st Embodiment of this invention The top view which shows the modification of the semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the modification of the semiconductor device in the 1st Embodiment of this invention The top view which shows the semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the semiconductor device in the 2nd Embodiment of this invention The top view which shows the semiconductor device in the 3rd Embodiment of this invention Sectional drawing which shows the semiconductor device in the 3rd Embodiment of this invention Sectional drawing which shows the semiconductor device in the 3rd Embodiment of this invention The top view which shows the semiconductor device in the 4th Embodiment of this invention Sectional drawing which shows the semiconductor device in the 4th Embodiment of this invention Sectional drawing which shows the semiconductor device in the 4th Embodiment of this invention The figure which shows the equivalent circuit of the built-in diode of the semiconductor device in the 4th Embodiment of this invention Circuit diagram showing an example of output part of display driving IC circuit The figure for demonstrating the subject of the equivalent circuit of the built-in diode of a semiconductor device

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied by a hybrid transistor in which an IGBT, a diode, and a MOS transistor are formed in the same element formation region. Note that in this specification, the high impurity concentration means an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more, preferably 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less. The concentration refers to a range in which the impurity concentration is greater than 5 × 10 ¹⁶ cm ^{−3 and} smaller than 1 × 10 ¹⁹ cm ⁻³ , preferably 1 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ . The low impurity concentration means an impurity concentration of 5 × 10 ¹⁶ cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or more and 3 × 10 ¹⁶ cm ⁻³ or less.

(First embodiment)
FIG. 1 is a plan view showing a hybrid transistor which is a semiconductor device according to a first embodiment of the present invention. 2 is a cross-sectional view taken along the line AA in FIG. As shown in FIG. 2, the semiconductor device according to the present embodiment is a single crystal having a thickness of 3.5 μm and low impurity on a support substrate 5 made of silicon single crystal or the like via a buried insulating film 6 such as silicon oxide. A P-type semiconductor layer 22 having a high concentration specific resistance is bonded to form an SOI substrate. The trench isolation 8 (insulation isolation) reaches the buried insulating film 6 from the surface of the semiconductor layer 22 and surrounds a region of the semiconductor layer 22 where a hybrid transistor is to be formed, as shown in FIG. The trench isolation 8 is formed by embedding an oxide film in a groove formed in the semiconductor layer 22.

  As shown in FIG. 2, a P-type base region 9 having a medium impurity concentration is provided on a part of the surface portion of the semiconductor layer 22, and an N-type emitter region 10 having a high impurity concentration is provided on the surface portion of the P-type base region 9. . A low impurity concentration N-type drift region 23 having a diffusion depth of about 2 μm is diffused adjacent to the P-type base region 9 on the surface of the semiconductor layer 22. In the N-type drift region 23, a high impurity concentration P-type collector region 11 is provided, and although not shown in the cross-sectional view shown in FIG. A drain region 14 is disposed (see FIG. 1). Further, on the surface of the semiconductor layer 22, the gate insulating film 12 such as a silicon oxide film is interposed from the end of the N-type emitter region 10 to a part on the P-type base region 9 and the N-type drift region 23. A gate electrode 13 made of polycrystalline silicon to which high concentration phosphorus is added is formed.

  The surface of the semiconductor layer 22 includes the gate electrode 13 and is covered with a first insulating film 17 such as a silicon oxide film, and the surface of the N-type emitter region 10 and the P-type base region 9 through each contact hole provided in the first insulating film 17. Are formed, and a first electrode 15 and a second electrode 16 are formed. The P-type collector region 11 and the N-type drain region 14 are connected in common. Further, a second insulating film 18 is formed on the first insulating film 17 as a protective film.

  Although the hybrid transistor of the present embodiment has the cross-sectional structure as described above, the planar pattern is as shown in FIG. 1 because it is mainly used for high-voltage driving. That is, as shown in FIG. 1, the trench isolation 8 arranged in a square shape surrounds the P-type semiconductor layer 22, and the inside of the square partitioned by the trench isolation 8 is the formation region of the hybrid transistor. Yes. The P-type base region 9 and the gate electrode 13 have an oval ring shape, which surrounds the oval N-type drift region 23. Further, the P-type collector region 11 and the N-type drain region 14 are alternately arranged along the longitudinal direction of the N-type drift region 23 at the center of the N-type drift region 23, and although not shown in FIG. The two electrodes 16 are electrically connected in common. The N-type emitter region 10 is disposed in the P-type base region 9 facing the linear array region in which the P-type collector region 11 and the N-type drain region 14 are alternately disposed. That is, the linear array region in which the P-type collector regions 11 and the N-type drain regions 14 are alternately arranged is sandwiched between two linear N-type emitter regions 10 disposed in the P-type base region 9. It is.

  In the hybrid transistor of the present embodiment having the above structure, the N-type emitter region 10, the P-type base region 9, the gate insulating film 12, the gate electrode 13, the N-type drift region 23, and the P-type collector region 11 are IGBTs. It is composed. The N-type emitter region 10, the P-type base region 9, the gate insulating film 12, the gate electrode 13, the N-type drift region 23, and the N-type drain region 14 constitute a MOS type transistor. Further, the P-type base region 9, the N-type drift region 23, and the N-type drain region 14 form a built-in diode.

  In the hybrid transistor of this embodiment, the operating current of the IGBT is mainly the base region 9 portion and the drift region 23 portion sandwiched between the N-type emitter region 10 facing the P-type collector region 11 in the plan view of FIG. Flowing. The operating current of the built-in diode mainly flows through a region sandwiched between the N-type drain region 14 and the P-type base region 9 facing the N-type drain region 14.

  Next, the diode forward current-voltage characteristics when the IGBT is in the on state in the hybrid transistor of the present embodiment will be described. The ON state means a state in which the voltage applied to the gate electrode 13 is controlled and a channel is formed on the surface of the base region 9 immediately below the gate electrode 13. FIG. 3 is a diagram showing simulation results of forward current-voltage characteristics of the built-in diode of the hybrid transistor of this embodiment and the built-in diode of the conventional hybrid transistor. Here, the conventional hybrid transistor has a structure in which an N-type semiconductor layer surrounded by isolation is used as it is as a drift region. Also, the horizontal axis of FIG. 3 shows the voltage applied to the second electrode 16 when the first electrode 15 including the emitter region 10 is set to the reference potential (0 V), and the emitter electrode including the emitter region is set to the reference potential (0 V). Corresponds to the voltage applied to the collector electrode. The vertical axis in FIG. 3 corresponds to the forward current.

  As shown in FIG. 3, the forward current of the built-in diode having a conventional structure increases linearly in proportion to the voltage applied to the collector electrode from 0 V to a negative voltage. As described above, since the channel on the surface of the base region directly under the gate electrode is in an on state, in such a region where the applied voltage is relatively small, current is dominant through the channel. It is considered that almost no current flows through the PN junction diode portion composed of the base region and the drift region (N-type semiconductor layer) (see FIG. 16). When the voltage applied to the collector electrode becomes about -4V, the forward current increases rapidly. It is considered that at this time, the main current of the forward current is switched to the current flowing through the PN junction diode portion. That is, as the voltage applied to the collector electrode increases, the potential difference between the PN junction ends of the base region and the drift region (N-type semiconductor layer) exceeds the built-in potential of the PN junction, and the PN junction is turned on in the forward direction. Thus, it is thought that the current increases rapidly due to the addition of current due to minority carriers of electrons and holes.

  On the other hand, in the hybrid transistor of this embodiment, when the applied voltage to the second electrode 16 is in the range of 0V to −1V, the current is smaller than that of the conventional structure. However, when the voltage applied to the second electrode 16 is on the negative voltage side from -1 V, the current is increased as compared with the diode having the conventional structure. That is, the current driving capability is improved. In particular, when the applied voltage to the second electrode 16 is about −0.7 V, the slope of current increase changes. This is because the channel is on in the region up to -0.7V, so the current through the channel is the main, but the current through the built-in diode is mainly on the negative potential side from -0.7V. It is believed that there is.

  Next, a description will be given of the factors that have been able to switch to the current via the PN junction of the built-in diode with the applied voltage smaller than that of the conventional structure by adopting the structure of the present embodiment. As shown in FIG. 2, the hybrid transistor of this embodiment has a structure in which a P-type semiconductor layer 22 exists below the P-type collector region 11 or the N-type drain region 14 via an N-type drift region 23. . In this structure, the PN junction that functions as a built-in diode is composed of a P-type semiconductor layer 22 and an N-type drift region 23. Since the PN junction is located at a relatively close distance from the P-type collector region 11 or the N-type drain region 14, the thickness of the high-resistance drift region 23 (acting as a parasitic resistance) existing until the PN junction is thin. . Therefore, when a voltage is applied to the second electrode 16, the voltage is applied to the PN junction with almost no voltage drop. For this reason, the built-in diode can be easily turned on in the forward direction.

  On the other hand, in the conventional structure, the PN junction that functions as a built-in diode is composed of an N-type semiconductor layer and a P-type base region. Therefore, the distance from the collector region or the drain region to the PN junction is a lateral distance to the base region. However, the distance in the lateral direction is usually set large in order to increase the breakdown voltage of the IGBT element. Therefore, the resistance during this period increases, and acts as a large parasitic resistance 120 as shown in FIG.

  As described above, in the structure of the present embodiment, the voltage at which the forward current switches from the current flowing through the channel to the current flowing through the built-in diode (PN junction) can be lowered, the parasitic resistance is small, and the current driving capability is high. A withstand voltage hybrid transistor can be realized.

  On the other hand, from the viewpoint of further reducing the parasitic resistance, the hybrid transistor shown in FIGS. 1 and 2 may have the following structure. FIG. 4 is a plan view showing a modification of the semiconductor device according to the present embodiment. FIG. 5 is a cross-sectional view taken along line BB in FIG. This hybrid transistor includes a P-type buried diffusion layer 24 in addition to the structure of the hybrid transistor shown in FIGS. As shown in FIG. 5, the P-type buried diffusion layer 24 includes the N-type drift region 23 and the P-type base region 9, and the buried insulating film 6 except at least the portion of the P-type semiconductor layer 22 immediately below the P-type collector region 11. Between. Further, the impurity concentration of the P-type buried diffusion layer 24 is set higher than the impurity concentration of the P-type semiconductor layer 22. Therefore, the parasitic resistance of the semiconductor layer 22 near the collector region 11 and the drain region 14 among the parasitic resistances of the built-in diode can be further reduced. Therefore, the forward current drive capability of the built-in diode can be further improved by the P-type buried diffusion layer 24.

  In this hybrid transistor, the P-type buried diffusion layer 24 is not formed immediately below the P-type collector region 11. This is because a positive voltage is applied to the second electrode 16 (collector region 11 and drain region 14), and the first electrode 15 (emitter region 10 and base region 9) and the gate electrode 13 are grounded (that is, the drift region). 23, the P-type buried diffusion layer 24 does not exist immediately below the collector region 11 and is a P-type low impurity concentration region (impurity layer 22). In the portion, the extension of the depletion layer of the PN junction becomes larger than that in other portions, and conversely, the extension of the depletion layer in the drift region 23 can be suppressed. As a result, in the PN junction between the P-type buried diffusion layer 24 and the N-type drift region 23, the collector region 11 and the emitter region generated due to the depletion layer extending toward the drift region 23 reaching the collector region 11 The breakdown of current due to punch through between 10 and 10 can be suppressed, and the breakdown voltage can be improved. Of course, the P-type buried diffusion layer 24 may be formed immediately below the collector region 11 if the breakdown voltage is acceptable.

(Second Embodiment)
In the first embodiment, the configuration in which the N-type drift region is provided in the P-type semiconductor layer has been described. However, the technical idea according to the present invention is that an N-type semiconductor layer is formed on an SOI substrate configured with an N-type semiconductor layer. It can also be applied when used as an N-type drift region.

  FIG. 6 is a plan view showing a hybrid transistor which is a semiconductor device according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line CC of FIG. In FIGS. 6 and 7, the same reference numerals are given to the portions having the same operational effects as the semiconductor device of the first embodiment.

  As shown in FIG. 7, the semiconductor device according to the present embodiment is a single crystal having a thickness of 3.5 μm and low impurity on a support substrate 5 made of silicon single crystal or the like via a buried insulating film 6 such as silicon oxide. An N-type semiconductor layer 7 having a high concentration specific resistance is bonded to form an SOI substrate. Similar to the first embodiment, the trench isolation 8 reaches the buried insulating film 6 from the surface of the semiconductor layer 7 and surrounds the region of the semiconductor layer 7 where the hybrid transistor is to be formed, as shown in FIG.

  A P-type base region 9 having a medium impurity concentration is provided on a part of the surface portion of the semiconductor layer 7, and an N-type emitter region 10 having a high impurity concentration is provided on the surface portion. The high impurity concentration P-type collector region 11 is provided directly in the N-type semiconductor layer 7 and is not shown in the cross-sectional view of FIG. Region 14 is arranged (see FIG. 6). Further, on the surface of the N-type semiconductor layer 7, a gate insulating film 12 such as a silicon oxide film extends from the end of the N-type emitter region 10 to the P-type base region 9 and a part on the N-type semiconductor layer 7. A gate electrode 13 is formed through the.

  In the semiconductor device of this embodiment, P extended from the P-type base region 9 to the surface of the N-type semiconductor layer 7 extending from the end of the gate electrode 13 to the P-type collector region 11 (or the N-type drain region 14). It is characterized by including a mold base extension region 25.

  As shown in FIG. 6, the P-type base extension region 25 has an elliptical ring shape surrounding a linear array region in which the collector regions 11 and the drain regions 14 are alternately arranged in a plan view. The P-type base extension region 25 is surrounded by the base region 9 having an oval ring shape. Furthermore, the P-type base extension region 25 protrudes from the P-type base region 9 and is electrically connected by a plurality of narrow P-type impurity layers 25 a that cross the N-type semiconductor layer 7 below the gate electrode 13. . The trench isolation 8, the emitter region 10, and the gate electrode 13 have the same planar shape as that of the semiconductor device of the first embodiment. In addition, the first electrode 15, the P-type collector region 11, and the N-type emitter region 10 and the surface of the P-type base region 9 are commonly connected through a contact hole provided in the first insulating film 17 covering the semiconductor layer 7. A second electrode 16 is provided in common with the surface of the N-type drain region 14.

  As can be understood from FIG. 7, the built-in diode in the hybrid transistor of the present embodiment is configured by a PN junction of the P-type base region 9 and the P-type base extension region 25 and the N-type semiconductor layer 7. In particular, the PN junction formed by the P-type base extension region 25 and the N-type semiconductor layer 7 is close to the P-type collector region 11 and the N-type drain region 14. That is, the lateral length of the high-resistance N-type semiconductor layer 7 between the P-type base extension region 25 and the P-type collector region 11 and the drain region 14 is small. Therefore, when the built-in diode performs forward operation, the parasitic resistance is reduced, and the forward current drive capability of the built-in diode can be improved.

  This embodiment is particularly useful when the thickness of the semiconductor layer constituting the SOI substrate is thick. When the film thickness of the semiconductor layer constituting the SOI substrate is thick, for example, in order to form a buried layer (P-type buried diffusion layer 24) as shown in FIG. 5, ion implantation by MeV order acceleration energy or epitaxial growth is performed. It is necessary to use this, and the manufacturing flow of the semiconductor device becomes complicated. However, as shown in FIG. 7, in the configuration in which the P-type base extension region 25 is formed on the surface side of the N-type semiconductor layer 7, it is not necessary to increase the acceleration energy at the time of ion implantation to the order of MeV. It has the advantage of simplifying the flow.

  In the above description, a configuration in which the P-type base extension region 25 is provided in the semiconductor layer 22 between the gate electrode 13 and the collector region 11 and the semiconductor layer 22 between the gate electrode 13 and the drain region 14 will be described. However, the same effect can be obtained if the P-type base extension region 25 is provided at least in the semiconductor layer 22 between the gate electrode 13 and the drain region 14.

(Third embodiment)
In the first and second embodiments, the configuration in which the P-type impurity region and the N-type impurity region are stacked in the depth direction has been described. However, the technical idea according to the present invention is that the P-type impurity region and the N-type impurity region are stacked. It can also be embodied by a configuration in which the impurity regions are arranged in the horizontal direction.

  FIG. 8 is a plan view showing a hybrid transistor which is a semiconductor device according to the third embodiment of the present invention. 9 is a cross-sectional view taken along the line DD in FIG. 8, and FIG. 10 is a cross-sectional view taken along the line EE in FIG. In FIGS. 8 to 10, the same reference numerals are given to the portions that exhibit the same operational effects as the semiconductor device of the first embodiment.

  As shown in FIGS. 9 and 10, the semiconductor device of this embodiment is a single crystal having a film thickness of 3.5 μm on a support substrate 5 made of silicon single crystal or the like via a buried insulating film 6 made of silicon oxide or the like. Then, a P-type semiconductor layer 22 having a low impurity concentration and a high specific resistance is bonded to form an SOI substrate. The trench isolation 8 reaches the buried insulating film 6 from the surface of the semiconductor layer 22 and surrounds the region of the semiconductor layer 22 where the hybrid transistor is to be formed.

  A P-type base region 9 having a medium impurity concentration is provided on a part of the surface portion of the semiconductor layer 22, and an N-type emitter region 10 having a high impurity concentration is further provided on the surface portion. As shown in FIG. 8, the P-type base region 9 has an oval ring shape in plan view, and a high impurity concentration P-type collector region 11 and a high impurity concentration N-type drain region 14 are alternately arranged. Encloses a linear array region. The trench isolation 8, the emitter region 10, and the gate electrode 13 have the same planar shape as that of the semiconductor device of the first embodiment. In addition, the first electrode 15, the P-type collector region 11, and the N-type emitter region 10 and the surface of the P-type base region 9 are commonly connected through a contact hole provided in the first insulating film 17 covering the semiconductor layer 22. A second electrode 16 is provided in common with the surface of the N-type drain region 14.

  As shown in FIG. 9, in the cross section taken along the line DD in FIG. 8, the diffusion depth is about 3.5 μm adjacent to the P-type base region 9 on the surface of the semiconductor layer 22, and the impurity concentration is almost the same as the P-type base region 9. And a P-type base extension region 25 having an impurity concentration higher than that of the semiconductor layer 22 is provided. In the present embodiment, the P-type base extension region 25 is also in contact with the buried insulating film 6. An N-type drain region 14 is provided on the surface portion in the P-type base extension region 25. The gate electrode 13 is formed on the surface of the semiconductor layer 22 from the end of the N-type emitter region 10 to a part on the P-type base region 9 and the P-type base extension region 25 via the gate insulating film 12. Is provided. In the DD line cross-sectional portion, the N-type drain region 14, the PN junction between the N-type drain region 14 and the P-type base extension region 25, the base extension region 25, and the base region 9 constitute a built-in diode.

  On the other hand, as shown in FIG. 10, in the cross section taken along the line E-E in FIG. 8, the diffusion depth is about 3.5 μm adjacent to the P-type base region 9 on the surface of the semiconductor layer 22 and lower than the P-type base extension region 25. An N-type drift region 23 having an impurity concentration and substantially the same impurity concentration level as that of the P-type semiconductor layer 22 is provided. In the present embodiment, the drift region 23 is also in contact with the buried insulating film 6. A P-type collector region 11 is provided on a surface portion in the N-type drift region 23. The gate electrode 13 is provided on the surface of the semiconductor layer 22 via the gate insulating film 12 from the end of the N-type emitter region 10 to part of the P-type base region 9 and the drift region 23. In the section taken along the line EE, the N-type emitter region 10, the P-type base region 9, the gate insulating film 12, the gate electrode 13, the N-type drift region 23, and the P-type collector region 11 constitute an IGBT.

  As described above, the hybrid transistor according to the present embodiment has a cross section as shown in FIG. 9 or 10 depending on the position in the longitudinal direction of the linear array region in which the P-type collector regions 11 and the N-type drain regions 14 are alternately arranged. It has a structure. As shown in FIG. 8, the P-type base extension region 25 is provided so as to extend from both sides of the N-type drain region 14 to the end of the P-type base region 9 so as to be perpendicular to the longitudinal direction of the array region. 23 is provided so as to extend from both sides of the P-type collector region 11 to the end of the P-type base region 9 in a direction perpendicular to the longitudinal direction of the array region. That is, the P-type base extension regions 25 and the N-type drift regions 23 are alternately arranged along the longitudinal direction of the arrangement region. Further, the longitudinal width of the base extension region 25 is made smaller than the longitudinal width of the N-type drain region 14, and the longitudinal width of the N-type drift region 23 is made wider than the longitudinal width of the P-type collector region 11. An arrangement is employed in which the base extension region 25 and the P-type collector region 11 are not in direct contact.

  As described above, the built-in diode in the hybrid transistor of the present embodiment is formed in a region different from the IGBT. As is apparent from FIG. 9, the body of the built-in diode has a medium impurity concentration and a relatively low resistance P-type base region 9 and P-type base extension region 25, and a high impurity concentration and a low resistance N-type. The drain region 23 is composed only of a PN junction. That is, unlike the conventional structure, no current flows through the drift region (semiconductor layer) having a low impurity concentration and a high resistance, and the forward current drive capability of the built-in diode can be improved.

  This embodiment is particularly useful when the film thickness of the semiconductor layer constituting the SOI substrate is thin. When the semiconductor layer constituting the SOI substrate is thin, for example, it becomes difficult to form a stacked structure of an N-type impurity layer and a P-type impurity layer in the depth direction of the semiconductor layer as shown in FIG. . In the present embodiment, since the N-type drift regions 23 and the P-type base extension regions 25 are alternately arranged in the lateral direction of the N-type semiconductor layer, it can be easily manufactured even when the semiconductor layer is thin. can do.

(Fourth embodiment)
FIG. 11 is a plan view showing a hybrid transistor which is a semiconductor device according to the fourth embodiment of the present invention. 12 is a cross-sectional view taken along line FF in FIG. 11, and FIG. 13 is a cross-sectional view taken along line GG in FIG. In FIGS. 11 to 13, the same reference numerals are given to the portions having the same operational effects as the semiconductor device of the first embodiment.

  As shown in FIGS. 12 and 13, the semiconductor device of this embodiment is a single crystal having a film thickness of 3.5 μm on a support substrate 5 made of silicon single crystal or the like via a buried insulating film 6 made of silicon oxide or the like. Thus, an N-type semiconductor layer 7 having a low impurity concentration and a high specific resistance is bonded to form an SOI substrate. The trench isolation 8 reaches the buried insulating film 6 from the surface of the semiconductor layer 7 and surrounds the region of the semiconductor layer 7 where the hybrid transistor is to be formed.

  A P-type base region 9 having a medium impurity concentration is provided in a part of the surface portion of the semiconductor layer 7. As shown in FIG. 11, the P-type base region 9 has an oval ring shape in plan view, and a high impurity concentration P-type collector region 11 and a high impurity concentration N-type drain region 14 are alternately arranged. Encloses a linear array region. The trench isolation 8 and the gate electrode 13 have the same planar shape as that of the semiconductor device of the first embodiment.

  In the semiconductor device of this embodiment, as shown in FIGS. 12 and 13, a high impurity concentration N-type emitter region 10 is provided in the P-type base region 9 in the cross-section of the FF line, and the GG line is provided. In the cross section, the N-type emitter region 10 is not provided inside the P-type base region 9.

  That is, as shown in FIG. 11, the N-type emitter region 10 is disposed in the P-type base region 9 facing the linear array region in which the P-type collector region 11 and the N-type drain region 14 are alternately disposed. The The emitter region 10 sandwiching the linear array region in which the P-type collector region 11 and the N-type drain region 14 are alternately arranged is divided into a plurality of adjacent emitter regions along the longitudinal direction of the linear array region. 10, only the P-type base region 9 exists. Further, the P-type base region 9 positioned between the N-type emitter regions 10 faces the drain region 14 at the shortest distance. Similar to the first embodiment, the N-type emitter region 10 and the surface of the P-type base region 9 are commonly connected through a contact hole provided in the first insulating film 17 covering the semiconductor layer 7. A second electrode 16 is provided in which the electrode 15, the P-type collector region 11 and the surface of the N-type drain region 14 are connected in common.

  As described above, in the hybrid transistor of the present embodiment, the portion where the emitter region 10 shown in FIG. 12 is formed and the portion where the emitter region 10 shown in FIG. 13 is not formed include at least the semiconductor layer 7 and the base region 9. They are shared and arranged alternately next to each other. In this hybrid transistor, a built-in diode is formed by a PN junction between the P-type base region 9 and the semiconductor layer 7 as in the conventional structure.

  This built-in diode is in an ON state in which a positive voltage is applied to the gate electrode 13 of the hybrid transistor and a channel is generated on the surface of the base region 9 immediately below the built-in diode, and the P-type collector region 11 and the N-type drain region 14 When a negative potential is applied with reference to the N-type emitter region 10 and the P-type base region 9, the forward bias is applied. As can be understood from FIG. 12, the structure of the FF line cross-sectional portion is the same as the conventional structure. Therefore, under the bias condition, the current mainly flows from the emitter region 10 to the surface of the base region 9 through the channel of the semiconductor layer 7. Passes near the surface of the drain region 14 and flows into the drain region 14. Therefore, the equivalent circuit of the cross-section portion of the FF line is the same as the circuit diagram shown in FIG. 16, and is due to the drift resistance (corresponding to the parasitic resistance 120 in FIG. 16) caused by the N-type low impurity concentration semiconductor layer 7. In addition, a large voltage drop occurs between the PN junction constituted by the base region 9 and the semiconductor layer 7 and the drain region 14. For this reason, since the potential difference between both ends of the PN junction is reduced, the current driving capability of the built-in diode at the cross-sectional portion of the FF line remains low.

  On the other hand, since the N-type emitter region 10 does not exist in the GG cross section shown in FIG. 13, even if a channel is formed on the surface of the base region 9, there is no N-type emitter region that supplies carriers to the channel. Therefore, current does not flow near the surface of the semiconductor layer 7. In this portion, current flows from the base region 9 into the drain region 14 via a deep and wide portion of the semiconductor layer 7 existing between the base region 9 and the drain region 14. The equivalent circuit relating to the forward characteristic of the GG line section is the circuit diagram shown in FIG. 14, that is, a circuit in which a parasitic resistor 20 corresponding to a wide deep portion of the semiconductor layer 7 is connected in series to the built-in diode 21. Can be considered. Since the cross-sectional area of the semiconductor layer 7 region through which the current flows is considerably larger than the cross-sectional area of the semiconductor layer 7 region through which the current flows at the FF line cross-section, the size of the parasitic resistance 20 is at the FF line cross-section. It becomes smaller than the magnitude of the parasitic resistance caused by the semiconductor layer 7. Therefore, the voltage drop between the PN junction of the built-in diode 21 and the drain region 14 is also reduced, and the voltage applied to the second electrode 16 is applied to the PN junction with almost no voltage drop. As a result, the current drive capability of the built-in diode 21 can be improved in the cross-section portion along the line GG.

  As shown in FIG. 11, the FF line cross-sectional portion and the GG line cross-sectional portion are adjacent to each other in plan view, and the semiconductor layer 7 is common. Is transmitted to the semiconductor layer 7 in the cross-sectional portion of the adjacent GG line, and acts in such a direction that the voltage applied to the PN junction of the built-in diode in the cross-sectional portion of the GG line is reduced. However, a current flows in the horizontal direction from the vicinity of the PN junction at the GG line cross section to the vicinity of the FN junction at the FF line cross section, whereby the voltage difference applied to the PN junction at both cross sections is maintained. Further, as described above, in this embodiment, since the base region 9 between the adjacent emitter regions 10 is disposed in a state of facing the drain region 14 at the shortest distance, a semiconductor layer that becomes a drift region in this portion. 7 can be minimized, and the parasitic resistance 20 can be minimized.

  As described above, according to the present invention, even when the MOS transistor structure is in the ON state, the current capability of the built-in diode can be improved compared to the conventional structure. That is, in the present invention, since the PN junction of the built-in diode can be arranged in the drain region, the voltage drop in the drift region can be reduced, and the PN junction can be obtained even when the MOS transistor structure is in the ON state. Can be turned on with a lower forward voltage. In addition, since the diode current rises with a lower forward voltage, the current driving capability is improved as compared with the conventional structure.

  Further, in the configuration in which the emitter region is not provided in the base region facing the drain region, there is no emitter region for supplying carriers to the channel even when the MOS transistor structure is on. Therefore, the voltage drop in the drift region up to the PN junction of the built-in diode can be reduced, and the PN junction is turned on with a lower forward voltage even when the MOS transistor structure is on. be able to. As a result, the current drive capability of the built-in diode is improved as compared with the conventional structure.

  The embodiments described above do not limit the technical scope of the present invention, and various modifications and applications can be made within the scope of the technical idea of the present invention other than those already described. For example, in each of the above embodiments, a hybrid transistor including an N-channel MOS type structure has been described. However, by inverting the conductivity type of each diffusion layer such as an emitter region, a base region, a base extension region, a drift region, and a drain region. The forward current drive capability of the built-in diode can be improved also for the hybrid transistor including the P-channel MOS type structure. In addition, the present invention realizes downsizing and cost reduction of a plasma display device including the above-described semiconductor device as an output unit of a driving IC circuit because the driving IC circuit can be downsized. Can do.

  According to the present invention, it is possible to realize a semiconductor device such as a high voltage hybrid transistor having a small parasitic resistance and a large current driving capability, which is useful as a semiconductor device and a plasma display device.

5 Support substrate 6 Embedded insulating film 7 N-type semiconductor layer 8 Trench isolation 9 P-type base region 10 High-concentration N-type emitter region 11 High-concentration P-type collector region 12 Gate insulating film 13 Gate electrode 14 High-concentration N-type drain region 15 1 electrode 16 2nd electrode 17 1st insulating film 18 2nd insulating film 20 Parasitic resistance 21 Built-in diode 22 P-type semiconductor layer 23 N-type drift region 24 P-type buried diffusion layer 25 P-type base extension region

Claims (10)

A first conductivity type semiconductor layer;
A base region of a first conductivity type provided in the semiconductor layer;
An emitter region of a second conductivity type provided in the base region;
A second conductivity type impurity layer provided on the semiconductor layer adjacent to the base region over a predetermined depth smaller than the thickness of the semiconductor layer from the surface;
A first conductivity type collector region and a second conductivity type drain region provided in the impurity layer apart from the base region;
A gate electrode provided on a surface of the semiconductor layer through a gate insulating film over an end portion of the emitter region, a portion of the base region, and a portion of the impurity layer;
A first electrode electrically connected in common to the emitter region and the base region;
A second electrode electrically connected in common to the collector region and the drain region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising a first conductivity type buried impurity layer having an impurity concentration higher than that of the semiconductor layer in the semiconductor layer below the second conductivity type impurity layer.   The semiconductor device according to claim 2, wherein the buried impurity layer is disposed in a region excluding the semiconductor layer immediately below the collector region. A second conductivity type semiconductor layer;
A base region of a first conductivity type provided in the semiconductor layer;
An emitter region of a second conductivity type provided in the base region;
A first conductivity type collector region and a second conductivity type drain region provided in the semiconductor layer apart from the base region;
A gate insulating film is provided on the surface of the semiconductor layer over the end of the emitter region, over the base region, and over a portion of the semiconductor layer between the base region and the collector region. A gate electrode;
A first electrode electrically connected in common to the emitter region and the base region;
A second electrode electrically connected in common to the collector region and the drain region;
The semiconductor layer is electrically connected to a part of the base region, and is provided in the semiconductor layer at least between the drain region and the gate electrode through a part of the semiconductor layer below the gate electrode from the base region. An extended impurity region of the first conductivity type;
A semiconductor device comprising:   The semiconductor device according to claim 4, wherein the extended impurity region is also provided in the semiconductor layer between the gate electrode and the collector region. A semiconductor layer;
A base region of a first conductivity type provided in the semiconductor layer;
An emitter region of a second conductivity type provided in the base region;
A second conductivity type impurity layer provided in the semiconductor layer adjacent to the base region;
A first conductivity type collector region provided in the second conductivity type impurity layer apart from the base region;
A gate electrode provided on an end of the emitter region, on the base region and on a part of the impurity layer of the second conductivity type over the surface of the semiconductor layer via a gate insulating film. 1 part and
The semiconductor layer;
A base region of the first conductivity type;
An emitter region of the second conductivity type;
A first conductivity type impurity layer provided in the semiconductor layer adjacent to the base region;
A second conductivity type drain region provided in the first conductivity type impurity layer apart from the base region;
The gate electrode provided on the surface of the semiconductor layer over a portion of the emitter region, on the base region, and on the impurity layer of the first conductivity type via a gate insulating film;
A second part comprising:
A first electrode electrically connected in common to the emitter region and the base region;
A second electrode electrically connected in common to the collector region and the drain region;
With
The first portion and the second portion are adjacent to each other and arranged along a direction different from the direction from the base region to the collector region or from the base region to the drain region. Semiconductor device. A second conductivity type semiconductor layer;
A base region of a first conductivity type provided in the semiconductor layer;
An emitter region of a second conductivity type provided in the base region;
A collector region of a first conductivity type provided in the semiconductor layer apart from the base region;
A gate insulating film is provided on the surface of the semiconductor layer over the end of the emitter region, over the base region, and over a portion of the semiconductor layer between the base region and the collector region. A gate electrode;
A first portion comprising:
A semiconductor layer of the second conductivity type;
A base region of the first conductivity type;
A drain region of a second conductivity type provided in the semiconductor layer apart from the base region;
The gate electrode provided on the surface of the semiconductor layer via a gate insulating film over the base region and a part on the semiconductor layer between the base region and the drain region;
A second part comprising:
A first electrode electrically connected in common to the emitter region and the base region;
A second electrode electrically connected in common to the collector region and the drain region;
With
The first portion and the second portion are adjacent to each other and arranged along a direction different from the direction from the base region to the collector region or from the base region to the drain region. Semiconductor device.   The semiconductor device according to claim 1, wherein the semiconductor layer is provided on an insulating film provided on one main surface of the support substrate.   9. The semiconductor device according to claim 8, wherein the semiconductor device has insulation isolation formed so as to surround the base region and the impurity layer in a plane and to reach the insulating film on the support substrate from a surface of the semiconductor layer.   A plasma display device comprising the semiconductor device according to claim 1.

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