JP2011066058A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress penetration of impurity to a gate electrode. <P>SOLUTION: In a method of manufacturing a semiconductor device, polycrystalline silicon formed on a substrate is etched to form a first gate electrode 25A on a first region of the substrate, and a second gate electrode 25A is formed on a second region of the substrate. A first pattern covering the first region and the first gate electrode is formed, first impurity is implanted into the second region with a first dose and a first extension region is formed in the second region with the second gate electrode and the first pattern as masks. A second pattern where upper faces of the first gate electrode, the first region and the second gate electrode are exposed is formed. The first extension region is covered, second impurity is implanted into the first region with a dose larger than the first dose and a second extension region is formed with the first gate electrode, the second gate electrode and the second pattern as the masks. At least an upper part of the first gate electrode or the second gate electrode is made into amorphous. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  1 to 5 are manufacturing process diagrams of a conventional semiconductor device. 1A and 1B show the manufacturing of a semiconductor device when a gate insulating film 2 is formed on a semiconductor substrate 1 and a gate electrode 3A and a gate electrode 3B are formed on the gate insulating film 2. FIG. It is process drawing. The material of the gate electrode 3A and the gate electrode 3B is polysilicon. In FIG. 1A, a gate electrode 3A is formed in a region (hereinafter referred to as “internal Tr region”) in the semiconductor substrate 1 where an internal transistor is formed. In FIG. 1B, a gate electrode 3B is formed in a region where an input / output (I / O) transistor is formed in the semiconductor substrate 1 (hereinafter referred to as “input / output Tr region”). In FIGS. 1A and 1B, an element isolation region 4 is formed.

  After forming the gate electrode 3A and the gate electrode 3B, as shown in FIGS. 2A and 2B, a resist pattern 5 is formed so as to cover the internal Tr region. By performing ion implantation at a low dose using the resist pattern 5 as a mask, a pocket region 6 and an extension region 7 are formed in the input / output Tr region as shown in FIG. Since the pocket region 6 and the extension region 7 are formed in the input / output Tr region by ion implantation at a low dose, the polysilicon of the gate electrode 3B in the input / output Tr region is not amorphous but is in a microcrystalline state. . Next, the resist pattern 5 is removed, and thin sidewalls (SW) 8 are formed on the side surfaces of the gate electrode 3A and the gate electrode 3B.

  Next, as shown in FIGS. 3A and 3B, a resist pattern 9 is formed so as to cover the input / output Tr region. By performing ion implantation at a high dose using the resist pattern 9 as a mask, a pocket region 10 and an extension region 11 are formed in the internal Tr region as shown in FIG. Since the pocket region 10 and the extension region 11 are formed in the internal Tr region by ion implantation at a high dose, as shown in FIG. 3A, the polysilicon layer is formed on the polysilicon of the gate electrode 3A in the internal Tr region. An amorphous layer 12 is formed.

  Then, as shown in FIGS. 4A and 4B, sidewall films 13 are formed on the sides of the gate electrode 3A and the gate electrode 3B. The material of the sidewall film 13 is a nitride film, and the deposition temperature of the nitride film is about 545 ° C. When the material of the sidewall 13 film is an oxide film, since the film formation temperature of the oxide film is about 515 ° C., the grain growth of polysilicon of the gate electrode 3A and the gate electrode 3B is small. In contrast, the nitride film deposition temperature is about 30 ° C. higher than the oxide film deposition temperature, the polysilicon grain size of the gate electrode 3A and the gate electrode 3B is increased, and the gate electrode 3A and the gate electrode 3B. The polysilicon becomes single crystal silicon 14.

As shown in FIGS. 5A and 5B, when the source / drain diffusion region 15 is formed in the internal Tr region and the input / output Tr region, ion implantation is performed on the internal Tr region and the input / output Tr region. . Since the amorphous layer 12 is formed on the upper part of the gate electrode 3A in the internal Tr region, it is difficult for impurities to penetrate into the gate electrode 3A. However, since the amorphous layer 12 is not formed on the gate electrode 3B in the input / output Tr region, channeling is likely to occur, and impurities penetrate through the gate electrode 3B. The penetration of impurities into the gate electrode 3B is not preferable because it causes a change in transistor characteristics.

JP 2009-10417 A

  The purpose of this case is to suppress the penetration of impurities into the gate electrode.

  According to one aspect of the present invention, a method of manufacturing a semiconductor device forms a first gate electrode above a first region of a substrate by forming polycrystalline silicon over the substrate and etching the polycrystalline silicon. Forming a second gate electrode above the two regions, forming a first resist pattern covering the first region and the first gate electrode above the substrate, and using the second gate electrode and the first resist pattern as a mask By implanting a first impurity into the second region at a first dose, a step of forming a first extension region in the second region, a step of removing the first resist pattern, a step of covering the first extension region, Forming a second resist pattern exposing the upper surface of the first gate electrode, the first region, and the second gate electrode above the substrate; a first gate electrode; a second gate electrode; The second extension region is formed in the first region by implanting the second impurity into the first region with a second dose amount larger than the first dose amount using the two resist pattern as a mask, and the first gate electrode and And amorphizing at least the upper part of the second gate electrode.

  According to this case, it is possible to prevent impurities from penetrating the gate electrode.

FIG. 6 is a manufacturing process diagram (No. 1) for a conventional semiconductor device; FIG. 11 is a manufacturing process diagram (No. 2) for a conventional semiconductor device; FIG. 7 is a manufacturing process diagram (No. 3) for a conventional semiconductor device; FIG. 11 is a manufacturing process diagram (No. 4) for a conventional semiconductor device; FIG. 6 is a manufacturing process diagram (No. 5) for a conventional semiconductor device; FIG. 6 is a manufacturing process diagram (No. 1) of a semiconductor device according to the first embodiment; 6 is a manufacturing process diagram (No. 2) of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a manufacturing process diagram (No. 3) of the semiconductor device according to the first embodiment; FIG. 7 is a manufacturing process diagram (No. 4) of the semiconductor device according to the first embodiment; FIG. 6 is a manufacturing process diagram (No. 5) of the semiconductor device according to the first embodiment; FIG. 6A is a sixth manufacturing process diagram of the semiconductor device according to the first embodiment; It is a figure which shows the density | concentration profile of indium when changing the acceleration voltage and performing ion implantation. It is a figure which shows the density | concentration profile of arsenic (As) at the time of performing ion implantation by changing acceleration voltage. FIG. 7 is a manufacturing process diagram (No. 7) of the semiconductor device according to the first embodiment; FIG. 8 is a manufacturing process diagram (8) of the semiconductor device according to the first embodiment; FIG. 3 is a diagram showing a phosphorus (P) concentration profile immediately after ion implantation when forming a source / drain diffusion region 36 and a source / drain diffusion region 37 in a semiconductor substrate 21; FIG. 6 is a diagram showing a phosphorus (P) concentration profile immediately after ion implantation when forming a source / drain diffusion region in a semiconductor substrate 1 in the conventional example shown in FIG. 5. FIG. 6A is a manufacturing process diagram (No. 1) of a semiconductor device according to a second embodiment; FIG. 6 is a manufacturing process diagram (No. 2) of a semiconductor device according to the second embodiment; FIG. 11 is a manufacturing process diagram (No. 3) of a semiconductor device according to the second embodiment; FIG. 6D is a manufacturing process diagram (No. 4) of the semiconductor device according to the second embodiment.

  The semiconductor device and the manufacturing method thereof according to the present embodiment will be described below with reference to the drawings. The configurations of the following examples are illustrative, and the semiconductor device and the manufacturing method thereof according to the present embodiment are not limited to the configurations of the examples.

  A first example of the semiconductor device and the manufacturing method thereof according to this embodiment will be described. In the method of manufacturing a semiconductor device according to the first embodiment, an internal transistor and an input / output (I / O) transistor are formed on the same semiconductor substrate. The internal transistor is, for example, an n-type Metal Oxide Semiconductor field effect transistor (n-type MOSFET) that operates at a power supply voltage of 1.0V. The input / output (I / O) transistor is, for example, an n-type MOSFET that operates at a power supply voltage of 1.8 V or 3.3 V. Example 1 shows an example in which an n-type MOSFET is manufactured. However, the present invention is not limited to this, and the semiconductor device and the manufacturing method thereof according to the present embodiment may be applied when manufacturing a p-type MOSFET.

  FIG. 6 is a manufacturing process diagram of the semiconductor device in accordance with the first embodiment. In the method for manufacturing a semiconductor device according to the first embodiment, first, as shown in FIGS. 6A and 6B, a gate insulating film 22 is formed on a p-type semiconductor substrate 21, and the gate insulating film 22 is formed. A polysilicon (microcrystalline silicon) film 23 is formed thereon. The semiconductor substrate 21 is a silicon substrate, for example. An element isolation region 24 is formed in the semiconductor substrate 21. By forming a plurality of element isolation regions 24 in the semiconductor substrate 21, a region where an internal transistor is formed (hereinafter referred to as an “internal Tr region”) and an input / output (I / O) transistor are formed. Regions (hereinafter referred to as “input / output Tr regions”) are defined. The element isolation region 24 is formed using a method such as Shallow Trench Isolation (STI) or LOCOS method.

  The internal Tr region includes a region where a source / drain diffusion region, a pocket region, and an extension region (source / drain extension region) of the semiconductor substrate 21 are formed (hereinafter referred to as a “first semiconductor region”), and a first semiconductor region. And the region above. The input / output Tr region includes a region where a source / drain diffusion region, a pocket region, and an extension region (source / drain extension region) of the semiconductor substrate 21 are formed (hereinafter referred to as a “second semiconductor region”), and a second semiconductor. And a region above the region.

  The gate insulating film 22 is, for example, a gate oxide film. The gate insulating film 22 is formed using, for example, a thermal oxidation method. The film thickness of the gate insulating film 22 differs between the internal Tr region and the input / output Tr region. The film thickness of the gate insulating film 22 in the input / output Tr region is larger than the film thickness of the gate insulating film 22 in the internal Tr region. It is thick. This is because the gate insulating film 22 is formed on the entire surface of the semiconductor substrate 21, the gate insulating film 22 in the internal Tr region is removed by etching, and the gate insulating film 22 is formed again on the entire surface of the semiconductor substrate 21. The gate insulating film 22 has a different film thickness.

  The polysilicon film 23 is formed using, for example, a CVD method at a film formation temperature of 605 ° C. When the polysilicon film 23 is formed, an n-type impurity such as phosphorus (P) or arsenic (As) is added to the polysilicon film 23. Further, after the polysilicon film 23 is formed, n-type impurities such as phosphorus (P) and arsenic (As) may be ion-implanted into the polysilicon film 23.

Next, as shown in FIGS. 7A and 7B, the gate electrode 25A is formed in the internal Tr region, and the gate electrode 25B is formed in the input / output Tr region. In other words, the first of the semiconductor substrate 21
A gate electrode 25 A is formed above the semiconductor region, and a gate electrode 25 B is formed above the second semiconductor region of the semiconductor substrate 21. For example, after applying a resist film on the polysilicon film 23 by spin coating, the resist film is patterned by a photolithography technique to form a resist pattern on the polysilicon film 23. Then, by etching the polysilicon film 23 using the resist pattern as a mask, the gate electrode 25A is formed in the internal Tr region, and the gate electrode 25B is formed in the input / output Tr region.

  Next, as shown in FIGS. 8A and 8B, a resist pattern 26 is formed above the semiconductor substrate 21. Specifically, as shown in FIG. 8A, a resist pattern 26 is formed so as to cover the first semiconductor region of the semiconductor substrate 21 and the gate electrode 25A. Further, as shown in FIG. 8B, an opening is provided in the resist pattern 26 so that the second semiconductor region of the semiconductor substrate 21 and the gate electrode 25 </ b> B are exposed from the resist pattern 26. The resist pattern 26 is formed by, for example, applying a resist film on the gate insulating film 22 by a spin coating method and then patterning the resist film by a photolithography technique.

Next, as shown in FIGS. 8A and 8B, by performing ion implantation using the gate electrode 25B and the resist pattern 26 as a mask, the pocket region 27 and the extension are formed in the second semiconductor region of the semiconductor substrate 21. Region 28 is formed. For example, boron (B) is used as a p-type impurity, and ion implantation is performed four times from different directions under the conditions of an acceleration voltage of 9 kev, a dose amount of 3 × 10 ¹² / cm ² , and an incident angle of 28 degrees. Then, annealing (heat treatment) is performed to form a pocket region 27 in the second semiconductor region of the semiconductor substrate 21. Further, for example, arsenic (As) is used as an n-type impurity, and ion implantation is performed under the conditions of an acceleration voltage of 7 kev, a dose amount of 7 × 10 ¹⁴ / cm ² , and an incident angle of 0 degree. Then, annealing (heat treatment) is performed to form an extension region 28 in the second semiconductor region of the semiconductor substrate 21.

  Since the pocket region 27 and the extension region 28 are formed by ion implantation with a low dose, the polysilicon of the gate electrode 25B in the input / output Tr region is not amorphized but is in a microcrystalline state.

Next, the resist pattern 26 above the semiconductor substrate 21 is removed. For example, the resist pattern 26 is removed by an ashing method using plasma generated by applying a high frequency to a gas containing oxygen gas (O ₂ ).

  Next, thin sidewalls (SW) 29 are formed on the side surfaces of the gate electrode 25A and the gate electrode 25B. The thin SW 29 is formed, for example, by forming an oxide film on the entire surface of the semiconductor substrate 21 and etching back the oxide film. However, in the present embodiment, an example of forming the ThinSW 29 is shown, but the formation of the ThinSW 29 may be omitted.

  Next, as shown in FIGS. 9A and 9B, a resist pattern 30 is formed above the semiconductor substrate 21. Specifically, as shown in FIG. 9B, a resist pattern 30 is formed so as to cover the second semiconductor region of the semiconductor substrate 21 and the gate electrode 25B. As shown in FIG. 9A, an opening is provided in the resist pattern 30 so that the first semiconductor region of the semiconductor substrate 21 and the gate electrode 25A are exposed from the resist pattern 30.

Next, as shown in FIGS. 10A and 10B, etch back is performed to expose the upper surface of the gate electrode 25 </ b> B from the resist pattern 30. In FIG. 10B, a step is formed between the upper surface of the gate electrode 25B and the upper surface of the resist pattern 30, but an edge back is formed so that no step is generated between the upper surface of the gate electrode B and the upper surface of the resist pattern 30. May be performed.

Next, as shown in FIGS. 11A and 11B, by performing ion implantation using the gate electrode 25A, the gate electrode 25B, and the resist pattern 30 as a mask, pockets are formed in the first semiconductor region of the semiconductor substrate 21. Region 31 and extension region 32 are formed. For example, indium (In) is used as a p-type impurity, and ion implantation is performed four times from different directions under the conditions of an acceleration voltage of 60 kev, a dose of 1.5 × 10 ¹³ / cm ² , and an incident angle of 28 degrees. . Thereby, the pocket region 31 is formed in the first semiconductor region of the semiconductor substrate 21. Further, for example, arsenic (As) is used as an n-type impurity, and ion implantation is performed four times under the conditions of an acceleration voltage of 1 kev, a dose amount of 4 × 10 ¹⁴ / cm ² , and an incident angle of 0 degree. As a result, the extension region 32 is formed in the first semiconductor region of the semiconductor substrate 21. Thereafter, annealing (heat treatment) at 1000 ° C./10 sec is performed.

  Ion implantation for forming the pocket region 31 and the extension region 32 is performed at a high dose. That is, the pocket region 31 is formed in the first semiconductor region of the semiconductor substrate 21 shown in FIG. 11 under the condition of a higher dose than the ion implantation for forming the pocket region 27 in the second semiconductor region of the semiconductor substrate 21 shown in FIG. Ion implantation is performed to form. Further, the extension region 32 is formed in the first semiconductor region of the semiconductor substrate 21 shown in FIG. 11 under the condition of a higher dose than the ion implantation for forming the extension region 28 in the second semiconductor region of the semiconductor substrate 21 shown in FIG. Ion implantation is performed to form.

  As shown in FIGS. 11A and 11B, high dose ion implantation is simultaneously performed on the gate electrode 25A in the internal Tr region and the gate electrode 25B in the input / output Tr region. A pocket region 31 is formed in the first semiconductor region of the semiconductor substrate 21 by high dose ion implantation, and an amorphous layer 33 is formed at least above the gate electrode 25A in the internal Tr region and the gate electrode 25B in the input / output Tr region. can do. In addition, the extension region 32 is formed in the first semiconductor region of the semiconductor substrate 21 by high dose ion implantation, and the amorphous layer 33 is formed at least on the gate electrode 25A in the internal Tr region and the gate electrode 25B in the input / output Tr region. Can be formed. When ion implantation is performed using indium (In) or arsenic (As), the amorphous layer 33 is formed above the gate electrode 25A in the internal Tr region and the gate electrode 25B in the input / output Tr region without causing depletion. Can do.

With reference to FIG. 12 and FIG. 13, an acceleration voltage when ion implantation is performed with a high dose will be described. FIG. 12 is a diagram showing a concentration profile of indium (In) when ion implantation is performed while changing the acceleration voltage. The conditions other than the acceleration voltage are as follows. Indium (In) is used as a p-type impurity, and ion implantation is performed four times under different conditions with a dose of 1.5 × 10 ¹³ / cm ² and an incident angle of 28 degrees. It was. The gate electrode 25B has a thickness (height) of 95 nm, and the resist pattern has a thickness (height) of 90 nm.

The vertical axis in FIG. 12 indicates the concentration of indium (In) (10 ¹⁵ to 10 ²⁰ atoms / cm ³ ). The horizontal axis in FIG. 12 is based on the upper surface of the semiconductor substrate 21 and the resist pattern 30, the thickness of the gate oxide film 22 and the semiconductor substrate 21 (10 ⁻⁸ m), and the gate electrode 25B, the gate oxide film 22 and the semiconductor. The thickness (10 ⁻⁸ m) of the substrate 21 is shown.

A solid line C in FIG. 12 indicates the concentration of indium (In) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 80 kev. A dotted line D in FIG. 12 indicates the concentration of indium (In) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 75 kev. A broken line E in FIG. 12 indicates the concentration of indium (In) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 70 kev.

  A solid line F in FIG. 12 indicates the concentration of indium (In) in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 80 kev. A dotted line G in FIG. 12 indicates the concentration of indium (In) in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 75 kev. A broken line H in FIG. 12 indicates the concentration of indium (In) in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 70 kev.

As shown in FIG. 12, when ion implantation is performed with an acceleration voltage of 70 kev, the concentration of indium (In) in the semiconductor substrate 21 is 10 ¹⁷ atoms / cm ³ or less. If the concentration of indium (In) in the semiconductor substrate 21 is 10 ¹⁷ atoms / cm ³ or less, the threshold value of the gate electrode 25B hardly changes. Therefore, if ion implantation is performed at an acceleration voltage of 70 kev or less, the pocket region 31 can be formed in the first semiconductor region of the semiconductor substrate 21 without affecting the threshold value of the gate electrode 25B.

FIG. 13 is a diagram showing a concentration profile of arsenic (As) when ion implantation is performed while changing the acceleration voltage. As conditions other than the acceleration voltage, arsenic (As) was used as an n-type impurity, and ions were implanted four times from different directions under the conditions of a dose amount of 4 × 10 ¹⁴ / cm ² and an incident angle of 0 degree. The gate electrode 25B has a thickness (height) of 95 nm, and the resist pattern has a thickness (height) of 90 nm.

The vertical axis in FIG. 13 indicates the arsenic (As) concentration (10 ¹⁵ to 10 ²⁰ atoms / cm ³ ). The horizontal axis in FIG. 13 is based on the upper surface of the semiconductor substrate 21, and the resist pattern 30, the thickness of the gate oxide film 22 and the semiconductor substrate 21 (10 ⁻⁸ m), and the gate electrode 25B, the gate oxide film 22 and the semiconductor. The thickness (10 ⁻⁸ m) of the substrate 21 is shown.

  A solid line J in FIG. 13 indicates the concentration of arsenic (As) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 1 kev. A dotted line K in FIG. 13 indicates the concentration of arsenic (As) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 40 kev. A broken line L in FIG. 13 indicates the concentration of arsenic (As) in the resist pattern 30, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 50 kev.

  A solid line M in FIG. 13 indicates the concentration of arsenic (As) in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 1 kev. A dotted line N in FIG. 13 indicates the arsenic (As) concentration in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 40 kev. A broken line O in FIG. 13 indicates the concentration of arsenic (As) in the gate electrode 25B, the gate oxide film 22, and the semiconductor substrate 21 when ion implantation is performed with an acceleration voltage of 50 kev.

As shown in FIG. 13, when ion implantation is performed with an acceleration voltage of 40 kev, the arsenic (As) concentration in the semiconductor substrate 21 is 10 ¹⁷ atoms / cm ³ or less. If the concentration of arsenic (As) in the semiconductor substrate 21 is 10 ¹⁷ atoms / cm ³ or less, the threshold change of the gate electrode 25B hardly occurs. Therefore, if ion implantation is performed at an acceleration voltage of 40 keV or less, the extension region 32 can be formed in the first semiconductor region of the semiconductor substrate 21 without affecting the threshold value of the gate electrode 25B.

Returning to the description of the semiconductor device manufacturing method according to the first embodiment. As shown in FIGS. 14A and 14B, the resist pattern 30 above the semiconductor substrate 21 is removed. For example, the resist pattern 30 is removed by an ashing (ashing) method using plasma generated by applying a high frequency to a gas containing oxygen gas (O ₂ ).

Next, as shown in FIGS. 14A and 14B, a sidewall film 34 is formed on the side of the gate electrode 25A in the internal Tr region, and the side film is formed on the side of the gate electrode 25B in the input / output Tr region. A wall film 34 is formed. The sidewall film 34 is, for example, a nitride film. For example, after forming a nitride film over the semiconductor substrate 21, the nitride film is etched back to form the sidewall films 34 on the sides of the gate electrode 25A and the gate electrode 25B. The nitride film is formed, for example, by a CVD method using silane (SiH ₄ ) and ammonia (NH ₃ ) at a film formation temperature of 545 ° C.

  When the deposition temperature of the nitride film is set to 545 ° C., the grain size of the polysilicon of the gate electrode 25A and the gate electrode 25B increases, and the polysilicon of the gate electrode 25A and the gate electrode 25B becomes the single crystal silicon 35. As shown in FIGS. 14A and 14B, since the amorphous layer 33 is formed on the gate electrode 25A and the gate electrode 25B, the upper part of the gate electrode 25A and the gate electrode 25B is the amorphous layer 33. The lower part is single crystal silicon 35.

  Next, as shown in FIGS. 15A and 15B, ion implantation is performed to form a source / drain diffusion region 36 in the first semiconductor region of the semiconductor substrate 21, and the second semiconductor of the semiconductor substrate 21. A source / drain diffusion region 37 is formed in the region.

For example, first, phosphorus (P) is used as an n-type impurity, and ion implantation is performed under the conditions of an acceleration voltage of 15 kev, a dose of 5 × 10 ¹³ / cm ² , and an incident angle of 0 degrees. Next, using phosphorus (P) as an n-type impurity, ion implantation is performed under the conditions of an acceleration voltage of 5 kev, a dose of 6 × 10 ¹⁵ / cm ² , and an incident angle of 0 degree. Then, annealing (heat treatment) at 1030 ° C./3 sec is performed, the source / drain diffusion region 36 is formed in the first semiconductor region of the semiconductor substrate 21, and the source / drain diffusion region 37 is formed in the second semiconductor region of the semiconductor substrate 21.

  As described above, by performing ion implantation twice, the source / drain diffusion region 36 is formed in the first semiconductor region of the semiconductor substrate 21, and the source / drain diffusion region 37 is formed in the second semiconductor region of the semiconductor substrate 21. By performing ion implantation twice under different conditions, a concentration gradient is formed in the source / drain diffusion region 36 and the source / drain diffusion region 37.

  An n-type impurity is added to the gate electrode 25A and the gate electrode 25B by ion implantation when forming the source / drain diffusion region 36 and the source / drain diffusion region 37 in the semiconductor substrate 21. As shown in FIGS. 15A and 15B, an amorphous layer 33 is formed on the gate electrode 25A and the gate electrode 25B. Therefore, channeling is suppressed by the amorphous layer 33 on the gate electrode 25A and the gate electrode 25B, and penetration of n-type impurities into the gate electrode 25A and the gate electrode 25B is suppressed. Therefore, the amorphous layer 33 functions as a suppression layer that suppresses the penetration of impurities into the gate electrode 25A and the gate electrode 25B.

FIG. 16 is a diagram showing a phosphorus (P) concentration profile immediately after ion implantation when forming the source / drain diffusion region 36 and the source / drain diffusion region 37 in the semiconductor substrate 21. The ion implantation uses phosphorus (P) as an n-type impurity, an acceleration voltage of 15 kev, and a dose amount of 5
The conditions are × 10 ¹³ / cm ² , the incident angle is 0 °, the acceleration voltage is 5 kev, the dose is 6 × 10 ¹⁵ / cm ² , and the incident angle is 0 °.

The vertical axis in FIG. 16 indicates the phosphorus (P) concentration (10 ¹⁵ to 10 ²² atoms / cm ³ ). The horizontal axis of FIG. 16 is based on the upper surface of the semiconductor substrate 21, and the thickness (10 ⁻⁸ m) of the gate electrode 25A, the gate oxide film 22 and the semiconductor substrate 21, and the gate electrode 25B, the gate oxide film 22 and the semiconductor. The thickness (10 ⁻⁸ m) of the substrate 21 is shown.

  A solid line P in FIG. 16 indicates the concentration of phosphorus (P) in the gate electrode 25 </ b> A, the gate oxide film 22, and the semiconductor substrate 21. As shown in FIG. 16, it can be seen that phosphorus (P) does not exist in the gate oxide film 22 and the semiconductor substrate 21, and phosphorus (P) does not penetrate through the gate electrode 25A.

  A solid line Q in FIG. 16 indicates the concentration of phosphorus (P) in the gate electrode 25 </ b> B, the gate oxide film 22, and the semiconductor substrate 21. As shown in FIG. 16, it can be seen that phosphorus (P) does not exist in the gate oxide film 22 and the semiconductor substrate 21, and phosphorus (P) does not penetrate through the gate electrode 25B.

FIG. 17 is a diagram showing a phosphorus (P) concentration profile immediately after ion implantation when forming a source / drain diffusion region in the semiconductor substrate 1 in the conventional example shown in FIG. The ion implantation uses phosphorus (P) as an n-type impurity, an acceleration voltage of 15 kev, a dose amount of 5 × 10 ¹³ / cm ² , an incident angle of 0 degree, an acceleration voltage of 5 kev, and a dose amount of 6 The condition is × 10 ¹⁵ / cm ² and the incident angle is 0 degree.

The vertical axis in FIG. 17 indicates the phosphorus (P) concentration (10 ¹⁵ to 10 ²² atoms / cm ³ ). The horizontal axis of FIG. 17 indicates the thickness (10 ⁻⁸ m) of the gate electrode 3A, the gate oxide film 2 and the semiconductor substrate 1, and the gate electrode 3B, the gate oxide film 2 and the semiconductor with respect to the upper surface of the semiconductor substrate 1. The thickness (10 ⁻⁸ m) of the substrate 1 is shown.

  17 indicates the concentration of phosphorus (P) in the gate electrode 3A, the gate oxide film 2, and the semiconductor substrate 1, and the solid line S in FIG. 17 indicates the gate electrode 3B, the gate oxide film 2, and the semiconductor substrate 1. Shows the concentration of phosphorus (P). As shown in FIG. 17, it can be seen that phosphorus (P) exists in the gate oxide film 2 and the semiconductor substrate 1, and the penetration of phosphorus (P) into the gate electrode 3B occurs.

  The pocket region 27 and the pocket region 31 suppress the extension of the depletion layer and suppress the short channel effect. In the method of manufacturing the semiconductor device according to the first embodiment, the pocket region 27 and the pocket region 31 are formed on the semiconductor substrate 21. However, the pocket region 27 and the pocket region 31 are not formed on the semiconductor substrate 21. Also good. That is, in FIG. 8, the pocket region 27 may not be formed in the second semiconductor region of the semiconductor substrate 21. In FIG. 11, the pocket region 31 may not be formed in the first semiconductor region of the semiconductor substrate 21.

  In FIG. 11, ion implantation for forming the extension region 32 in the first semiconductor region of the semiconductor substrate 21 is performed under a high dose condition. Therefore, even if the pocket region 31 is not formed in the first semiconductor region of the semiconductor substrate 21, in FIG. 11, an amorphous layer is formed at least above the gate electrode 25A in the internal Tr region and the gate electrode 25B in the input / output Tr region. 33 is formed.

  A second example of the semiconductor device and the manufacturing method thereof according to this embodiment will be described. In the method of manufacturing the semiconductor device according to the first embodiment, as described with reference to FIGS. 9 and 10, the resist pattern 30 is formed over the semiconductor substrate 21 and etched back to thereby form the gate electrode 25 </ b> B from the resist pattern 30. The top surface of was exposed. In the semiconductor device manufacturing method according to the second embodiment, an example in which the upper surface of the gate electrode 25B is exposed from the resist pattern 43 by adjusting the exposure amount will be described. In addition, about the same component, the code | symbol same as Example 1 is attached | subjected, and the description is abbreviate | omitted. Further, the drawings in FIGS. 1 to 17 are referred to as necessary.

  In the method for manufacturing a semiconductor device according to the second embodiment, the same steps as those described with reference to FIGS. 6 to 8 of the method for manufacturing a semiconductor device according to the first embodiment are performed. Then, the resist pattern 26 above the semiconductor substrate 21 is removed. Next, as shown in FIGS. 18A and 18B, a resist film 40 is applied over the semiconductor substrate 21 by, eg, spin coating.

  Next, as shown in FIGS. 19A and 19B, a semiconductor substrate is used by using a photomask (light-shielding portion) 41 having openings above the first semiconductor region and the second semiconductor region of the semiconductor substrate 21. The resist film 40 formed above the first semiconductor region 21 and the second semiconductor region 21 is exposed. For example, the resist film 40 is exposed using an excimer laser (KrF). In this case, by adjusting the exposure amount, as shown in FIGS. 19A and 19B, the upper portion of the resist film 40 formed above the first semiconductor region and the second semiconductor region of the semiconductor substrate 21. To expose. In FIGS. 19A and 19B, the photomask 41 having openings above the first semiconductor region and the second semiconductor region of the semiconductor substrate 21 is used, but the second semiconductor region of the semiconductor substrate 21 is used. You may use the photomask 41 by which only upper direction was opened.

  Next, as shown in FIGS. 20A and 20B, the first semiconductor substrate 21 is formed using a photomask (light-shielding portion) 42 having an opening only above the first semiconductor region of the semiconductor substrate 21. The resist film 40 formed above the semiconductor region is exposed. For example, the resist film 40 is exposed using an excimer laser (KrF). In this case, by adjusting the exposure amount, as shown in FIGS. 20A and 20B, the entire resist film 40 formed above the first semiconductor region of the semiconductor substrate 21 is exposed.

  Next, as shown in FIGS. 21A and 21B, the resist film 40 is developed to expose the first semiconductor region of the semiconductor substrate 21, the upper surfaces of the gate electrode 25A and the gate electrode 25B. A pattern 43 is formed. The development of the resist film 40 is performed by, for example, a wet process using a chemical solution. In FIG. 21B, there is a step between the upper surface of the gate electrode 25B and the upper surface of the resist pattern 43, but the upper surface of the gate electrode B and the upper surface of the resist pattern 43 are adjusted by adjusting the exposure amount. A step may be prevented from occurring.

  With respect to the resist film 40 above the first semiconductor region of the semiconductor substrate 21, the exposure amount is adjusted to expose the entire resist film 40, and then the resist film 40 is developed. Thereby, the first semiconductor region of the semiconductor substrate 21 and the gate electrode 25 </ b> A can be exposed from the resist pattern 43. Further, with respect to the resist film 40 above the second semiconductor region of the semiconductor substrate 21, the exposure amount is adjusted to expose the upper portion of the resist film 40, and then the resist film 40 is developed. Thereby, the upper surface of the gate electrode 25 </ b> B can be exposed from the resist pattern 43. After the upper surface of the gate electrode 25B is exposed from the resist pattern 43, the same steps as those described in FIGS. 11, 14, and 15 of the method for manufacturing the semiconductor device according to the first embodiment are performed.

1, 21 Semiconductor substrate 2, 22 Gate insulating film 3A, 3B, 25A, 25B Gate electrode 4, 24 Element isolation region 5, 9, 26, 30, 43 Resist pattern 6, 10, 27, 31 Pocket region 7, 11, 28, 32 Extension region 8, 29 Thin sidewall 12, 33 Amorphous layer 13, 34 Side wall film 14, 35 Single crystal silicon 15, 36, 37 Source / drain diffusion region 23 Polysilicon film 40 Resist film 41, 42 Photomask ( Shading part)

Claims (6)

A polycrystalline silicon film is formed over the substrate, and the polycrystalline silicon is etched to form a first gate electrode over the first region of the substrate, and a second gate electrode over the second region of the substrate. Forming, and
Forming a first resist pattern covering the first region and the first gate electrode above the substrate;
Forming a first extension region in the second region by implanting a first impurity in the second region with a first dose using the second gate electrode and the first resist pattern as a mask;
Removing the first resist pattern;
Forming a second resist pattern covering the first extension region and exposing the top surfaces of the first gate electrode, the first region, and the second gate electrode above the substrate;
Using the first gate electrode, the second gate electrode, and the second resist pattern as a mask, a second impurity is implanted into the first region at a second dose larger than the first dose. Forming a second extension region in one region and amorphizing at least an upper portion of the first gate electrode and the second gate electrode;
A method for manufacturing a semiconductor device, comprising: Forming the second resist pattern above the substrate;
Forming the second resist pattern so as to cover the second region and the second gate electrode;
Etching back the second resist pattern to expose an upper surface of the second gate electrode from the second resist pattern;
The method of manufacturing a semiconductor device according to claim 1, comprising: Forming the second resist pattern above the substrate;
Forming a resist film above the substrate;
Exposing the upper part of the resist film formed above the first region and above the second region using a first exposure mask having openings above the first region and above the second region;
Exposing the resist film formed above the first region using a second exposure mask having an opening above the first region;
Forming the second resist pattern on the substrate by exposing the upper surface of the first gate electrode, the first region, and the second gate electrode by developing the resist film;
The method of manufacturing a semiconductor device according to claim 1, comprising: Removing the second resist pattern;
Forming sidewalls on the sides of the first gate electrode and the second gate electrode;
A source / drain region is formed in the first region and the second region by implanting a third impurity into the first region and the second region using the first gate electrode, the second gate electrode, and the sidewall as a mask. Process,
The method for manufacturing a semiconductor device according to claim 1, further comprising: Forming a polycrystalline silicon film over the substrate and etching the polycrystalline silicon to form a gate electrode over the substrate;
Forming an extension region in the substrate by implanting a first impurity in the substrate at a first dose using the gate electrode as a mask;
Forming a resist film above the substrate;
Exposing an upper portion of the resist film formed above the substrate using an exposure mask having an opening above at least the gate electrode; and
Developing the resist film to form a resist pattern having an opening in which the upper surface of the gate electrode is exposed above the substrate;
A process of amorphizing at least an upper portion of the gate electrode by injecting a second impurity into the upper surface of the gate electrode at a second dose larger than the first dose using the resist pattern as a mask;
A method for manufacturing a semiconductor device, comprising: Removing the resist pattern;
Forming a sidewall on the side of the gate electrode;
Forming a source / drain region in the substrate by injecting a third impurity into the substrate using the gate electrode and the sidewall as a mask;
The method of manufacturing a semiconductor device according to claim 5, further comprising:

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