JP2011060962A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be improved in breakdown voltage, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes a GaN layer 10, a first insulating layer 13, a second insulating layer 14, an electrode layer, and an FP electrode 17. The GaN layer 10 includes a high-defect region 10a and a low-defect region 10b lower in defect density than the high-defect region 10a, and has a principal surface 10c. The first insulating layer 13 is formed so as to cover the high-defect region 10a on the principal surface 10c of the GaN layer 10. The second insulating layer 14 is formed on the low-defect region 10b on the principal surface 10a of the GaN layer 10, and has an opening formed. The electrode layer is formed in the opening in contact with the principal surface 10a of the GaN layer 10. The FP electrode 17 is formed to be connected with the electrode layer and to overlap the second insulating layer 14. The thickness H13 of the first insulating layer 13 is larger than the thickness H14 of the second insulating layer 14. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, a semiconductor device is manufactured by preparing a high-quality gallium nitride (GaN) substrate having a low dislocation density over a wide region and forming an epitaxial growth layer on the substrate. Examples of such a semiconductor device include Japanese Unexamined Patent Application Publication No. 2007-184371 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2007-227790 (Patent Document 2).

  Patent Documents 1 and 2 disclose a diode including a first conductivity type GaN-based semiconductor layer, an insulating film, and a first electrode. The first conductivity type GaN-based semiconductor layer includes first to third regions. The second region is provided between the first region and the third region. The first and third regions have a threading dislocation density that is less than the first threading dislocation density. The second region has a threading dislocation density that is greater than the first threading dislocation density. The first electrode forms a Schottky junction in the first and third regions. The insulating film is provided between the second region and the first electrode. According to Patent Documents 1 and 2, it is disclosed that an insulating film can be formed in a second region (core) having a high threading dislocation density, thereby reducing the influence of the second region and increasing the element area. ing.

JP 2007-184371 A JP 2007-227790 A

  However, the present inventor has found that when the field plate (FP) structure is applied to the diodes disclosed in Patent Documents 1 and 2, there is a problem that the breakdown voltage cannot be sufficiently improved.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method that can improve the breakdown voltage.

  The present inventor has a problem that the withstand voltage cannot be sufficiently improved when the field plate (FP) structure is applied to the diodes disclosed in Patent Documents 1 and 2 above, and the required characteristics of the insulating film used for the FP structure and the core portion are covered. It was found that the required characteristics of the insulating film are different. Specifically, when an insulating film covering the core is formed in accordance with the required characteristics of the insulating film used for the FP structure, the withstand voltage cannot be improved because the thickness of the insulating film covering the core is insufficient. If the insulating film used for the FP structure is formed in accordance with the required characteristics of the insulating film covering the core, the structure cannot be suitable as the FP structure, and the breakdown voltage cannot be improved.

  As described above, as a result of the present inventors diligently researching the required characteristics applicable to the semiconductor device having the FP structure, when the thickness of the insulating film covering the core portion is larger than the thickness of the insulating film used for the FP structure, It was found that the breakdown voltage can be improved.

  Therefore, the semiconductor device of the present invention includes a gallium nitride (GaN) layer, a first insulating layer, a second insulating layer, an electrode layer, and a field plate electrode (FP electrode). The gallium nitride layer includes a high defect region and a low defect region having a defect density lower than that of the high defect region, and has a main surface and a back surface opposite to the main surface. The first insulating layer is formed so as to cover the high defect region on the main surface of the gallium nitride layer. The second insulating layer is formed on the low defect region on the main surface of the gallium nitride layer, and an opening is formed. The electrode layer is formed in the opening so as to be in contact with the main surface of the gallium nitride layer. The FP electrode is formed so as to be connected to the electrode layer and to overlap the second insulating layer. The thickness of the first insulating layer is larger than the thickness of the second insulating layer.

  The method for manufacturing a semiconductor device of the present invention includes the following steps. A gallium nitride layer including a high defect region and a low defect region having a defect density lower than that of the high defect region and having a main surface and a back surface opposite to the main surface is prepared. A first insulating layer is formed so as to cover the high defect region on the main surface of the gallium nitride layer. A second insulating layer having an opening is formed on the low defect region on the main surface of the gallium nitride layer. An electrode layer is formed in the opening so as to be in contact with the main surface of the gallium nitride layer. A field plate electrode is formed so as to be connected to the electrode layer and to overlap the second insulating layer. In the step of forming the second insulating layer, a second insulating layer having a thickness smaller than that of the first insulating layer is formed.

  According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, the thickness of the first insulating layer covering the high defect region is larger than the thickness of the second insulating layer forming the FP structure. Thereby, the withstand voltage of the first insulating layer itself can be improved, and the optimum structure as the insulating layer for the FP of the second insulating layer can be realized, so that the withstand voltage can be improved based on the electric field relaxation by the FP structure. That is, it is possible to achieve both the necessary characteristics of the first insulating layer covering the high defect region and the necessary characteristics of the second insulating layer that constitutes the optimum structure as the FP insulating layer. For this reason, generation | occurrence | production of the leakage current in the 1st insulating layer on a high defect area | region can be suppressed, obtaining the pressure | voltage resistant improvement effect by FP structure. Therefore, a semiconductor device with improved breakdown voltage can be realized.

  Preferably, in the semiconductor device, the first insulating layer includes a material having a dielectric constant smaller than a dielectric constant of a material constituting the second insulating layer.

  Preferably, in the method of manufacturing a semiconductor device, in the step of forming the first insulating layer, the first insulating layer including a material having a dielectric constant smaller than that of the material constituting the second insulating layer is formed. To do.

  Since the MIS (Metal-Insulator-Semiconductor) capacitance is proportional to the dielectric constant, the MIS capacitance component of the first insulating layer can be reduced. Thereby, the response characteristic of the semiconductor device can be improved.

  Preferably, in the method for manufacturing a semiconductor device, the step of forming the first insulating layer and the step of forming the second insulating layer include the following steps. An insulating layer is formed so as to cover the main surface of the gallium nitride layer. A part of the insulating layer is removed so as to reduce the thickness of the region formed on the low defect region in the insulating layer. An opening is formed in the insulating layer formed on the low defect region.

  After forming the insulating layers to be the first and second insulating layers, the thickness of the insulating layer to be the second insulating layer is reduced. Thereby, a semiconductor device in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer can be manufactured. Therefore, a semiconductor device capable of improving the breakdown voltage can be manufactured.

  Preferably, in the method for manufacturing a semiconductor device, the step of forming the first insulating layer includes a step of forming a lower first insulating layer so as to cover a high defect region on the main surface of the gallium nitride layer, and a lower first Forming the upper first insulating layer on the insulating layer, and forming the second insulating layer includes forming the lower first insulating layer or forming the upper first insulating layer. Perform simultaneously with the process.

  Separately from the step of forming the second insulating layer, the upper first insulating layer or the lower first insulating layer constituting the first insulating layer is formed. Thereby, a semiconductor device in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer can be manufactured. Therefore, a semiconductor device capable of improving the breakdown voltage can be manufactured.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, since the thickness of the first insulating layer is larger than the thickness of the second insulating layer, the breakdown voltage can be improved.

1 is a plan view schematically showing a Schottky barrier diode (SBD) as a semiconductor device in Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view schematically showing a region 1a in FIG. It is a top view which shows schematically another SBD in Embodiment 1 of this invention. It is a flowchart which shows the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 1 of this invention. It is a figure which shows SBD in Embodiment 2 of this invention roughly, is equivalent to the area | region 1a in FIG. 1, and is equivalent to sectional drawing along the II-II line. It is a flowchart which shows the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 2 of this invention. It is a figure which shows SBD in Embodiment 3 of this invention roughly, is equivalent to the area | region 1a in FIG. 1, and is equivalent to sectional drawing along the II-II line. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 4 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 4 of this invention. It is sectional drawing which shows schematically the manufacturing process of SBD in Embodiment 4 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
A Schottky Barrier Diode (SBD) 1 that is an example of a semiconductor device in the present embodiment will be described with reference to FIGS. As shown in FIGS. 1 and 2, the SBD 1 in the present embodiment includes a GaN layer 10 including a GaN substrate 11 and an epitaxial layer 12, a first insulating layer 13, a second insulating layer 14, and a Schottky electrode 16. And an electrode 15 including a field plate electrode (FP electrode) 17 and an ohmic electrode 18.

  The GaN layer 10 includes a GaN substrate 11 and an epitaxial layer 12. The GaN layer 10 includes a high defect region (core) 10a, a low defect region 10b having a defect density lower than that of the high defect region 10a, and has a main surface 10c and a back surface 10d opposite to the main surface 10c. is doing. The high defect region 10 a of the epitaxial layer 12 is continuous with the high defect region 10 a of the GaN substrate 11, and the low defect region 10 b of the epitaxial layer 12 is continuous with the low defect region 10 b of the GaN substrate 11.

  Although the high defect region 10a is formed in a stripe shape as shown in FIG. 1, it is not particularly limited to this. For example, as shown in FIG. 3, the high defect area 10a may be formed in a dot shape.

The GaN substrate 11 has a main surface 11a and a back surface 11b opposite to the main surface 11a. The GaN substrate is made of, for example, n ⁺ -GaN. Note that n ⁺ -GaN means that n-type impurities are doped at a higher concentration than the n-GaN layer.

Epitaxial layer 12 is formed on main surface 11 a of GaN substrate 11. Epitaxial layer 12 is made of, for example, n ⁻ -GaN. Note that n ⁻ -GaN means that n-type impurities are doped at a lower concentration than the n-GaN layer.

  The thickness W of the epitaxial layer 12 is such that the shortest distance L from the end of the first insulating layer 13 to the end of the high defect region 10a in the epitaxial layer 12 (the main layer of the epitaxial layer 12 of the element surrounded by the high defect region 10a). It is preferable that the length of the surface 12a overlaps the first insulating layer 13) or less. Since the main surface 12a of the epitaxial layer 12 in the high defect region 10a has the same potential as the back surface 12b, the distance L of the first insulating layer 13 covering the high defect region 10a from the end of the high defect region 10a in the epitaxial layer 12 By ensuring the thickness to be equal to or greater than the thickness W of the epitaxial layer 12, the breakdown voltage can be further ensured.

The “high defect region” means a region having a defect density higher than that of the low defect region. “A region with a high defect density” is a region such as a dislocation concentration region or an inversion layer region. The “dislocation concentration region” means a region having a relatively high dislocation density (for example, a region that is two digits or more higher) than other regions. For example, the dislocation density of the high defect region 10a exceeds 1 × 10 ⁸ cm ⁻² , and the dislocation density of the low defect region 10b is 1 × 10 ⁸ cm ⁻² or less. This includes a case where the dislocation concentration region is intentionally formed at the time of manufacturing the GaN layer 10 and the other regions have a low dislocation density, and a case where the dislocation concentration region is formed unintentionally for some reason. The “inversion layer region” means a region where a crystal plane having a polarity opposite to that of the other region is present on the main surface 10c and the back surface 10d of the GaN layer 10 when made of crystals having polarity. For example, in the main surface 10c of the GaN layer 10, the high defect region 10a is an N surface, the low defect region 10b is a Ga surface, and in the back surface 10d of the GaN layer 10, the high defect region 10a is a Ga surface. The defect area 10b is the N plane. The inversion layer region also includes a case where it is intentionally formed to ensure the quality of other regions and a case where it is formed unintentionally for some reason.

  The first insulating layer 13 is formed so as to cover the entire high defect region 10 a on the main surface 12 a of the epitaxial layer 12. That is, the high defect region 10 a on the main surface 12 a of the epitaxial layer 12 is not exposed by the first insulating layer 13.

  The second insulating layer 14 is formed on the low defect region 10b in the main surface 10c of the GaN layer 10 (main surface 12a of the epitaxial layer 12), and an opening is formed. The second insulating layer 14 constitutes an FP structure. The second insulating layer 14 is disposed adjacent to the first insulating layer 13 with the Schottky electrode 16 interposed therebetween.

  The thickness H13 of the first insulating layer 13 is larger than the thickness H14 of the second insulating layer 14. The thickness H13 of the first insulating layer 13 has a thickness (for example, 100 nm or more and 10 μm or less) necessary for reducing the influence of the high defect region 10a. The thickness H14 of the second insulating layer 14 has an appropriate thickness (for example, 10 nm or more and 5 μm or less) as the FP insulating layer. The thickness H13 of the first insulating layer 13 is preferably larger than the thickness H14 of the second insulating layer 14 by, for example, 100 nm or more and 10 μm or less.

  Here, the “thickness H13 of the first insulating layer 13” and the “thickness H14 of the second insulating layer 14” are values at the thickest positions in the first and second insulating layers 13 and 14, respectively. is there.

The first insulating layer 13 preferably includes a material having a dielectric constant smaller than that of the material constituting the second insulating layer 14. As such a material, silicon dioxide (SiO ₂ ) or a so-called low-k material having a low relative dielectric constant can be used for the first insulating layer 13. Examples of the low-k material include carbon-containing silicon oxide (SiOC). The second insulating layer 14 includes, for example, a silicon nitride film (SiN _x film), a silicon oxynitride film (SiON film), an aluminum nitride (AlN), a silicon oxycarbide film (SiOC film), magnesium oxide (MgO), oxide Zirconium (ZrO ₂ ), hafnium oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), scandium oxide (Sc ₂ O ₃ ), or the like can be used.

Here, the “dielectric constant” is a value measured using an impedance measurement method.
Further, the first insulating layer 13 may be two or more layers. In the case of two or more layers, it is only necessary that at least one layer constituting the first insulating layer 13 has a dielectric constant smaller than that of the material constituting the second insulating layer 14.

  The electrode 15 includes a Schottky electrode 16 and an FP electrode 17. The electrode 15 is formed, for example, so that the planar shape is circular. The FP electrode 17 and the second insulating layer 14 form a field plate (FP) structure.

  Schottky electrode 16 is formed in the opening of second insulating layer 14 so as to be in contact with main surface 12a of epitaxial layer 12. In other words, the Schottky electrode 16 is formed between the first insulating layer 13 and the second insulating layer 14 on the main surface 12 a of the epitaxial layer 12. The Schottky electrode 16 forms a Schottky junction with the epitaxial layer 12. The Schottky electrode 16 is made of a material such as nickel (Ni) or gold (Au).

  The FP electrode 17 is connected to the Schottky electrode 16 and is formed so as to overlap the second insulating layer 14. The FP electrode 17 is made of a material such as Ni or Au, for example.

  The ohmic electrode 18 is formed on the back surface 11b of the GaN substrate 11 (the back surface 10d of the GaN layer 10). The ohmic electrode 18 forms an ohmic junction with the GaN substrate 11. The ohmic electrode 18 is made of, for example, any one of titanium (Ti), aluminum (Al), Au, and the like, or two or more of these materials.

  Next, with reference to FIGS. 1 to 16, a method for manufacturing a semiconductor device in the present embodiment will be described.

  As shown in FIGS. 4 and 5, first, a main surface 11a and a back surface 11b opposite to the main surface 11a are included, including a high defect region 10a and a low defect region 10b having a defect density lower than that of the high defect region 10a. Is prepared (step S1).

  In this step S1, it is preferable to prepare a GaN substrate in which high defect regions 10a are periodically present. For example, as shown in FIG. 1, a GaN substrate 11 in which high defect regions 10a are formed in stripes, and a GaN substrate 11 in which high defect regions 10a are formed in dots as shown in FIG. 3 are prepared.

  Next, as shown in FIGS. 4 and 6, the epitaxial layer 12 is formed on the GaN substrate 11 (step S2). The formation method of the epitaxial layer 12 is not specifically limited, For example, MOCVD (Metal Organic Chemical Vapor Deposition) method etc. can be employ | adopted. At this time, the high defect region 10 a formed in the GaN substrate 11 is taken over by the epitaxial layer 12. Thereby, the epitaxial layer 12 including the high defect region 10a and the low defect region 10b having a defect density lower than that of the high defect region 10a and having the main surface 12a and the back surface 12b opposite to the main surface 12a can be formed. .

  In step S2, when the epitaxial layer 12 is formed on the GaN substrate 11, the high defect region 10a becomes a recess on the main surface, and a step is formed on the main surface. Further, when the low defect region 10b on the main surface 10c is a Ga atom plane, the high defect region 10a on the main surface 10c is an N atom plane.

  By performing steps S1 and S2, the main surface 10c and the back surface 10d opposite to the main surface 10c include the high defect region 10a and the low defect region 10b having a defect density lower than that of the high defect region 10a. Can be prepared.

Next, as shown in FIG. 7, an insulating layer 21 to be the first insulating layer 13 and the second insulating layer 14 is formed so as to cover the main surface 10 c of the GaN layer 10. In this step, the insulating layer 21 made of, for example, SiN _x is formed by, for example, a plasma CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 8, the ohmic electrode 18 is formed on the back surface 10d of the GaN layer 10 (step S3). In this step S3, for example, after the back surface 11b of the GaN substrate 11 is subjected to organic cleaning and hydrochloric acid cleaning, Ti / Al / Ti / Au (20 nm / 100 nm / 20 nm / 200 nm) is deposited using an EB (Electron Beam) evaporation method. It is formed on the entire back surface 11b. Thereafter, heating is performed at 600 ° C. for about 2 minutes in a nitrogen atmosphere, and alloying is performed to form the ohmic electrode 18.

  Next, as shown in FIG. 9, a mask layer such as a resist having a pattern in which a region (a region other than a region to be the first insulating layer 13) formed on the low defect region 10 b in the insulating layer 21 is opened. 22 is formed. Thereafter, a part of the insulating layer 21 is removed so as to reduce the thickness of the region formed on the low defect region 10b in the insulating layer 21 (the region exposed from the opening pattern of the mask layer 22 in the insulating layer 21). . That is, the thickness of the insulating layer 21 formed on the low defect region 10b is adjusted. The method of removing is not particularly limited, but can be removed by etching, for example. Etching may be either wet etching or dry etching. Thereby, as shown in FIG. 10, the insulating layer 21 has a region covering the high defect region 10a and having a thickness H13, and a region covering the low defect region 10b and having a thickness H14.

  Next, as shown in FIG. 11, the mask layer 22 is removed. The method for removing the mask layer 22 is not particularly limited. For example, organic cleaning, asher treatment in an atmosphere containing oxygen and nitrogen, and the like can be applied.

  Next, as shown in FIG. 12, a mask layer 23 such as a resist in which a region to be an opening of the second insulating layer 14 (a region where the Schottky electrode 16 is formed) is opened is formed. Thereafter, as shown in FIG. 13, the region of the insulating layer 21 exposed from the opening pattern of the mask layer 23 is removed. The method for removing is not particularly limited, but can be removed by etching. As the etching, either wet etching or dry etching may be applied, but it is preferable to apply wet etching from the viewpoint of reducing damage to the GaN layer 10. When wet etching is applied, for example, BHF (Buffered Hydrogen Fluoride) can be used. Thereby, the 1st insulating layer 13 and the 2nd insulating layer 14 which has an opening part can be formed.

  Next, the mask layer 23 is removed as shown in FIG. Since removal of mask layer 23 is similar to mask layer 22 described above, description thereof will not be repeated.

  Through the above steps, as shown in FIGS. 4 and 14, the step of forming the first insulating layer 13 (step S4) and the step of forming the second insulating layer 14 (step S5) can be performed. . Thereby, the second insulating layer 14 having a thickness H14 smaller than the thickness H13 of the first insulating layer 13 can be formed.

  Next, as shown in FIG. 15, a mask layer 24 such as a resist having an opening in a region where the electrode 15 is to be formed is formed. Next, for example, after surface treatment of the GaN epitaxial layer 12 by hydrochloric acid cleaning is performed at room temperature for 3 minutes, an electrode 25 is formed as shown in FIG. In this step, for example, Ni / Au, for example, is formed as the electrode 25 by resistance heating vapor deposition.

  Thereafter, the mask layer 24 is removed. At this time, the electrode 25 formed on the mask layer 24 is simultaneously removed (lifted off). As a result, as shown in FIG. 2, the Schottky electrode 16 that contacts the main surface 12a of the epitaxial layer 12 inside the opening of the second insulating layer 14 is connected to the Schottky electrode 16 and the first insulation is formed. An electrode 15 having an FP electrode 17 formed in a portion overlapping the layer 14 can be formed (step S6). Since the formation and removal of the mask layer 24 are the same as those of the mask layer 22, the description thereof will not be repeated.

  The SBD 1 shown in FIGS. 1 to 3 can be manufactured by performing the above steps (steps S1 to S6). In addition, about the said process (S1-S6), it is an example of the manufacturing method of SBD, You may provide another process and may change the order of a process.

  In the SBD manufacturing method of the present embodiment, the example in which the first and second insulating layers 13 and 14 are formed from the insulating layer 21 has been described. However, the present invention is not particularly limited thereto, and the first insulating layer is not limited thereto. After forming 13, the second insulating layer 14 may be formed. Alternatively, the first insulating layer 13 may be formed after the second insulating layer 14 is formed.

  In the SBD manufacturing method of the present embodiment, the example in which the Schottky electrode 16 and the FP electrode 17 are simultaneously formed in step S6 has been described. However, the FP electrode 17 is formed after the step of forming the Schottky electrode 16. You may provide the process to do. That is, the Schottky electrode 16 is formed in the opening formed in the second insulating layer 14 so as to be in contact with the epitaxial layer 12, and then connected to the Schottky electrode 16 and the second insulating layer. The FP electrode 17 may be formed so as to overlap with 14. In this case, the FP electrode 17 may be formed of the same material as the Schottky electrode 16. Alternatively, the FP electrode 17 may be formed using a material different from the material of the Schottky electrode 16 such as a material having good adhesiveness with the second insulating layer 14.

  Next, the operation of the Schottky barrier diode 1 in the present embodiment will be described. In order to turn on the Schottky barrier diode 1, a relatively positive voltage is applied to the electrode 15 on the anode electrode side, and a relatively negative voltage is applied to the ohmic electrode 18 on the cathode electrode side. A forward bias is applied to the Schottky barrier diode 1. As a result, a current flows from the electrode 15 on the anode electrode side to the ohmic electrode 18 on the cathode electrode side. At this time, in the Schottky barrier diode 1, a current flows in parallel to each of a plurality of elements formed in a region sandwiched between adjacent high defect regions 10a. That is, the current flowing through the SBD is the sum of the currents flowing through the respective elements that form the SBD.

  Next, in order to turn off the Schottky barrier diode 1, a relatively negative voltage is applied to the electrode 15 on the anode electrode side, and a relatively positive voltage is applied to the ohmic electrode 18 on the cathode electrode side. Then, a reverse bias is applied to the Schottky barrier diode 1. Since the first insulating layer 13 is formed on the high defect region 10a, the leakage current can be suppressed and the breakdown voltage of the SBD can be improved. Moreover, since the SBD has an FP structure, the breakdown voltage can be further improved.

  In the present embodiment, the thickness H13 of the first insulating layer 13 covering the high defect region 10a is larger than the thickness H14 of the second insulating layer 14 forming the FP structure. Thereby, the withstand voltage of the first insulating layer 13 itself can be improved, and the optimum structure as the FP insulating layer of the second insulating layer 14 can be realized, so that the withstand voltage can be improved based on the electric field relaxation by the FP structure. That is, it is possible to achieve both the necessary characteristics of the first insulating layer 13 covering the high defect region 10a and the necessary characteristics of the second insulating layer 14 that constitutes the optimum structure as the FP insulating layer. Therefore, while obtaining the breakdown voltage improvement effect by the FP structure in the second insulating layer 14, the breakdown voltage when the electric field is applied in the first insulating layer 13 on the high defect region 10a is maintained, and the leakage current is reduced. Occurrence can be suppressed. Therefore, an SBD with improved breakdown voltage can be realized.

  Further, when the first insulating layer 13 includes a material having a dielectric constant smaller than that of the material constituting the second insulating layer 14, the MIS capacitance component of the first insulating layer 13 is reduced. Can be reduced. For this reason, it is possible to improve the switching speed, which is the time until the change from the on state to the off state and the time until the change from the off state to the on state.

(Embodiment 2)
With reference to FIG. 17, an SBD which is an example of a semiconductor device in this embodiment will be described. The SBD in the present embodiment is different from 1a of the first embodiment shown in FIG. 2 in that the configuration of the region indicated by 1a in FIG. 1 or 3 is 1b shown in FIG.

  Specifically, as shown in FIG. 17, the first insulating layer 13 includes a lower first insulating layer 13a and an upper first insulating layer 13b formed on the lower first insulating layer 13a. Have. The lower first insulating layer 13a and the upper first insulating layer 13b may be made of different materials or the same material. At least one of the lower or upper first insulating layers 13 a and 13 b preferably has a dielectric constant smaller than that of the material constituting the second insulating layer 14. The first insulating layer 13 may be three or more layers.

  Next, with reference to FIGS. 17 to 27, a method for manufacturing the SBD in the present embodiment will be described.

  First, as shown in FIG. 18, as in the first embodiment, the GaN substrate 11 is prepared as shown in FIG. 5 (step S1), and the epitaxial layer 12 is formed as shown in FIG. 6 (step S2). ).

Next, as in Embodiment 1, an insulating layer 21 is formed as shown in FIG. The insulating layer 21 is preferably made of silicon dioxide (SiO ₂ ) or a so-called low-k material having a low relative dielectric constant.

  Next, as shown in FIG. 19, a mask layer such as a resist having a pattern in which a region (a region other than a region to be the first insulating layer 13) formed on the low defect region 10 b in the insulating layer 21 is opened. 23 is formed. After that, as shown in FIG. 20, the region formed on the low defect region 10b in the insulating layer 21 (the region exposed from the opening pattern of the mask layer 23 in the insulating layer 21) is removed. Next, as shown in FIG. 21, the mask layer 23 is removed. Thereby, the lower first insulating layer 13a can be formed (step S7). Formation and removal of the mask layer 23 are the same as those of the mask layer 23 of the first embodiment, and therefore description thereof will not be repeated.

  Next, as shown in FIG. 22, an insulating layer 26 is formed so as to cover main surface 12a of epitaxial layer 12 and lower first insulating layer 13a.

  Next, as shown in FIG. 23, the ohmic electrode 18 is formed on the back surface 11b of the GaN substrate 11 as in the first embodiment (step S3).

  Next, as shown in FIG. 24, a mask layer 27 such as a resist having an opening in a region where the Schottky electrode 16 is to be formed (a region where the Schottky electrode 16 is to be opened) is formed. Thereafter, as shown in FIG. 25, the region opened from the mask layer 27 in the insulating layer 26 is removed. Next, as shown in FIG. 26, the mask layer 27 is removed. Thereby, the upper first insulating layer 13b and the second insulating layer 14 can be formed (step S8). Since formation and removal of mask layer 27 are the same as those of mask layer 23 of the first embodiment, description thereof will not be repeated.

  In the present embodiment, step S8 for forming the second insulating layer 14 is performed simultaneously with the step for forming the upper first insulating layer 13b. By steps S7 and S8, the first insulating layer 13 having the lower first insulating layer 13a and the upper first insulating layer 13b and the second insulating layer 14 can be formed (steps S4 and S5). ).

  Next, as shown in FIG. 27, a mask layer 28 such as a resist having an opening in a region where the electrode 15 is to be formed is formed. Thereafter, the electrode 25 is formed as in the first embodiment. Next, the mask layer 28 is removed. Thus, as shown in FIG. 17, the Schottky electrode 16 that contacts the main surface 12a of the epitaxial layer 12 inside the opening of the second insulating layer 14 is connected to the Schottky electrode 16 and the first insulation is formed. An electrode 15 having an FP electrode 17 formed in a portion overlapping the layer 14 can be formed (step S6). Since mask layer 28 is similar to mask layer 24 of the first embodiment, description thereof will not be repeated.

  The SBD shown in FIG. 17 can be manufactured by performing the above steps (steps S1 to S8).

  In the SBD manufacturing method according to the present embodiment, step S5 for forming the second insulating layer 14 is performed simultaneously with step S8 for forming the upper first insulating layer 13b. You may perform simultaneously with step S7 to form.

  According to the SBD in the present embodiment, the first insulating layer 13 including a material having a dielectric constant smaller than that of the material constituting the second insulating layer 14 can be easily formed. Since the MIS (Metal-Insulator-Semiconductor) capacitance is proportional to the dielectric constant, the MIS capacitance component of the first insulating layer 13 can be reduced. Thereby, the response characteristic of SBD can be improved.

(Embodiment 3)
With reference to FIG. 28, an SBD which is an example of a semiconductor device in the present embodiment will be described. The SBD in the present embodiment is the same as the region 1a shown in FIG. 1 or FIG. 3 in that the configuration of the region 1c shown in FIG. 28 is 1a shown in FIG. 2 and the embodiment 2 shown in FIG. 1b.

  Specifically, the SBD shown in FIG. 28 has the same configuration as the SBD of the second embodiment shown in FIG. 17, but the upper first insulating layer 13b of the first insulating layer 13 It differs from the SBD in the second embodiment in that it covers the entire insulating layer 13a.

  The manufacturing method of the SBD in the present embodiment basically has the same configuration as the SBD of the second embodiment. However, in the method of forming the upper first insulating layer 13b, the SBD of the second embodiment is formed. It is different from the manufacturing method.

  Specifically, when the mask layer 27 shown in FIG. 24 is formed, the mask layer 27 is formed so as to cover the entire lower first insulating layer 13a. Thereafter, by removing the region opened from the mask layer 27 in the insulating layer 26, the upper first insulating layer 13b shown in FIG. 28 can be formed.

  According to the SBD in the present embodiment, the upper first insulating layer 13b covers the lower first insulating layer 13a. Therefore, end region R2 in contact with first insulating layer 13 in epitaxial layer 12 shown in FIG. 28 is under conditions suitable for the FP structure as compared with region R1 of SBD of the second embodiment shown in FIG. Therefore, the electric field concentration can be reduced. Therefore, the SBD in this embodiment can further improve the breakdown voltage.

(Embodiment 4)
The configuration of the semiconductor device in the present embodiment is the same as that in the first embodiment, but differs in the manufacturing method. Hereinafter, a method for manufacturing an SBD which is an example of the semiconductor device in the present embodiment will be described.

  First, as in the first embodiment, the GaN substrate 11 is prepared as shown in FIG. 5 (step S1), and the epitaxial layer 12 is formed as shown in FIG. 6 (step S2). Next, as in the first embodiment, an insulating layer 21 is formed as shown in FIG. Since these steps are the same as in the first embodiment, description thereof will not be repeated.

  Next, as shown in FIG. 19, a mask layer such as a resist having a pattern in which a region (a region other than a region to be the first insulating layer 13) formed on the low defect region 10 b in the insulating layer 21 is opened. 23 is formed. After that, as shown in FIG. 20, the region formed on the low defect region 10b in the insulating layer 21 (the region exposed from the opening pattern of the mask layer 23 in the insulating layer 21) is removed. Next, as shown in FIG. 21, the mask layer 23 is removed. Thereby, the first insulating layer 13 can be formed. Next, as shown in FIG. 22, an insulating layer 26 is formed so as to cover main surface 12 a of epitaxial layer 12 and first insulating layer 13. Since these steps are the same as those in the second embodiment, description thereof will not be repeated. 20 to 22, the lower first insulating layer 13a corresponds to the first insulating layer 13 in the present embodiment.

  Next, as shown in FIG. 23, the ohmic electrode 18 is formed on the back surface 11b of the GaN substrate 11 as in the first embodiment (step S3).

  Next, as shown in FIG. 29, a mask layer 29 such as a resist is formed on the region where the second insulating layer 14 is to be formed. Thereafter, as shown in FIG. 30, the region opened from the mask layer 29 in the insulating layer 26 is removed. Next, as shown in FIG. 31, the mask layer 29 is removed. Thereby, the second insulating layer 14 can be formed. Formation and removal of the mask layer 29 are the same as those of the mask layer 23 of the first embodiment, and therefore description thereof will not be repeated.

  Next, as shown in FIG. 15, a mask layer 24 having an opening in a region where the electrode 15 is to be formed is formed. Thereafter, as shown in FIG. 16, an electrode 25 is formed. Next, the mask layer 24 is removed. Thus, the Schottky electrode 16 that is in contact with the main surface 12a of the epitaxial layer 12 inside the opening of the second insulating layer 14 and the portion that is connected to the Schottky electrode 16 and overlaps the first insulating layer 14 are formed. The electrode 15 having the FP electrode 17 thus formed can be formed. Since these steps are the same as those in the first embodiment, description thereof will not be repeated.

  The SBD shown in FIG. 2 can be manufactured by performing the above steps. According to this embodiment, since the first insulating layer 13 and the second insulating layer 14 are formed in separate steps, the thickness of the first and second insulating layers 13 and 14 can be easily adjusted. Yes. Further, when the material of the first insulating layer 13 and the material of the second insulating layer 14 are different, the dielectric constant is smaller than the dielectric constant of the material in which the first insulating layer 13 constitutes the second insulating layer 14. Can be easily formed.

  Here, in the first to fourth embodiments, the SBD is described as an example of the semiconductor device. However, the semiconductor device of the present invention is not limited to the SBD, and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), The present invention can also be applied to JFETs (Junction Field-Effect Transistors), pn diodes, IGBTs (Insulated Gate Bipolar Transistors), and the like.

  Although the embodiments of the present invention have been described as described above, it is also planned from the beginning to combine the features of each embodiment as appropriate. In addition, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

  1 Schottky barrier diode (SBD), 10 GaN layer, 10a high defect region, 10b low defect region, 10c, 11a, 12a main surface, 10d, 11b, 12b back surface, 11 GaN substrate, 12 epitaxial layer, 13 first Insulating layer, 13a Lower first insulating layer, 13b Upper first insulating layer, 14 Second insulating layer, 15, 25 electrode, 16 Schottky electrode, 17 FP electrode, 18 Ohmic electrode, 21, 26 insulating layer, 22, 23, 24, 27, 28, 29 Mask layers.

Claims (6)

A gallium nitride layer including a high defect region, a low defect region having a defect density lower than that of the high defect region, and having a main surface and a back surface opposite to the main surface;
A first insulating layer formed to cover the high defect region on the main surface of the gallium nitride layer;
A second insulating layer formed on the low-defect region on the main surface of the gallium nitride layer and having an opening;
An electrode layer formed in the opening to be in contact with the main surface of the gallium nitride layer;
A feed plate electrode connected to the electrode layer and formed to overlap the second insulating layer;
The thickness of the said 1st insulating layer is a semiconductor device larger than the thickness of the said 2nd insulating layer.   The semiconductor device according to claim 1, wherein the first insulating layer includes a material having a dielectric constant smaller than a dielectric constant of a material constituting the second insulating layer. Preparing a gallium nitride layer including a high defect region and a low defect region having a defect density lower than that of the high defect region, and having a main surface and a back surface opposite to the main surface;
Forming a first insulating layer so as to cover the high defect region on the main surface of the gallium nitride layer;
Forming a second insulating layer having an opening on the low-defect region on the main surface of the gallium nitride layer;
Forming an electrode layer in the opening so as to contact the main surface of the gallium nitride layer;
Connecting to the electrode layer and forming a field plate electrode so as to overlap the second insulating layer,
The method of manufacturing a semiconductor device, wherein, in the step of forming the second insulating layer, the second insulating layer having a thickness smaller than that of the first insulating layer is formed. The step of forming the first insulating layer and the step of forming the second insulating layer include:
Forming an insulating layer so as to cover the main surface of the gallium nitride layer;
Removing a portion of the insulating layer to reduce the thickness of the region formed on the low-defect region in the insulating layer;
The method for manufacturing a semiconductor device according to claim 3, further comprising: forming an opening in the insulating layer formed on the low defect region. The step of forming the first insulating layer includes a step of forming a lower first insulating layer so as to cover the high defect region on the main surface of the gallium nitride layer, and a step of forming the first insulating layer on the lower first insulating layer. Forming an upper first insulating layer,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the second insulating layer is performed simultaneously with the step of forming the lower first insulating layer or the step of forming the upper first insulating layer. .   The step of forming the first insulating layer forms the first insulating layer containing a material having a dielectric constant smaller than that of the material constituting the second insulating layer. The method for manufacturing a semiconductor device according to any one of the above.

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