JP2011060199A - Image signal processing apparatus, image signal processing system, and interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image signal processing apparatus compatible with the kinds and the number of interface circuits, which are different in accordance with an external device with a common hardware configuration. <P>SOLUTION: A sub-board 150 has an engine IF 156 for converting an image signal from a main board 110 in accordance with a physical layer specification of a print engine of a connection destination. The sub-board 150 is prepared by kind of a print engine, and is combined with a common main board 110 to be used. In an FPGA 120 of the main board 110, a sub-board IF 126 for converting, for example, a control protocol other than the physical layer specification in accordance with a print engine is formed as well as a common image processing circuit 124. A flash memory 116 stores circuit configuration data of the sub-board IF 126 by kind of the sub-board 150 (accordingly, a print engine), and the sub-board IF 126 is configured according to circuit configuration data corresponding to a sub-board kind set in a dip switch 119. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image signal processing device, an image signal processing system, and an interface circuit.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for increasing design freedom by separating a board in a computer into a main board and a sub board.

  Patent Document 2 discloses a configuration in which an expansion box is connected to a built-in card such as a PCI (Peripheral Component Interconnect) card so that the graphic card built in the computer has expandability.

  Patent Document 3 discloses a configuration in which a graphic card is separated into a signal generation board and a signal output board. In this configuration, by preparing a plurality of signal output boards with different external interface connectors to be mounted and replacing the signal output boards attached to the signal generation boards, it is possible to cope with external devices with different connectors.

JP 2007-103508 A Japanese Patent Laid-Open No. 11-175185 JP 2000-310989 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal processing apparatus that can cope with a different type or number of interface circuits depending on an external apparatus with a common hardware configuration.

  According to a first aspect of the present invention, there is provided a connection unit in which an interface circuit with an external device is detachably connected, an image signal to be supplied to the external device via the interface circuit, or from the external device via the interface circuit. A reconfigurable circuit that can be configured as an image processing circuit that processes a supplied image signal, corresponding to the type or number of the interface circuit connected to the connection unit, or a combination of the type and the number An image signal processing apparatus comprising: a reconfigurable circuit capable of configuring its own internal circuit into a circuit configuration.

  The invention according to claim 2 further includes acquisition means for acquiring a signal indicating a type of the interface circuit from the interface circuit connected to the connection unit, and the reconfigurable circuit is acquired by the acquisition means. 2. The image signal processing apparatus according to claim 1, wherein the internal circuit is configured to have a circuit configuration corresponding to a type corresponding to a signal.

  In the invention according to claim 3, when the reconfigurable circuit configures the internal circuit of the self, first, the circuit of the acquisition unit is configured in the internal circuit of the self, and the connection unit is connected to the connection unit. A first signal indicating the type of the interface circuit is acquired from the interface circuit via an image signal line that transmits the image signal to and from the interface circuit, and the acquisition unit circuit includes: The image signal processing apparatus according to claim 2, wherein the internal circuit is configured so as to have a circuit configuration corresponding to a type represented by the acquired first signal.

  According to a fourth aspect of the present invention, the acquisition unit circuit further acquires a second signal indicating the type of the external device via the interface circuit connected to the connection unit, and the reconfigurable circuit includes: The internal circuit is converted into a circuit configuration corresponding to a combination of the type of the interface circuit represented by the first signal acquired by the circuit of the acquisition unit and the type of external device represented by the second signal. The image signal processing apparatus according to claim 3, wherein the image signal processing apparatus is configured.

  The invention according to claim 5 is a storage device that stores a control program for controlling the external device for each type of the external device, and an execution circuit that executes the selected one of the control programs in the storage device The acquisition unit circuit selects and executes a control program corresponding to the type of external device represented by the second signal acquired via the interface circuit connected to the connection unit. The image signal processing apparatus according to claim 4, wherein the execution circuit is instructed as described above.

  The invention according to claim 6 further includes a number detection unit that detects the number of the interface circuits connected to the connection unit, wherein the reconfigurable circuit includes the number detected by the number detection unit, and the acquisition unit. 6. The image signal processing apparatus according to claim 2, wherein the internal circuit is configured into a circuit configuration corresponding to a combination of a type corresponding to the acquired signal and a combination thereof. is there.

  The invention according to claim 7 is provided with a number detection means for detecting the number of the interface circuits connected to the connection section, and the reconfigurable circuit has a circuit configuration corresponding to the number detected by the number detection means. The image signal processing apparatus according to claim 1, further comprising an internal circuit of the image signal processing apparatus.

  The invention according to claim 8 further includes a user designation receiving device that accepts a designation representing a type or number of interface circuits connected to the connection unit, or a combination of the type and the number from a user, and the reconfiguration 2. The image signal processing apparatus according to claim 1, wherein the possible circuit configures its own internal circuit into a circuit configuration corresponding to the designation received by the user designation receiving apparatus.

  The invention according to claim 9 further includes external device type acquisition means for further acquiring a signal representing the type of the external device via the interface circuit connected to the connection unit, and the reconfigurable circuit includes the reconfigurable circuit, To the circuit configuration corresponding to the combination of the type or number of the interface circuit connected to the connection unit, or a combination of the type and the number, and the type of the external device represented by the signal acquired by the external device type acquisition unit The image signal processing apparatus according to claim 1, wherein the image signal processing apparatus constitutes its own internal circuit.

  According to a tenth aspect of the present invention, there is provided a storage device that stores a control program for controlling the external device for each type of the external device, and an execution circuit that executes the selected one of the control programs in the storage device And acquiring the signal representing the type of the external device via the interface circuit connected to the connection unit, and selecting and executing a control program corresponding to the type of external device represented by the acquired signal The image signal processing apparatus according to claim 1, further comprising control means for controlling the circuit.

  According to an eleventh aspect of the present invention, there is provided a connecting portion to which an interface circuit with an external device is detachably connected, an image signal to be supplied to the external device via the interface circuit, or from the external device via the interface circuit. A reconfigurable circuit that can be configured as an image processing circuit that processes a supplied image signal, acquired a signal representing the type of the external device via the interface circuit connected to the connection unit, and acquired An image signal processing apparatus comprising: a reconfigurable circuit capable of configuring its own internal circuit into a circuit configuration corresponding to the type of external device represented by the signal.

  The invention according to claim 12 includes an image signal processing device and an image signal interface circuit provided between the image signal processing device and an external device, wherein the interface circuit is attached to and detached from the image signal processing device. A connection unit that can be freely connected and an image processing circuit that processes an image signal to be supplied to the external device via the interface circuit or an image signal supplied from the external device via the interface circuit. A reconfigurable circuit that can configure its own internal circuit to a circuit configuration corresponding to the type or number of the interface circuit connected to the connection unit, or a combination of the type and number. An image signal processing system comprising: a configurable circuit.

  The invention according to claim 13 transmits between an external device and a reconfigurable circuit that functions as an image processing circuit that processes an image signal to be supplied to the external device or an image signal supplied from the external device. A conversion circuit for converting to a signal format of the image signal to be generated, and a type of supplying a signal indicating its own type to the reconfigurable circuit in order to configure the reconfigurable circuit as the image processing circuit An interface circuit including a signal supply circuit.

  According to the first or twelfth aspect of the present invention, it is possible to provide an image signal processing apparatus that can cope with a different type or number of interface circuits depending on an external apparatus with a common hardware configuration.

  According to the second or thirteenth aspect of the present invention, a signal representing the type of interface circuit can be automatically acquired by the acquisition means.

  According to the third aspect of the invention, there is no need for a dedicated signal line for acquiring a signal representing the type of the interface circuit from the interface circuit.

  According to the invention of claim 4, the internal circuit of the reconfigurable circuit is further adapted to the type of each external device even when the same type of interface circuit is commonly used for a plurality of types of external devices. Can be configured.

  According to the fifth aspect of the present invention, the control program executed by the execution circuit of the image signal processing device can be switched according to the type of the external device.

  According to the sixth aspect of the invention, even if the number of interface circuits of the same type is changed to the number connected to the image signal processing device, it corresponds to the case where the circuit configuration on the image signal processing device side needs to be changed accordingly. be able to.

  According to the seventh aspect of the present invention, if the number of interface circuits of the same type is connected to the image signal processing device, the circuit configuration on the image signal processing device side needs to be changed accordingly. can do.

  According to the invention which concerns on Claim 8, the information of an interface circuit can be obtained according to the instruction | indication from a user.

  According to the ninth aspect of the present invention, even when the same type of interface circuit is commonly used for a plurality of types of external devices, the internal circuit of the reconfigurable circuit is configured in accordance with the type of each external device. be able to.

  According to the tenth aspect of the present invention, the control program executed by the execution circuit of the image signal processing device can be switched according to the type of the external device.

  According to the eleventh aspect of the present invention, it is possible to provide an image signal processing apparatus capable of handling different types of external apparatuses with a common hardware configuration.

1 is a diagram illustrating an example of a system including an image processing controller to which an apparatus according to an embodiment is connected. It is a figure which shows the example of the external appearance of the engine interface apparatus of embodiment. It is a figure which shows the example of the hardware constitutions of the engine interface apparatus of embodiment. 4 is a flowchart showing an example of a procedure of processing executed by the apparatus of FIG. 3 in an initialization phase. It is a figure which shows the 2nd example of the hardware constitutions of the engine interface apparatus of embodiment. 6 is a flowchart illustrating an example of a procedure of processing executed by the apparatus of FIG. 5 in an initialization phase. It is a figure which shows the 3rd example of the hardware constitutions of the engine interface apparatus of embodiment. It is a flowchart which shows the example of the procedure of the process which the apparatus of FIG. 7 performs in the initialization phase.

  First, an example of a printing system including an image processing controller 10 to which an engine interface device, which is an embodiment of an image signal supply device according to the present invention, can be connected will be described with reference to FIG.

  In this example, the image processing controller 10 is a computer that controls the print engine 20. The print engine 20 prints an image on a sheet in accordance with an image data (video) signal supplied from the image processing controller 10. The image processing controller 10 receives print data described in PDL (page description language) from a client PC (personal computer) 40 via a network 30 such as a local area network. Then, the print data is interpreted, converted into an image data signal that can be handled by the print engine 20, and supplied to the print engine 20. The image processing controller 10 communicates with the print engine 20 to control the print engine 20 and sequentially supply image data signals to the print engine 20.

  The image processing controller 10 is configured based on a computer such as a PC or a workstation, for example. The image processing controller 10 includes various programs such as a job management program that manages the print execution order for print data (print jobs) received from each client PC 40, and an interpreter program that interprets the print data and converts it into image data. Is installed. The CPU (central processing unit) of the PC or workstation that is the base of the image processing controller 10 executes these programs, thereby executing processing according to these programs.

  Among the various types of processing executed by the image processing controller 10, there are those that are more suitable for mounting as hardware circuits. For example, image processing such as color space conversion, enlargement / reduction, and rotation of an image is processing for a hardware circuit. A circuit that executes processing for such a hardware circuit is mounted on an expansion board compliant with an expansion board standard such as PCIe (Peripheral Component Interconnect express) and is mounted in an expansion slot on the motherboard of the image processing controller 10. It has been done conventionally. In addition, the external output connector of the expansion board and the print engine 20 are connected by a cable, and the image data signal processed by the image processing circuit on the expansion board is supplied to the print engine 20 through the cable. ing.

  In such a configuration, the signal transmission path such as the bit width (number of signal lines) of the cable connecting the external output connector of the expansion board and the print engine 20, the signal level (voltage) in these signal lines, the shape of the cable connector, etc. The physical layer specifications may differ depending on the type (model) of the print engine 20. For this reason, an engine IF (interface) circuit is provided between the image processing circuit on the expansion board and the external output connector to match the specifications of the physical layer with the print engine 20. Conventionally, it has been common to design an entire expansion board including an engine IF circuit according to the type of print engine 20 to be connected.

  However, in many cases, the processing performed by the image processing circuit on the expansion board does not depend on the type of the print engine 20. Therefore, the expansion board is a board (referred to as a “main board”) on which a circuit that executes a common process independent of the print engine 20 (referred to as a “main board”) and a board (such as an engine IF circuit that depends on the print engine 20) ( It can be considered that the design is divided into “sub-substrate”. In this embodiment, such a common main board and a sub board corresponding to the type of the print engine 20 are used in combination.

  FIG. 2 shows an example of the appearance of the engine interface device of this embodiment configured by combining a main board and a sub board. In this example, the main board 110 is a board compliant with, for example, the PCI or PCIe standard, and is an FPGA (Field Programmable) that can be configured as various circuits such as a CPU 112 that controls each circuit on the main board 110 and an image processing circuit. A circuit chip group such as (Gate Array) (not shown) is mounted. The image processing circuit configured on the FPGA is a circuit that executes common image processing for a plurality of types of print engines 20 that are assumed to be connected to the image processing controller 10. The main board 110 is provided with a PCI or PCIe standard connector, and this connector is connected to a PCI or PCIe slot on the motherboard of the image processing controller 10.

  One print engine 20 is connected to the sub-boards 150-1 and 150-2 via cables connected to the external output connectors 160-1 and 160-2. That is, this example is an example in which the print engine 20 is of a type that receives an image data signal via two cables. In each of the sub-boards 150-1 and 150-2, an engine IF circuit (not shown) that interfaces with the print engine 20 in the physical layer of the image data signal, and other unique to the connection destination print engine 20 are provided. A circuit for executing signal processing is mounted. The external output connectors 160-1 and 160-2 are provided on the sub-boards 150-1 and 150-2.

  In this example, the main board 110 and the sub board 150-1 are connected via a control signal line 172-1 and an image data signal line 174-1. The main board 110 and the sub board 150-2 are connected via a control signal line 172-2 and an image data signal line 174-2.

  In this example, the sub board 150-1 is fixed to the main board 110 by screwing or the like. A board in which the sub board 150-1 is fixed to the main board 110 fits in one slot of the PCI or PCIe standard (that is, does not interfere with a board inserted in an adjacent slot). In other words, the sub-board 150-1 is designed to have a size that does not interfere with adjacent slots when fixed to the main board 110.

  On the other hand, a fixing jig 151 is attached to the sub board 150-2, and the sub board 150-2 is fixed to the mother board by inserting the fixing jig into an empty slot on the mother board of the image processing controller 10. To do. Neither the sub board 150-1 nor 150-2 is electrically connected to the motherboard, and various signals are acquired from the main board 110.

  If the print engine 20 is of a type that can be connected to the image processing controller 10 with a single cable, only the sub-board 150-1 is sufficient. If the print engine 20 is of a type that is connected to the image processing controller 10 with three cables, in addition to the sub boards 150-1 and 150-2, another sub board is used. As described above, the sub-board 150 may be used in a number corresponding to the number of cables connecting the print engine 20 and the image processing controller 10.

  However, this is only an example. Instead of this, it is conceivable that a plurality of external output connectors and engine IF circuits are provided on one sub-board 150, and only one sub-board 150 is required for the print engine 20 that needs to be connected by a plurality of cables.

  As described above, in the system in which the engine interface device is configured by the combination of the main board 110 and the sub board 150, the interface of the physical layer of the signal with the print engine 20 is secured by the engine IF circuit on the sub board 150. The However, it is not only the physical layer specifications that differ depending on the type of print engine 20. For example, printing speed, number of colors (monochrome, CMYK 4 colors, 5 colors, 6 colors), printing method (4-cycle method, tandem method), number of exposure beams (dual beam, single beam), paper type (cut paper, continuous paper) The control system specifications such as “book” are also different. Due to the difference in specifications, the specifications of the image data signal such as the format of the image data, the number of colors, the transfer speed, the specification of the handshake signal for control, the status signal unique to the print engine, etc. Different for each. Therefore, it is necessary to perform an interface process for matching the specifications of the image data signal with the type of the connected print engine 20. In this embodiment, this interface processing is performed by an IF circuit (sub-board IF 126 described later) configured on the FPGA on the main board 110.

  Next, an example of the hardware configuration of the engine interface device 100 of this embodiment will be described with reference to FIG. In this example, the engine interface device 10 is configured by the main board 110 and one sub board 150, and the main board 110 is compliant with the PCIe standard.

  First, the sub substrate 150 will be described. The sub board 150 includes an engine IF (interface circuit) 156 that interfaces the physical layer specifications of the control signal and the image data signal supplied from the main board 110 in accordance with the control circuit 200 of the print engine 20 to be connected. . For example, the engine IF 156 adapts the signal input from the main board 110 side to the bit width (number of signal lines) of the signal cable for connection with the print engine 20 and the signal level in the signal line of these cables. Convert as follows. The former is realized by circuits such as parallel / serial conversion, parallel / parallel conversion, and serial / parallel conversion. The latter is realized by an impedance conversion circuit. Note that the conversion of the bit width and signal level of the signal cable may be performed for each of the control and image data signals.

  In addition to the physical layer interface circuit exemplified above, the engine IF 156 includes processing specific to the print engine 20 that is not executed by the FPGA 120 on the main board 110 (for example, a control signal is transmitted to the print engine). A circuit for processing to convert to a specific one or a specific image processing) may be incorporated.

  In the figure, the engine IF 156 is drawn as one block, but the engine IF 156 may be composed of a plurality of circuit chips and circuit elements.

  The engine IF 156 converts a control signal (for example, a command for the print engine 20) received from the CPU 112 of the main board 110 via the control signal line 172 and the connection unit 152 according to the physical layer specification of the print engine 20. Then, the converted signal is supplied to the control circuit 200 of the print engine 20 via the control signal line 182 connected to the connection unit 162. Conversely, a signal sent from the control circuit 200 of the print engine 20 via the control signal line 182 (for example, a signal indicating the state of the print engine 20 or a signal indicating a response to the command) is sent to the connection unit 162. The signal is converted in accordance with the physical layer specification on the main board 110 side, and transmitted to the main board 110 side via the connection unit 152 and the control signal line 172.

  The engine IF 156 converts the image data signal received from the FPGA 120 of the main board 110 via the image data signal line 174 and the connection unit 154 in accordance with the physical layer specification of the print engine 20, and connects the converted signal to the connection. This is supplied to the control circuit 200 of the print engine 20 via the image data signal line 184 connected to the unit 164.

  As described above, the engine IF 156 absorbs differences in physical layer specifications such as the bit width and signal level of the signal line (cable) between the print engine 20 and the main board 110 and the sub board 150. The physical layer specifications of the control signal line 172 and the image data signal line 174 may be fixed (common to all types of the print engine 20).

  Note that the connection portions 162 and 164 for signal connection with the print engine 20 are included in the external output connector 160 (160-1 or 160-2) illustrated in FIG. The connector shape and signal line arrangement of the external output connector 160 are adapted to the type of the print engine 20 to be connected. That is, the sub-board 150 absorbs the difference in the connection connector that is part of the physical layer specification between the main board 110 and the print engine 20 by the external output connector 160.

  As the sub-board 150, a plurality of types having different engine IF 156 and / or external output connector shapes are prepared, and a user or a service engineer selects one that matches the connection destination print engine 20, Combined with the substrate 110.

  Next, the main substrate 110 will be described. On the main board 110, a CPU 112, a RAM (Random Access Memory) 114, a flash memory 116, a page memory 118, an FPGA 120, a DIP switch (DIP-SW) 119, and connection units 132 and 134 are mounted. Among these, the CPU 112, the RAM 114, the flash memory 116, and the FPGA 120 are connected to a bus 130 provided on the main board 110.

  The CPU 112 is an arithmetic device that executes arithmetic processing for controlling the engine interface device 100, and the RAM 114 is used as a working memory for the arithmetic processing. The CPU 112 transmits a control signal representing a control command or the like generated as a result of the arithmetic processing to the sub board 150 via the connection unit 132 and the control signal line 172. In addition, a response and other control signals sent from the sub-board 150 side via the control signal line 172 are received via the connection unit 132, and arithmetic processing for control is advanced using the received control signal.

  The flash memory 116 stores an engine control program executed by the CPU 112 and FPGA data representing a circuit configuration to be configured in the FPGA 120. Here, the engine control program is a program representing processing for controlling the print engine 20. This program defines, for example, communication processing with the print engine 20 and what kind of command is sent to the print engine 20 when.

  The flash memory 116 stores FPGA data representing the circuit configuration of a common PCIe-IF (interface circuit) 122 and image processing circuit 124 that does not depend on the type of the print engine 20, and the type of the sub-board 150 (as a result). FPGA data defining the circuit configuration of a different sub board IF (interface circuit) 126 is stored for each of the connection destination print engines 20 (corresponding to the type). Note that the sub circuit board IF 126 having the same circuit configuration may correspond to a plurality of types of sub circuit boards IF 126.

  Note that the storage device for storing such a control program and FPGA data is not limited to the illustrated flash memory 116. Instead of the flash memory 116, other types of nonvolatile storage devices such as a ROM (Read Only Memory) and a hard disk may be used. When a rewritable storage device such as the flash memory 116 is used, when a new type of print engine 20 or sub board 150 appears, the circuit configuration data of the corresponding sub board IF 126 may be added. Conceivable.

  The page memory 118 is a memory that stores one page of image data to be processed by the image processing circuit 124 configured in the FPGA 120, and is configured as a RAM, for example. The image data for one page supplied from the motherboard 12 side is stored in the page memory 118 via the image processing circuit 124, and the image processing circuit 124 executes image processing with reference to the page memory 118 as necessary. To do. In addition, instead of the page memory 118 for storing page-unit image data, a memory for storing other units of image data, such as a memory for storing band-unit image data obtained by dividing a page by a predetermined number of lines. May be used.

  The FPGA 120 is a type of circuit whose internal circuit configuration can be changed. In this example, the FPGA 120 configures its own internal circuit in accordance with FPGA data (stored in the flash memory 116) instructed by the CPU 112. In the illustrated example, the FPGA 120 configures a PCIe-IF 122, an image processing circuit 124, and a sub board IF 126 within itself.

  Of these, the PCIe-IF 122 is a circuit that performs communication interface processing compliant with the PCIe standard. The PCI-IF 122 is connected to a PCIe connector (not shown), and the connector is inserted into the PCIe slot 14 of the motherboard 12 of the image processing controller 10. Via this PCIe connection, the CPU and other circuits on the motherboard 12 and the CPU 112 and other circuits on the main board 110 communicate with each other.

  The image processing circuit 124 performs predetermined image processing on image data supplied from the motherboard 12 via the PCIe slot 14. Image processing performed by the image processing circuit 124 includes color space conversion, enlargement / reduction, and rotation of the image. The image processing circuit 124 includes element circuits for performing such various processes. When the image data supplied from the mother board 12 is compressed data, an expansion processing circuit that expands the compressed data and restores the original image data may be incorporated in the image processing circuit 124. FPGA data representing the configuration of such various element circuits and the connection relationship between these element circuits is stored in the flash memory 116 as data defining the circuit configuration of the image processing circuit 124.

  Of the circuits configured in the FPGA 120 illustrated in FIG. 3, the PCIe-IF 122 and the image processing circuit 124 are common circuits that do not depend on the type of the print engine 20 connected via the sub-board 150. However, other common circuits may be configured in the FPGA 120. In this case, the configuration data of the other common circuit is stored in the flash memory 116.

  When a circuit for interface processing conforming to the PCIe standard is provided separately from the FPGA 120, the PCIe-IF 122 does not have to be configured in the FPGA 120.

  In addition to such a common circuit, the FPGA 120 is configured with a different sub board IF 126 for each type of the sub board 150 (and thus the print engine 20 to which it is connected). The sub-board IF 126 changes the image data signal from the one that conforms to the specification inside the main board 110 to the specification of the sub-board 150 (and thus the control circuit 200 of the print engine 20) regarding the specifications other than the physical layer specification of the image data signal. Convert to a suitable one. Specifications other than the physical layer specification of the image data signal include the format of the image data signal, the number of colors, the transfer speed, the specification of the handshake signal for control, the status signal unique to the print engine, and the like. For example, the format of the image data signal includes, for example, whether or not a signal indicating a page break is included in the image data signal and whether or not a signal indicating a line break is included. The number of colors of the image data signal includes, for example, four colors of monochrome and CMYK, five colors obtained by adding an intermediate color to CMYK, and six colors.

  The sub-board IF 126 includes one or more circuit elements for such a command or signal interface. Such a circuit element is constituted by FPGA data.

  The sub board IF 126 is connected to the connection part 134. The connection unit 134 is connected to the connection unit 154 of the sub-board 150 via the image data signal line 174. The image data signal output from the sub board IF 126 is transmitted to the sub board 150 side via the connection unit 134 and the image data signal line 174.

  In order to configure the sub board IF 126 suitable for the type of the sub board 150 (and hence the type of the print engine 20), the main board 110 is provided with a DIP switch (DIP-SW) 119. The dip switch 119 is provided with a plurality of on / off switches, and the combinations of the on / off states of the on / off switches are codes indicating the types of the different sub-boards 150, respectively. That is, data indicating the circuit configuration of each sub-board IF 126 is registered in the flash memory 116 in association with the code indicated by the combination of the on / off states of the dip switch 119.

  For example, when the main board 110 and the sub board 150 are attached to the image processing controller 10, the user or service engineer sets each on / off switch of the dip switch 119 according to the type of the sub board 150. Then, in an initialization phase such as when the image processing controller 10 is activated, for example, the CPU 112 of the main board 110 reads the switch setting state (on / off combination) of the dip switch 119 as shown in FIG. 4 (S10). Next, the CPU 112 reads data indicating the circuit configuration of the sub-board IF corresponding to the code indicated by the switch setting state and data indicating a common circuit configuration such as the image processing circuit 124 from the flash memory 116 (S12). Then, the CPU 112 configures the inside of the FPGA 120 as illustrated in FIG. 3 by writing the read circuit configuration data (FPGA data) into the FPGA 120 (S14). When the initialization is completed in this way, the CPU 112 shifts to an image transmission phase, and executes a control program corresponding to this phase to control the print engine 20 to execute printing.

  Note that the device for setting the type of the connected sub-board 150 is not limited to the DIP switch 119. Further, the image processing circuit 124 may be partially customized according to the type of the sub-board 150 (and thus the print engine 20). For example, in the print engine 20 connected to a certain sub-board 150, when a certain kind of special image processing is required, a circuit for the image processing is incorporated in FPGA data so that the circuit is configured. And so on.

  In the above example, the program representing the initialization process illustrated in FIG. 4 is also stored in the flash memory 116.

  In FIG. 3, only one pair of the control signal connection portion 132 and the image data signal connection portion 134 is shown on the main board 110. However, in order to cope with the print engine 20 that requires connection with a plurality of cables. A plurality of such connection portion pairs may be provided on the main substrate 110.

  In the above, the circuit configuration of the sub-substrate IF 126 of the FPGA 120 is changed according to the type of the sub-substrate 150 connected to the main substrate 110. However, this circuit configuration may be performed according to the number of sub-substrates 150 to be connected. . For example, consider a case where the function of the print engine 20 changes depending on the number of cables connecting the image processing controller 10 and the print engine 20 (for example, the printing speed increases as the number increases). In this case, the types of sub-boards 150 connected to the main board 110 are the same, but the number to be connected varies depending on the system configuration on the user side. Since the function provided by the print engine 20 changes according to the number of connected sub-boards 150, the circuit configuration of the sub-board IF 126 of the main board 110 is also changed according to the provided function of the print engine 20. For this purpose, for the types of sub-boards 126 that can be connected to the main board 110 differently, the FPGA data of the circuit configuration of the different sub-board IF 126 is registered in the flash memory 116 for each connected number. Then, for example, the type and number of sub-boards 150 to be connected can be set by a device such as a dip switch 119, and the CPU 112 may read the FPGA data corresponding to the setting from the flash memory 116 and write it into the FPGA 120.

  Note that, as an example, the main board 110 may correspond to only a single type of sub board 150, but the number of connectable sub boards 150 includes a plurality of variations. In this case, the data of the circuit configuration of the different sub board IF 126 may be registered in the flash memory 116 for each number of the sub boards 150, and the number may be set in the setting device such as the dip switch 119.

  Even if the print engine 20 requires a plurality of sub-boards 150, if the number of sub-boards 150 to be used is fixed, the FPGA data may be specified only from the type of the sub-board 150.

  Next, another configuration example of the engine interface device 100 is shown with reference to FIG. In FIG. 5, the same elements as those shown in FIG.

  In the example of FIG. 3, the type (and / or number) of sub-boards 150 connected to the main board 110 is set in advance by the setting device such as the DIP switch 119 on the main board 110 on the user side. On the other hand, in the example of FIG. 5, the main board 110 side automatically acquires (determines) the type of the connected sub board 150.

  In other words, in the example of FIG. 5, a type notification unit 157 that is a circuit that notifies a signal or information indicating the type of the sub-board 150 (referred to as a “sub-board signal”) is provided on the sub-board 156. Then, a control signal line 176 for transmitting the sub board signal from the type notifying unit 157 to the CPU 112 of the main board 110 is provided. The control signal line 176 connects the CPU 112 and the type notification unit 157 via the connection unit 132 on the main board 110 side and the connection unit 152 on the sub board 150 side. When the power is turned on, the type notifying unit 157 of the sub board 150 outputs a preset sub board signal (representing the type of the sub board 150) to the control signal line 176. In an initialization process performed when the power is turned on, the CPU 112 first executes a process (acquisition unit 113) for acquiring a sub-board signal transmitted via the signal line 176. A program for processing of the acquisition unit 113 is read from the flash memory 116 and executed. The sub board signal acquired by the acquisition unit 113 by this processing corresponds to the setting content of the dip switch 119 in the example of FIG. The CPU 112 executes a process similar to steps S12 and S14 in FIG. 4 according to the sub-board signal acquired in this way, thereby configuring a circuit suitable for the sub-board 150 in the FPGA 120.

  A case where the same type of sub-board 150 corresponds to a plurality of different types of print engines 20 is also conceivable. For example, even if the upper layer specifications such as the control command or the image data format are different, the same type of sub-board 150 can be used if the physical layer of the signal is common. In such a case, the circuit configuration of the FPGA 120 cannot be determined only by the type of the connected sub-board 150, and needs to be determined in consideration of the type of the connected print engine 20. For example, when a plurality of types of print engines 20 having different colors can be connected to one sub-board 150, the FPGA 120 may generate any number of color image data signals if the type of the print engine 20 is not known. I do not know.

  Therefore, as a further example, an example will be described in which the circuit configuration of the FPGA 120 is determined not only for the type of the sub-board 150 but also for the type of the print engine 20. Here, a description will be given by taking the apparatus configuration of FIG. 5 as an example.

  In this example, the flash memory 116 includes, for each combination of the type of the sub-board 150 (and the number if the circuit varies depending on the number) and the type of the print engine 20, the sub-board IF 126 corresponding to the combination. FPGA data representing the circuit configuration is registered.

  The acquisition unit 113 executed by the CPU 112 during the initialization process acquires the sub board signal from the type notifying unit 157 of the sub board 150, and also from the control circuit 200 of the print engine 20 via the engine IF 156 of the sub board 150. The type information of the print engine 20 is acquired. Then, the CPU 112 reads out the FPGA data corresponding to the combination of the type of the sub-board 150 represented by the sub-board signal and the type of the print engine 20 from the flash memory 116, and writes the FPGA data into the FPGA 120, thereby obtaining the combination. Corresponding internal circuits (such as the sub-board IF 126) are configured in the FPGA 120.

  If the circuit configuration of the FPGA differs depending on the number of connected sub-boards 150, for example, the CPU 112 is in an active state during initialization processing among a plurality of pairs of connection units 132 and 134 on the main board 110, for example. What is necessary is just to obtain | require the number of the pair which exists, and let the number be the number of the sub board | substrate 150. Then, FPGA data corresponding to the combination of the type and number of sub-boards 150 and the type of print engine 20 may be selected and written to the FPGA 120.

  As yet another example, there may be a case where the interface processing performed by the sub-board IF 126 can be determined from the type of the connected print engine 20 without directly depending on the connected sub-board 150. In such a case, the CPU 112 obtains information on the type of the print engine 20 from the control circuit 200 of the print engine 20 via the engine IF 156 of the sub board 150, for example, at the time of initialization processing, and corresponds to the type. The FPGA data to be read may be read from the flash memory 116 and written to the FPGA 120.

  As still another example, an example in which the control program executed by the CPU 112 in the image transmission phase (the normal processing phase after completion of the initialization phase) is switched according to the type of the connected print engine 20 will be described below. Protocols such as a communication protocol and a control protocol between the engine interface apparatus 100 and the print engine 20 may differ depending on the type of the print engine 20. In this example, in order to cope with such a case, a control program in which these protocols are installed is changed according to the type of the print engine 20.

  In this example, the flash memory 116 stores a control program corresponding to each type of the print engine 20. Note that the same control program may correspond to a plurality of types of print engines 20.

  Then, when the engine interface apparatus 100 is initialized, the acquisition unit 113 of the CPU 112 first acquires a sub board signal from the type notification unit 157 of the sub board 150 as illustrated in FIG. 6 (S20). Subsequently, the acquisition unit 113 acquires the type information of the print engine 20 from the control circuit 200 of the print engine 20 via the engine IF 156 of the sub board 150 via the control signal line 172 or 176 (S22). Next, the acquisition unit 113 determines whether or not the type of the sub board 150 indicated by the acquired sub board signal matches the type of the acquired print engine 20 (S24). When the sub board 150 is connected to the wrong print engine 20, the determination result in step S24 is negative (No), and the CPU 112 indicates that the wrong print engine 20 is connected to the mother board 12 side of the image processing controller 10. Send an error code indicating. As a result, an error message to that effect is displayed on the screen of the image processing controller 10 (S25). In the flash memory 116, a program and information (such as information on a correct combination of the sub-board and the print engine type) for this determination are registered, and the CPU 112 may execute the program. Note that the processing of S24 and S25 may be applied to the above-described example in which the circuit configuration of the FPGA is determined based on the combination of the types of the sub-board and the print engine.

  If it is determined in step S24 that the connected sub-board 150 and the type of the print engine 20 match, the CPU 112 determines the type of sub-board 150 represented by the sub-board signal (if the number is also related, the type and number). ) Is read from the flash memory 116 (S26), and the internal circuit of the FPGA 120 is configured according to the data (S28). In this example, only the type (and number) of the sub-boards 150 is considered, but the FPGA data may be selected in consideration of the type of the print engine 20.

  In addition, the CPU 112 selects a control program corresponding to the type of the print engine 20 acquired in step S22 from the flash memory 116, and executes the selected control program to enter the image transmission phase (normal operation phase after initialization). Transition (S29).

  Next, still another example will be described with reference to FIGS. In the example of FIG. 5, a dedicated control channel (control signal line 176) for transmitting a signal representing the type of the sub-board 150 is provided, but in the examples of FIGS. 7 and 8, the original image data signal line 174 is provided. The signal is transmitted via.

  In this example, the engine IF 156 of the sub board 150 is provided with a circuit called a sub board type information holding unit 158. The sub board type information holding unit 158 holds information indicating the type of the sub board 150 (engine IF 156). Then, when the engine interface device 100 is initialized, the information is supplied from the sub board type information holding unit 158 to the main board 110 side via the image data signal line 174.

  When the image data signal line 174 includes a plurality of lines, the sub board type information holding unit 158 may be configured as a circuit that holds the setting of the combination of the signal levels of these lines at the time of initialization. The signal level of each line of the image signal data line 174 holds the sub board type information until the main board 110 starts to control the image data signal line 174 in the period when the engine interface device 100 is initialized. The setting signal level of each line set in the unit 158 is set. A combination of the signal levels of these lines becomes a code representing the type of the sub-board 150.

  In this example, as shown in FIG. 8, the CPU 112 of the main board 110 first reads out circuit configuration data of an acquisition circuit for acquiring a sub board signal from the flash memory 116 at the beginning of the initialization process (S30), By writing the circuit configuration data into the FPGA 120, an acquisition circuit is configured in the FPGA 120 (S32). Note that the circuit configuration data of the acquisition circuit is registered in the flash memory 116 in advance.

  The acquisition circuit configured in the FPGA 120 acquires a combination of signal levels of each line of the image data signal line 174 at this time (this is a sub board signal indicating the type of the sub board 150) (S34). Thereafter, the acquisition circuit may acquire the type information of the print engine 20 via the image data signal line 174 via the engine IF 156 and the image data signal line 174 (S22). The subsequent processing may be the same as the procedure shown in FIG.

  Note that the format of the sub-board signal transmitted through the image data signal line 174 is not limited to the combination of the signal levels of each line described above. For example, the sub-board signal may be expressed as a signal whose level changes in time series.

  The embodiments described above are merely exemplary. For example, instead of the FPGA 120, another type of circuit that can reconfigure the circuit configuration, such as DRP (Dynamic Reconfigurable Processor), may be used. Further, the interface between the main board 110 and the motherboard 12 of the image processing controller 10 is not limited to PCI or PCIe, but may be compliant with other standards.

  In the above-described embodiment, the engine interface apparatus 100 that supplies the image data signal to the print engine 20 is illustrated, but this is only an example. The interface device such as a video output card that supplies an image generated by a computer to a display device, a scanner card that serves as an interface with a scanner, and a video capture card that changes a video signal into a data format that can be handled by a computer, etc. A similar configuration can be adopted. The engine interface device 100 and the video output card that control the print engine 20 supply image data signals processed in the device or the card to an external device, that is, the print engine 20 or the display device. In contrast, scanner cards and video capture cards receive image signals from external devices that output image signals, such as scanners, video cameras, and television sets, and perform predetermined image processing on the received image signals. And output the image processing result data. The image processing result data is output, for example, in a still image or moving image file format that can be handled by a computer. As described above, the interface device that processes the image data signal input from the external device in the computer as described above also has a main board on which a common image processing circuit (which is a reconfigurable circuit) is mounted, The function may be separated into a sub-board on which an interface circuit that interfaces with a physical layer corresponding to the type of external device to be connected is mounted. Then, the reconfigurable circuit on the main board is different from the interface circuit on the sub board in the reconfigurable circuit on the main board. What is necessary is just to comprise the interface circuit which absorbs the difference above.

  10 image processing controller, 12 motherboard, 14 PCIe slot, 20 print engine, 30 network, 40 client PC, 100 engine interface device, 110 main board, 112 CPU, 114 RAM, 116 flash memory, 118 page memory, 120 FPGA, 122 PCIe-IF (interface circuit), 124 image processing circuit, 126 sub board IF, 130 bus, 132, 134 connection part, 150 sub board, 152,154 connection part, 156 engine IF, 160 connector, 162, 164 connection part, 172, 182 Control signal line, 174, 184 Image data signal line, 200 Print engine control circuit.

Claims (13)

A connection part to which an interface circuit with an external device is detachably connected;
A reconfigurable circuit configurable as an image processing circuit for processing an image signal to be supplied to the external device via the interface circuit or an image signal supplied from the external device via the interface circuit, wherein the connection A reconfigurable circuit capable of configuring its own internal circuit into a circuit configuration corresponding to the type or number of the interface circuits connected to the unit, or a combination of the types and the number,
An image signal processing apparatus comprising: An acquisition means for acquiring a signal indicating the type of the interface circuit from the interface circuit connected to the connection unit;
The image signal processing apparatus according to claim 1, wherein the reconfigurable circuit configures its own internal circuit into a circuit configuration corresponding to a type corresponding to a signal acquired by the acquisition unit.   When the reconfigurable circuit configures its own internal circuit, it first configures the acquisition means circuit in its own internal circuit, and the image circuit is connected to the interface circuit connected to the connection unit. A first signal representing the type of the interface circuit is acquired from the interface circuit via the image signal line for transmitting the signal by the circuit of the acquisition unit, and the first signal acquired by the circuit of the acquisition unit represents 3. The image signal processing apparatus according to claim 2, wherein the internal circuit is configured to have a circuit configuration corresponding to the type. The acquisition unit circuit further acquires a second signal representing the type of the external device via the interface circuit connected to the connection unit,
The reconfigurable circuit has a circuit configuration corresponding to a combination of the type of the interface circuit represented by the first signal obtained by the circuit of the obtaining unit and the type of the external device represented by the second signal. The image signal processing apparatus according to claim 3, comprising an internal circuit of the image signal processing apparatus. A storage device storing a control program for controlling the external device for each type of the external device;
An execution circuit for executing the selected one of the control programs in the storage device;
Further comprising
The acquisition unit circuit selects and executes a control program corresponding to the type of external device represented by the second signal acquired via the interface circuit connected to the connection unit. Instruct,
The image signal processing apparatus according to claim 4. Further comprising a number detection means for detecting the number of the interface circuits connected to the connection part,
The reconfigurable circuit configures its internal circuit into a circuit configuration corresponding to a combination of the number detected by the number detection unit and the type corresponding to the signal acquired by the acquisition unit.
The image signal processing apparatus according to claim 2, wherein the image signal processing apparatus is an image signal processing apparatus. Comprising a number detecting means for detecting the number of the interface circuits connected to the connecting portion;
The reconfigurable circuit configures its own internal circuit into a circuit configuration corresponding to the number detected by the number detection means.
The image signal processing apparatus according to claim 1. A user designation receiving device that accepts a designation representing the type or number of interface circuits connected to the connection unit, or a combination of the type and number, from a user;
The reconfigurable circuit configures its own internal circuit into a circuit configuration according to the designation received by the user designation receiving device.
The image signal processing apparatus according to claim 1. An external device type obtaining means for further obtaining a signal representing the type of the external device via the interface circuit connected to the connection unit;
The reconfigurable circuit includes the type or number of the interface circuit connected to the connection unit, or a combination of the type and the number, and the type of external device represented by the signal acquired by the external device type acquisition unit. 2. The image signal processing apparatus according to claim 1, wherein the internal circuit is configured to have a circuit configuration corresponding to the combination. A storage device storing a control program for controlling the external device for each type of the external device;
An execution circuit for executing the selected one of the control programs in the storage device;
The execution circuit is configured to acquire a signal representing the type of the external device via the interface circuit connected to the connection unit, and to select and execute a control program corresponding to the type of the external device represented by the acquired signal. Control means for controlling;
The image signal processing apparatus according to claim 1, further comprising: A connection part to which an interface circuit with an external device is detachably connected;
A reconfigurable circuit configurable as an image processing circuit for processing an image signal to be supplied to the external device via the interface circuit or an image signal supplied from the external device via the interface circuit, wherein the connection It is possible to acquire a signal representing the type of the external device via the interface circuit connected to the unit, and configure its own internal circuit to a circuit configuration corresponding to the type of the external device represented by the acquired signal Reconfigurable circuit,
An image signal processing apparatus comprising: An image signal processing device;
An image signal interface circuit provided between the image signal processing device and an external device;
With
The image signal processing apparatus includes:
A connection part to which the interface circuit is detachably connected;
A reconfigurable circuit configurable as an image processing circuit for processing an image signal to be supplied to the external device via the interface circuit or an image signal supplied from the external device via the interface circuit, wherein the connection A reconfigurable circuit capable of configuring its own internal circuit into a circuit configuration corresponding to the type or number of the interface circuits connected to the unit, or a combination of the types and the number,
An image signal processing system comprising: The signal format of the image signal transmitted between the external device and the reconfigurable circuit that functions as an image processing circuit that processes the image signal to be supplied to the external device or the image signal supplied from the external device. A conversion circuit for converting;
In order to configure the reconfigurable circuit as the image processing circuit, a type signal supply circuit that supplies a signal indicating its type to the reconfigurable circuit;
An interface circuit comprising:

Images