JP2011060082A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device for controlling a memory so as to improve the reliability of data to be stored in the memory. <P>SOLUTION: A block area determination part 31 determines an area accessed in a plurality of areas of an MRAM. An access frequency counter updating part 32 counts non-access frequency for each plurality of areas, based on area information determined by the block area determination part 31. A refresh area determination part 33 determines an area to be refreshed according to the non-access frequency counted for each plurality of areas by the access area counter updating part 32. Thereby, error data can be corrected and rewritten before data correction is disabled, and the reliability of data to be stored in the MRAM can be improved. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technology for controlling a memory having an ECC (Error Checking and Correcting) circuit that performs error detection and error correction of data, and in particular, controls the memory so as to improve the reliability of data stored in the memory. The present invention relates to a memory control device.

  In recent years, the capacity and speed of non-volatile memories such as flash memories and MRAMs (Magnetoresistive Random Access Memory) mounted in information processing apparatuses such as mobile phones and personal computers are increasing. In such a nonvolatile memory, there is a case where data becomes an incorrect value when data is written to the memory or while data is stored in the memory. In order to cope with this, a memory device in which an ECC circuit for detecting and correcting the data error is mounted to improve the reliability of stored data has been widely developed. As techniques related to this, there are inventions disclosed in the following Patent Documents 1 to 5.

  Patent Document 1 aims to perform request frequency management of a temporary storage unit with a small memory capacity. The file system includes a group of user terminals that send out a request signal to receive information, a basic file part in which information is stored, a temporary storage part in which frequently requested information is stored, and requested information. A search unit for searching; an information sending unit for sending information to a user terminal group; a counter unit for counting the order in which information is requested; a comparison increment unit for incrementing a count value smaller than the requested information by one; Is provided. The file system further includes an increment unit that increments all count values by one, a maximum value detection unit that detects the maximum count value of the counter unit, an erase unit that erases information corresponding to the maximum count value, and the erase unit And a decrementing unit for erasing the contents of the counter unit corresponding to the information erased by 1 and decrementing the count value larger than the erased information by one.

  Patent Document 2 aims to prevent a file system from suddenly becoming unusable and to determine when to replace the flash memory itself. The file system for flash memory has a judging means for judging whether or not the number of times of writing for each physical block of the flash memory exceeds the guaranteed number of times of rewriting that can be normally written, and as a result of this judgment, In the case where the guaranteed number of rewrites is exceeded, there is a search means for searching for an unused alternative physical block in place of the physical block. The file system further includes alternative physical block creation means for copying the description content of the physical block whose number of occurrences of writing exceeds the guaranteed number of rewrites to the alternative physical block.

  Patent Document 3 discloses a flash memory storage that, as a write control means for leveling the number of rewrites of each memory block, greatly increases the time when a memory block becomes defective and maximizes the available capacity by eliminating a spare area. The object is to realize a file system of the medium control means. A means for storing the number of writes of each memory block of the nonvolatile memory in the memory block is provided, and a means for finding a memory block having the smallest number of times of writing as a write target is provided. Write processing means for storing in a block.

  Patent Document 4 aims to improve the file rewriting performance by utilizing the page erase function. The block is composed of physical addresses 0, 1, 2, and 3. In the initial state, the physical addresses 0, 1, 2, and 3 are all in the erased state. When data LA0, LA1, LA2, and LA3 are written to physical addresses 0, 1, 2, and 3, the count values are “1”, respectively. In this way, the rewriting operation in units of pages (physical addresses) is performed, and the value of the counter value of the physical address for which data has been updated is updated. Finally, when the sum of the count values in the block reaches the allowable value 32, refresh is performed and the state of the memory cells in the block is initialized.

  Patent Document 5 relates to a method and apparatus for reducing data errors in a magnetoresistive random access memory (MRAM). In the disclosed method, data bits and their error correction code (ECC) check bits are stored in a storage area. Thereafter, data bits and ECC check bits are read to detect and check for errors. Next, start refreshing the data based on the count (access the data bits stored in the storage area and its ECC check bits, and finally check the data bits and ECC check bits for the storage area, By correcting and restoring, the data bits and their ECC check bits are refreshed).

JP-A-6-110742 JP-A-8-272664 Japanese Patent Laid-Open No. 10-31611 JP 2004-240572 A JP-T-2006-527447

  Among non-volatile memories, there is a memory such as an MRAM that has a high possibility of causing a problem called write disturb that rewrites arbitrary data other than a write target when data is written. Even if error detection / error correction is performed by the ECC circuit at the time of data reading, as the number of times of writing to the MRAM increases, the data stored in the area with low access frequency becomes an incorrect value while it is not accessed. The possibility of being rewritten increases. Therefore, it is conceivable that a large number of bits are erroneously rewritten in an area with low access frequency.

  On the other hand, the ECC circuit can generally perform only 2-bit error detection and 1-bit error correction of data. Therefore, it is impossible to correct an error in data of 2 bits or more. For this reason, when a large number of bits are erroneously rewritten in an area with low access frequency, there is a problem that even if an ECC circuit is used, it cannot be corrected.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory control device that controls a memory so as to improve the reliability of data stored in the memory.

  According to an embodiment of the present invention, there is provided a memory control device that controls a memory having a function of detecting and correcting data errors when reading data. The block area determination unit determines which of the plurality of areas of the MRAM is an access to the MRAM. The access frequency counter updating unit counts the frequency of not accessing each of the plurality of regions based on the region information determined by the block region determining unit. The refresh area determination unit determines an area that needs to be refreshed according to the frequency of not accessed which is counted for each of the plurality of areas by the access frequency counter update unit. The refresh execution unit reads data from the area determined to be refreshed by the refresh area determination unit.

  According to this embodiment, the refresh area determination unit determines the area that needs to be refreshed according to the frequency of not accessed which is counted for each of the plurality of areas by the access frequency counter update unit. You can correct wrong data and write it back before it becomes impossible. Therefore, it is possible to improve the reliability of data stored in the MRAM.

It is a figure which shows the structural example of the data processor provided with the memory control circuit in the 1st Embodiment of this invention. FIG. 2 is a block diagram showing a functional configuration of a refresh control circuit 1 in the first embodiment of the present invention. It is a flowchart for demonstrating the process sequence of the refresh control circuit 1 in the 1st Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the refresh control circuit 1a in the 2nd Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the refresh control circuit 1b in the 3rd Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the refresh control circuit 1c in the 4th Embodiment of this invention.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a data processing apparatus including a memory control circuit according to the first embodiment of the present invention. Since a typical memory that causes a write disturb that erroneously rewrites arbitrary data other than the data to be written at the time of data writing is an MRAM, the memory device will be described as an MRAM. However, the present invention is not limited to this. is not.

  In addition, when data stored in the MRAM is read and the data is already rewritten to incorrect data, an operation of correcting the erroneous data to correct data and writing it back is referred to as refresh.

  The data processing device includes a memory control device (hereinafter also referred to as a refresh control circuit) 1, a CPU (Central Processing Unit) 11, an ECC circuit 12, an MRAM 13, and an access selector 14.

  The CPU 11 performs processing while writing / reading data to / from the MRAM 13 by fetching and executing an instruction code from a built-in memory (not shown) or the MRAM 13. At this time, the CPU 11 outputs an address via the address signal line 101 and inputs / outputs data via the data signal line 201.

  The access selector 14 receives an address output from the CPU 11 via the address signal line 101 and receives an address output from the refresh control circuit 1 via the address signal line 102. When there is an access request from the CPU 11 to the MRAM 13, the access selector 14 selects an address from the CPU 11 and outputs it to the ECC circuit 12 via the address signal line 103. When there is an access request from the refresh control circuit 1 to the MRAM 13, the address from the refresh control circuit 1 is selected and output to the ECC circuit 12 via the address signal line 103. Note that when the access request from the CPU 11 and the access request from the refresh control circuit 1 conflict, the access request from the CPU 11 is given priority.

  The MRAM 13 has a data storage area and an ECC check code storage area corresponding to the data storage area. When receiving a data write request from the CPU 11, the ECC circuit 12 outputs data to the MRAM 13 through the data signal line 202 and performs data write. At this time, the ECC circuit 12 calculates an ECC check code and stores it in the ECC check code storage area in the MRAM 13.

  When the ECC circuit 12 receives a data read request from the CPU 11 or the refresh control circuit 1, the ECC circuit 12 reads data from the MRAM 13, reads an ECC check code from the ECC check code storage area in the MRAM 13, and performs data error detection. If there is a data error, the data is corrected, and the corrected data and the ECC check code are written back to the MRAM 13. Then, the ECC circuit 12 outputs the corrected data to the CPU 11 via the data signal line 201.

  The ECC circuit 12 outputs an error detection signal 301 to the refresh control circuit 1 when detecting a data error. This error detection signal 301 is used by a memory control device in a third embodiment to be described later.

  The refresh control circuit 1 includes an access management table 2 and a write access definition value register 3. Further, the access management table 2 divides an area for storing data in the MRAM 13 into a plurality of areas (hereinafter referred to as blocks), and each block has a block valid bit 21, an access frequency counter 22, and a block address 23. Keep information.

  The block valid bit 21 is information used to determine whether the information held by the block is valid. This block valid bit 21 is used by the memory control device in the fourth embodiment to be described later.

  The access frequency counter 22 is a counter value indicating the frequency at which the block is not accessed. The refresh control circuit 1 refers to the value of the access frequency counter 22 to determine whether or not to refresh the block.

  The block address 23 is information indicating which area in the MRAM 13 the block corresponds to, and a part of the address when the CPU 11 accesses the MRAM 13, for example, the upper bits of the address output from the CPU 11 is used. .

  The write access definition value register 3 holds the number of times of writing serving as a reference value for starting refreshing the MRAM 13. The refresh control circuit 1 performs refresh on the block in which the value of the access frequency counter 22 is larger than the write access definition value. This write access definition value is used by the memory control device in the second to fourth embodiments described later.

  FIG. 2 is a block diagram showing a functional configuration of the refresh control circuit 1 according to the first embodiment of the present invention. The refresh control circuit 1 includes a block area determination unit 31, an access frequency counter update unit 32, a refresh area determination unit 33, and a refresh execution unit 34. Hereinafter, although the case where the refresh control circuit 1 is realized by hardware will be described, the refresh control circuit 1 can also be realized by a CPU (not shown) executing a program, that is, by software.

  When receiving the address output from the CPU 11, the block area determination unit 31 refers to the block address 23 stored in the access management table 2 and determines which area of the MRAM 13 is to be accessed.

  The access frequency counter updating unit 32 updates the value of the access frequency counter 22 of each block stored in the access management table 2 in response to an access request from the CPU 11 to the MRAM 13 and an access request from the refresh control circuit 1 to the MRAM 13. .

  The refresh area determination unit 33 refers to the value of the access frequency counter 22 stored in the access management table 2 to determine a block area that needs to be refreshed, and requests the refresh execution unit 34 to execute the refresh of the block. To do.

  The refresh execution unit 34 performs a refresh on the block for which a refresh execution request has been received from the refresh area determination unit 33. Specifically, referring to the block address 23 of the block, the address is output to the access selector 14 via the address signal line 102 and a data read request for the block is made to the MRAM 13. As a result, the ECC circuit 12 reads data from the MRAM 13, reads an ECC check code from the ECC check code storage area in the MRAM 13, performs data error detection, corrects the data if there is a data error, The corrected data and the ECC check code are written back to the MRAM 13.

  FIG. 3 is a flowchart for explaining the processing procedure of the refresh control circuit 1 according to the first embodiment of the present invention. First, when the data processing apparatus is activated, the access frequency counter updating unit 32 resets the access frequency counters 22 of all the blocks stored in the access management table 2 to “0” (S11).

  Next, the block area determination unit 31 determines whether or not there is a data write request from the CPU 11 to the MRAM 13 (S12). If there is a data write request (S12, Yes), the address information output from the CPU 11 and the block address 23 stored in the access management table 2 are collated to determine which block the data is written to, The information is output to the access frequency counter updating unit 32 (S13).

  Next, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S14), increments the value of the access frequency counter 22 of all other blocks by "1" (S15), and step S19 The process proceeds.

  If there is no data write request from the CPU 11 to the MRAM 13 (S12, No), the block area determination unit 31 determines whether there is a data read request from the CPU 11 to the MRAM 13 (S16). If there is no data read request (S16, No), the process returns to step S12 and the subsequent processing is repeated.

  When there is a data read request (S16, Yes), the block area determination unit 31 collates the address information output from the CPU 11 with the block address 23 stored in the access management table 2, and to which block It is determined whether it is data reading, and the information is output to the access frequency counter updating unit 32 (S17). Then, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S18), and the process proceeds to step S19.

  In step S <b> 19, the refresh area determination unit 33 refers to the value of the access frequency counter 22 stored in the access management table 2, extracts a block having a large count value, and refreshes the corresponding block with respect to the refresh execution unit 34. And information on the block is output to the access frequency counter updating unit 32.

  Here, the refresh area determination unit 33 may determine the block with the largest access frequency counter 22 as the refresh target block, or set a plurality of blocks with the large access frequency counter 22 as the refresh target blocks. You may decide. In addition, the refresh area determination unit 33 counts the number of times of transition to the process of step S19, and determines the block having the largest access frequency counter 22 value as the refresh target block only once every several times. Good.

  The access frequency counter update unit 32 resets the access frequency counter 22 corresponding to the block to be refreshed by the refresh area determination unit 33 (S20), returns to step S12, and repeats the subsequent processing.

  As described above, the CPU 11 repeatedly writes data to and reads data from the MRAM 13, thereby changing the value of the access frequency counter 22 of each block. When data writing to the MRAM 13 increases, the value of the access frequency counter 22 of the block in which neither data writing nor data reading is performed increases.

  That is, a block having a large value of the access frequency counter 22 has not been accessed for a while, and there is a high possibility that a data error due to write disturb has occurred in the data of the block held in the MRAM 13. Therefore, the refresh control circuit 1 makes a data read request to the block in descending order of the value of the access frequency counter 22.

  As described above, according to the memory control device of the present embodiment, since refresh is performed in the order of the block with the largest access frequency counter 22, the read is intentionally performed on the block with the low access frequency. Can be done. Therefore, before the correction of the data becomes impossible, the ECC circuit 12 can correct the erroneous data and write it back, and the reliability of the data stored in the MRAM 13 can be improved.

(Second Embodiment)
In the first embodiment described above, since the block to be refreshed is determined by the relative relationship of the value of the access frequency counter 22, the refresh is also performed on the block that has not been written to the extent that write disturb occurs. It is thought that it will be.

  In the second embodiment of the present invention, the reliability of the data of a block in which writing is performed to such an extent that refresh is performed on a block whose access frequency counter 22 exceeds a certain value and write disturb occurs. It is what raises.

  The configuration of the data processing apparatus in the second embodiment of the present invention is the same as the configuration of the data processing apparatus in the first embodiment shown in FIG. Further, the functional configuration of the refresh control circuit in the second embodiment of the present invention is different from the functional configuration of the refresh control circuit in the first embodiment shown in FIG. Only the difference. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that the reference numerals of the refresh control circuit and the refresh area determination unit are 1a and 33a, respectively.

  FIG. 4 is a flowchart for explaining the processing procedure of the refresh control circuit 1a according to the second embodiment of the present invention. First, when the data processing apparatus is activated, the access frequency counter updating unit 32 resets the access frequency counters 22 of all the blocks stored in the access management table 2 to “0” (S31). At this time, a value that predefines the reference for starting the refresh operation is set in the write access definition value register 3. The CPU 11 may set a value in the write access definition value register 3, or the refresh control circuit 1 may set a predetermined value in the write access definition register 3 at startup.

  Next, the block area determination unit 31 determines whether or not there is a data write request from the CPU 11 to the MRAM 13 (S32). When there is a data write request (S32, Yes), the address information output from the CPU 11 and the block address 23 stored in the access management table 2 are collated to determine which block the data is written to, The information is output to the access frequency counter updating unit 32 (S33).

  Next, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S34), increments the value of the access frequency counter 22 of all other blocks by “1” (S35), and step S39. The process proceeds.

  If there is no data write request from the CPU 11 to the MRAM 13 (S32, No), the block area determination unit 31 determines whether there is a data read request from the CPU 11 to the MRAM 13 (S36). If there is no data read request (S36, No), the process returns to step S32 and the subsequent processing is repeated.

  When there is a data read request (S36, Yes), the block area determination unit 31 collates the address information output from the CPU 11 with the block address 23 stored in the access management table 2 to determine which block. It is determined whether it is data reading, and the information is output to the access frequency counter updating unit 32 (S37). Then, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S38), and the process proceeds to step S39.

  In step S39, the refresh area determination unit 33a refers to the value of the access frequency counter 22 stored in the write access definition value register 3 and the access management table 2, and the value of the access frequency counter 22 exceeds the write access definition value. It is determined whether there is a block.

  If there is no block in which the value of the access frequency counter 22 exceeds the write access definition value (S39, No), the process returns to step S32 and the subsequent processing is repeated. If there is a block in which the value of the access frequency counter 22 exceeds the write access definition value (S39, Yes), the refresh execution unit 34 refreshes the corresponding block and the access frequency counter update unit 32 The information regarding the corresponding block is output (S40).

  The access frequency counter update unit 32 resets the access frequency counter 22 corresponding to the block to be refreshed by the refresh area determination unit 33a (S41), returns to step S32, and repeats the subsequent processing.

  As described above, according to the memory control apparatus of the present embodiment, since the block whose access frequency counter 22 exceeds the write access definition value is refreshed, the first embodiment In addition to the effects described in (1), the reliability of the data stored in the MRAM 13 can be further increased.

(Third embodiment)
In the second embodiment described above, when the reference value for starting refresh set in the write access definition value register 3 is low, the block is written even when the writing is not performed to the extent that write disturb occurs. It is conceivable that refresh is performed.

  On the contrary, when the reference value set in the write access definition value register 3 is high, it is considered that the block is not refreshed even though the refresh is necessary.

  In the third embodiment of the present invention, the value of the write access definition value register 3 is dynamically changed to refresh a block that is highly likely to cause a write disturb.

  The configuration of the data processing apparatus in the third embodiment of the present invention is the same as the configuration of the data processing apparatus in the first embodiment shown in FIG. Further, the functional configuration of the refresh control circuit in the third embodiment of the present invention is different from the functional configuration of the refresh control circuit in the first embodiment shown in FIG. Only the difference. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that the reference numerals of the refresh control circuit and the refresh area determination unit are 1b and 33b, respectively.

  FIG. 5 is a flowchart for explaining the processing procedure of the refresh control circuit 1b according to the third embodiment of the present invention. First, when the data processing apparatus is activated, the access frequency counter updating unit 32 resets the access frequency counters 22 of all the blocks stored in the access management table 2 to “0” (S51). At this time, as in the second embodiment, the write access definition value register 3 is set to a value that predefines the reference for starting the refresh operation.

  Next, the block area determination unit 31 determines whether or not there is a data write request from the CPU 11 to the MRAM 13 (S52). If there is a data write request (S52, Yes), the address information output from the CPU 11 and the block address 23 stored in the access management table 2 are collated to determine which block the data is written to, The information is output to the access frequency counter update unit 32 (S53).

  Next, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S54), increments the value of the access frequency counter 22 of all other blocks by “1” (S55), and step S59. The process proceeds.

  If there is no data write request from the CPU 11 to the MRAM 13 (S52, No), the block area determination unit 31 determines whether there is a data read request from the CPU 11 to the MRAM 13 (S56). If there is no data read request (S56, No), the process returns to step S52 and the subsequent processing is repeated.

  When there is a data read request (S56, Yes), the block area determination unit 31 collates the address information output from the CPU 11 with the block address 23 stored in the access management table 2, and for which block It is determined whether it is data reading, and the information is output to the access frequency counter updating unit 32 (S57). Then, the access frequency counter updating unit 32 resets the access frequency counter 22 of the corresponding block (S58), and the process proceeds to step S59.

  In step S59, the refresh area determination unit 33b refers to the values of the access frequency counter 22 stored in the write access definition value register 3 and the access management table 2, and the value of the access frequency counter 22 exceeds the write access definition value. It is determined whether there is a block.

  If there is no block in which the value of the access frequency counter 22 exceeds the write access definition value (S59, No), the process returns to step S52 and the subsequent processing is repeated. If there is a block in which the value of the access frequency counter 22 exceeds the write access definition value (S59, Yes), the refresh execution unit 34 refreshes the corresponding block and the access frequency counter update unit 32 The information about the corresponding block is output (S60).

  The access frequency counter update unit 32 resets the access frequency counter 22 corresponding to the block to be refreshed by the refresh area determination unit 33b (S61).

  Next, the refresh area determination unit 33b receives the error detection signal 301 output from the ECC circuit 12 and acquires information indicating whether or not there is a data error (S62).

  Next, the refresh area determination unit 33b corrects the value of the write access definition value register 3 according to whether or not there is a data error (S63), returns to step S52, and repeats the subsequent processing. For example, if there is no data error, it is determined that the current write access definition value is small, and is corrected to a larger value. If there is a data error, it is determined that the current write access definition value is large and is corrected to a smaller value.

  As described above, according to the memory control device of the present embodiment, the write access definition value is modified depending on whether or not there is a data error. In addition to the effects described in the second embodiment, Thus, it becomes possible to perform the refresh to the MRAM 13 more appropriately.

(Fourth embodiment)
In the first to third embodiments, regardless of whether or not data is written in the block, the block in which data is not written for a while is refreshed. However, there is no particular problem even if a data error occurs in a block to which data has not yet been written.

  In the fourth embodiment of the present invention, the block valid bit 21 is used to determine whether or not the block has already been written with data, thereby preventing unnecessary refresh operations.

  The configuration of the data processing apparatus in the fourth embodiment of the present invention is the same as the configuration of the data processing apparatus in the first embodiment shown in FIG. In addition, the functional configuration of the refresh control circuit in the fourth embodiment of the present invention is different from the functional configuration of the refresh control circuit in the first embodiment shown in FIG. Only the function of the area determination unit is different. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that the reference numerals of the refresh control circuit, the block area determination unit, the access frequency counter update unit, and the refresh area determination unit will be described as 1c, 31c, 32c, and 33c, respectively.

  FIG. 6 is a flowchart for explaining the processing procedure of the refresh control circuit 1c according to the fourth embodiment of the present invention. First, when the data processing apparatus is activated, the block area determination unit 31c invalidates the information of the block valid bits 21 of all blocks, and the access frequency counter update unit 32c stores all the blocks stored in the access management table 2. The access frequency counter 22 is reset to “0” (S71).

  Next, the block area determination unit 31c determines whether or not there is a data write request from the CPU 11 to the MRAM 13 (S72). When there is a data write request (S72, Yes), the address information output from the CPU 11 and the block address 23 stored in the access management table 2 are collated to determine which block the data is written to, The information is output to the access frequency counter updating unit 32c (S73).

  Next, the access frequency counter updating unit 32c resets the access frequency counter 22 of the corresponding block (S74). Then, the block area determination unit 31c changes the information of the block valid bit 21 of the corresponding block from invalid to valid (S75).

  Next, the access frequency counter updating unit 32 increments only the value of the access frequency counter 22 of the block in which the block valid bit 21 is valid among all the other blocks by “1” (S76), and step S80. The process proceeds.

  If there is no data write request from the CPU 11 to the MRAM 13 (S72, No), the block area determination unit 31c determines whether there is a data read request from the CPU 11 to the MRAM 13 (S77). If there is no data read request (S77, No), the process returns to step S72 and the subsequent processing is repeated.

  When there is a data read request (S77, Yes), the block area determination unit 31c collates the address information output from the CPU 11 with the block address 23 stored in the access management table 2, and to which block It is determined whether it is data reading, and the information is output to the access frequency counter updating unit 32c (S78). Then, the access frequency counter updating unit 32c resets the access frequency counter 22 of the corresponding block (S79), and the process proceeds to step S80.

  In step S80, the refresh area determination unit 33c determines whether there is a block to be refreshed. This process may use the method of determining that the blocks to be refreshed in the order of the block having the largest value of the access frequency counter 22 described in the first embodiment, or the second and third embodiments. A method may be used in which a block in which the value of the access frequency counter 22 described in the embodiment exceeds the write access definition value is determined as a block to be refreshed.

  If there is no block to be refreshed (S80, No), the process returns to step S72 and the subsequent processing is repeated. If there is a block to be refreshed (S80, Yes), the refresh execution unit 34 is caused to refresh the block, and information on the block is output to the access frequency counter update unit 32c (S81). ).

  The access frequency counter updating unit 32c resets the access frequency counter 22 corresponding to the block to be refreshed by the refresh area determination unit 33c (S82), returns to step S72, and repeats the subsequent processing.

  As described above, according to the memory control device of the present embodiment, it is determined whether refresh is performed by determining whether or not the block has already been written using the block valid bit 21. As a result, unnecessary refresh operations can be prevented from being performed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 refresh control circuit, 2 access management table, 3 write access definition register, 11 CPU, 12 ECC circuit, 13 MRAM, 14 access selector, 21 block valid bit, 22 access frequency counter, 23 block address, 31 block area determination unit, 32, access frequency counter update unit, 33 refresh area determination unit, 34 refresh execution unit, 101, 102, 103, 104 address signal line, 201, 202 data signal line.

Claims (6)

A memory control device for controlling a memory having a function of performing error detection and error correction of data at the time of data reading,
First area determination means for determining which of a plurality of areas of the memory is an access to the memory;
Counting means for counting the frequency of not accessing each of the plurality of areas based on the area information determined by the first area determining means;
Second area determination means for determining an area that needs to be refreshed according to the frequency of not being accessed counted for each of the plurality of areas by the counting means;
A memory control apparatus comprising: refresh execution means for reading data from an area determined to be refreshed by the second area determination means. The counting means resets the frequency corresponding to the area where data was read,
The memory control device according to claim 1, wherein the frequency corresponding to an area where data has been written is reset and the frequency corresponding to other areas is incremented.   3. The memory control device according to claim 1, wherein the second area determination unit determines the areas that need to be refreshed in descending order of the frequency of not being accessed counted for each of the plurality of areas by the counting unit. .   3. The second area determination unit determines an area where the frequency of non-access counted for each of the plurality of areas by the counting unit is larger than a reference value as an area that needs to be refreshed. The memory control device described.   5. The memory control device according to claim 4, wherein the second area determination means changes the reference value when there is a data error when data is read by the refresh execution means. The first area determination means changes the information of the valid bit corresponding to the area where data has been written from invalid to valid,
6. The second area determination unit according to claim 1, wherein only the area where the valid bit is valid is set as a refresh target area, and the area where the valid bit is invalid is excluded from the refresh target area. The memory control device according to any one of the above.

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