JP2016151922A - Memory control device and memory control method - Google Patents

Abstract

PURPOSE: To provide a memory control device and a memory control method with which it is possible to perform an error check and a refresh process on a memory without obstructing the operation of the memory.CONSTITUTION: The number of times data is read from each of a plurality of blocks constituting a memory is stored as block access count information. A refresh process is performed on a block among the plurality of blocks of the memory in which the number of times data is read exceeds a first threshold on the basis of the block access count information. A memory check process is also performed on a block in which the number of times data is read is less than or equal to the first threshold and greater than or equal to a second threshold. No refresh process and memory check process are performed on a block in which the number of times data is read is less than the first threshold and second threshold.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a memory control device and a memory control method for accessing data to a memory.

  In recent years, with an increase in memory capacity, NAND flash memories that are superior in bit unit price have become widespread. In such a NAND flash memory, with the increase in capacity and integration, the problems of aging degradation of written data and the problem that data cannot be read correctly due to concentrated read operations have become prominent. These problems are caused by the fact that the charge for data retention decreases with the passage of years, and the stored data is destroyed due to a small amount of charge accumulation in the adjacent memory cells accompanying the read operation.

  Therefore, in order to avoid such a problem, an error correcting code (ECC) for correcting an error in data is added to the data and written together with the data, and the error is corrected by reading the data. Is done. However, there is a limit to the number of bits that can be corrected using the correction code, and correction cannot be performed when an error with the number of bits exceeding the limit occurs. Therefore, it is necessary to detect and correct an error before the number of correctable bits reaches the limit. Therefore, as a method for detecting an error before the limit of the number of bits that can be corrected, an apparatus for performing a memory check when normal data reading is not performed and determining whether it is necessary to perform refresh processing has been considered (for example, Patent Document 1).

JP 2011-128751 A

  In such an apparatus, a memory check is performed during memory standby (idling) to determine an area that requires refresh processing. However, even if the memory is in a standby state at the start of the memory check, data read may be requested during the memory check process thereafter. In such a case, since it is necessary to perform the data read process after the memory check process is completed, there is a problem that the operation of the memory is hindered, for example, the data read process is delayed.

  In addition, when access to a specific memory cell is concentrated, many bit errors may occur not only in the memory cell where access is concentrated but also in adjacent memory cells in the same memory block. There has been a problem that there may be an error in the number of bits that exceeds the limit that can be corrected with an error correction code.

  The present invention has been made to solve the above problems, and provides a memory control device and a memory control method capable of performing a memory error check and refresh process without hindering the operation of the memory. Objective.

  A memory control device according to the present invention is a memory control device that performs data write or read control on a memory, and is an interface unit that is connected to the memory and performs data write or read on the memory And a storage unit for storing the number of times of reading data for each of the plurality of blocks constituting the memory as block access number information, and reading of data among the plurality of blocks of the memory based on the block access number information And a control unit that performs a refresh process on a block whose number of times exceeds a first threshold value.

  According to another aspect of the present invention, there is provided a memory control method for performing data write or read control on a memory, wherein the number of times data is read from each of a plurality of blocks constituting the memory is set to the number of block accesses. Storing as information, and performing refresh processing on a block in which the number of times of reading data exceeds a first threshold among the plurality of blocks of the memory based on the block access count information, It is characterized by including.

  In the present invention, it is determined whether or not to perform refresh processing and memory check processing according to the number of accesses to each memory block in the memory. The refresh process or the memory check process is performed only when the access count exceeds a predetermined threshold. Since processing is not performed for memory blocks with a small number of accesses, the time required for memory check and refresh processing can be shortened.

  Further, when receiving the reset signal, it is determined whether or not the reset signal is a power-on reset signal. Only when it is determined that the power-on reset signal has been received, whether or not to perform the memory check process and the refresh process. Make a decision. As a result, since there is no standby state for memory check and refresh processing at the time of reset other than immediately after power-on, high-speed access to the flash memory can be performed.

  Therefore, according to the present invention, it is possible to perform a memory error check and refresh process without hindering the operation of the memory.

It is a block diagram which shows the structure of the information processing apparatus which concerns on this invention. It is a figure which shows the information contained in page / block information and management information. It is a figure which shows typically the some block and page which comprise flash memory. It is a flowchart which shows a starting check routine. It is a flowchart which shows a memory check object offset page update routine. It is a flowchart which shows an error generation confirmation routine. It is a flowchart which shows a block access frequency information offset update routine. It is a flowchart which shows a refresh routine. It is a flowchart which shows a block access frequency information update routine. It is a flowchart which shows the block access frequency information update routine in Example 2 of this invention. It is a figure which shows the information contained in the page / block information and management information in Example 3 of this invention. It is a flowchart which shows the starting check routine in Example 3 of this invention. It is a flowchart which shows the 2nd mode process routine in Example 3 of this invention. It is a flowchart which shows the priority memory check object offset page update routine in Example 3 of this invention. It is a flowchart which shows the memory check object block and offset page update routine in Example 3 of this invention. It is a flowchart which shows the error generation confirmation routine in Example 3 of this invention. It is a flowchart which shows the refresh routine in Example 3 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an information processing apparatus 10 including a memory control apparatus according to the present invention. As shown in FIG. 1, the information processing apparatus 10 includes a CPU (Central Processing Unit) 11, an interface unit 12, a RAM (Random Access Memory) 13, a flash memory 14, a CPU bus 15, a power-on reset generation unit 16, and an OR gate 17. And an internal reset generator 18.

  The CPU 11 is connected to the interface unit 12, the RAM 13, and the internal reset generation unit 18 via the CPU bus 15. The CPU 11 performs data read / write access to the flash memory 14 via the CPU bus 15 and the interface unit 12.

  That is, the CPU 11 reads out program data (not shown) stored in the flash memory 14, that is, a main program for realizing the main function of the information processing apparatus 10 through the interface unit 12, and follows this main program. A control unit that executes main control. Further, the CPU 11 reads the refresh program data and the memory check program data stored in the flash memory 14 through the interface unit 12, and performs a refresh process according to the refresh program data and a memory check process according to the memory check program data. Execute. This refresh process is a process of reading an encoded data piece from a target memory block, performing an error correction process, and writing it in a different memory block. The memory check process is a process for checking whether or not the data stored in the flash memory 14 can be read correctly. Details of the refresh process and the memory check process will be described later.

  The interface unit 12 includes an error detection / correction unit 20, a status register 21, and a memory check area designation register 22. The error detection and correction unit 20 detects an error included in a check target page (hereinafter referred to as an offset page) of a memory block (hereinafter simply referred to as a block) that is a target of a memory check process described later. Further, the error detection and correction unit 20 corrects an error for the designated block. The status register 21 holds information such as the number of bits of errors detected by the error detection / correction unit 20. The memory check area designation register 22 holds information indicating a memory area designated as a target of the memory check process. The interface unit 12 has control information for access such as reading and writing to the flash memory 14. The control information of the interface unit 12 is reset (initialized) according to the reset signal R.

  The RAM 13 includes a power-on reset check area 30 as a storage unit. In the power-on reset check area 30, for example, a 1-byte value “0x5A” (power-on-reset code) is stored in the CPU 11 as information indicating that the power-on reset signal PR that is the first reset signal after power-on is received. Written by. Once “0x5A” is written, the power-on reset check area 30 holds the value of “0x5A” until the power is turned off. The RAM 13 stores page / block information 31. As shown in FIG. 2A, the page / block information 31 includes block access count information 301, refresh target block information 302, memory check target block information 303, and memory check target offset page information 304.

  As shown in FIG. 3A, the flash memory 14 is divided into access areas of L blocks 1 to L (L; natural number), each block including K pages 1 to K (K: natural number). Has been. The flash memory 14 has an area for storing management information 40. The management information 40 includes block access count information 401, refresh target block information 402, and memory check target block information 403, as shown in FIG.

  The block access count information 301 and 401 is information indicating the cumulative number of read accesses to each block of the flash memory 14 for each block. The block access count information update process will be described later.

  The power-on reset generation unit 16 generates a one-pulse reset signal PR (first reset signal) when the information processing apparatus 10 is turned on, and supplies this to the OR gate 17. The internal reset generation unit 18 generates a one-pulse reset signal IR (second reset signal) in response to a reset request command issued during execution of the main control or a timeout error by a program timer (not shown). Is supplied to the OR gate 17. When the reset signal PR is supplied from the power-on reset generation unit 16, the OR gate 17 supplies the reset signal R to the CPU 11 and the interface unit 12 as a reset signal R (initialization signal). In addition, when the reset signal IR is supplied from the internal reset generation unit 18, the OR gate 17 supplies the reset signal R to the CPU 11 and the interface unit 12.

  In accordance with the reset signal R, the CPU 11 executes a start check process according to the start check routine shown in FIG. The activation check process is a process including a refresh process, a memory check process, and a process for determining whether to perform these processes.

  First, the CPU 11 determines whether or not the value held in the power-on reset check area 30 of the RAM 13 is “0x5A” (step S1). When it is determined in step S1 that the value held in the power-on reset check area 30 is “0x5A”, the CPU 11 determines that the received reset signal R is not based on the power-on reset signal PR. This start check routine is terminated. On the other hand, if it is determined in step S1 that “0x5A” is not held in the power-on reset check area 30, the CPU 11 determines that the received reset signal R is based on the power-on reset signal PR, and the RAM 13 "0x5A" is written in the power-on reset check area 30 (step S2).

  Next, the CPU 11 reads the management information 40 shown in FIG. 2B from the flash memory 14 via the interface unit 12, and writes it into the RAM 13 as page / block information 31 (step S3). As a result, the block access count information 401 in the management information 40 is stored in the RAM 13 as the block access count information 301. Further, the refresh target block information 402 in the management information 40 is stored in the RAM 13 as the refresh target block information 302. Further, memory check target block information 403 is stored in the RAM 13 as memory check target block information 303.

  Based on the block access count information 301 stored in the RAM 13, the CPU 11 determines whether or not the read access count of the target block (for example, block 1) in the flash memory 14 exceeds the first access threshold TA1. It is determined whether it is larger than TA1 (step S4). Note that the determination in step S4 is performed for all blocks 1 to L through addition and storage processing of the refresh target block information.

  As a result of the determination in step S4, when the number of read accesses of the target block is larger than the first access threshold TA1, the CPU 11 adds the block as a refresh target block to the refresh target block information 302 (step S5). . Further, the CPU 11 stores the information as the refresh target block information 402 in the flash memory 14 (step S6).

  On the other hand, if it is determined in step S4 that the number of read accesses of the target block does not exceed the first access threshold TA1, the CPU 11 determines that the number of read accesses of the target block is the second access threshold TA2 (TA2 <TA It is determined whether it is larger than TA1) (step S7).

  As a result of the determination in step S7, when the number of read accesses of the target block is larger than the second access threshold TA2, the CPU 11 sets the block as a memory check target area and the memory check area designation register 22 of the interface unit 12. (Step S8). After execution of step S8, the CPU 11 executes the update process of the memory check target offset page shown in FIG. 5 for the memory check target block (step S9).

  FIG. 5 is a flowchart showing a routine of such memory check target offset page update processing. The CPU 11 first uses the number obtained by incrementing the number indicated by the memory check target offset page information 304 stored in the RAM 13 by 1 as the page number indicating the new memory check target offset page, and the memory check target offset page information in the RAM 13. It is overwritten and stored in 304 (step S21). For example, when the page number “N” is stored, the page number “N + 1” obtained by incrementing 1 is overwritten and stored as a new page number. Next, the CPU 11 determines whether or not the incremented page number has exceeded the last page number K (step S22). If it is determined in step S22 that the number K of the last page has been exceeded, that is, if all the memory check processing within the memory check target block has been completed, the CPU 11 stores the memory check target offset stored in the RAM 13 The page number of the page information 304 is set to 0 (step S23).

  After execution of the memory check target offset page information update process (step S9) in FIG. 4, the CPU 11 executes a memory read check process (memory check process) for the specified memory area (step S10).

  That is, the CPU 11 specifies an address in the flash memory 14 and supplies a read command signal to the interface unit 12. The interface unit 12 reads the encoded data piece stored in the page corresponding to the designated address from the flash memory 14 in response to the read command signal. The error detection and correction unit 20 of the interface unit 12 performs error detection processing on the encoded data piece, and generates error information indicating the number of error bits. The CPU 11 stores the error information in the status register 21 of the interface unit 12 in association with the block number in the flash memory 14 in which the encoded data piece in which the error is detected is held.

  As shown in FIG. 3B, the memory check process is performed for all pages up to the Kth page of the target block (for example, block M) while incrementing the number of pages.

  The CPU 11 executes an error occurrence confirmation process as shown in FIG. 6 during the memory read check process for the designated memory area in step S10.

  Based on the error information stored in the status register 21, the CPU 11 determines whether the number of error bits exceeds the first error threshold TE1, that is, whether it is larger than TE1 (step S31). . The first error threshold value TE1 is a value close to the limit value of the number of error bits that can be corrected by error correction processing, and is a numerical value that serves as a guide for the number of bits that require refresh processing.

  When it is determined that the number of error bits is larger than the first error threshold TE1, the CPU 11 adds the block to the refresh target block information 302 in the RAM 13 (step S32). Further, the CPU 11 stores the information as the refresh target block information 402 in the flash memory 14 (step S33).

  On the other hand, when it is determined in step S31 that the number of error bits does not exceed the first error threshold TE1, the CPU 11 determines whether or not the number of error bits is larger than the second error threshold TE2 (TE2 <TE1). Is determined (step S34). The second error threshold value TE2 is a numerical value that serves as a guide for the number of error bits that need to be observed, although the number does not require the refresh process.

  When it is determined that the number of error bits does not exceed the second error threshold TE2, the CPU 11 clears the block from the memory check target block information 303 in the RAM 13 (step S35). On the other hand, when it is determined that the number of error bits is larger than the second error threshold value TE2, the CPU 11 does not clear the block. That is, the RAM 13 holds the previous memory check target block information 303 as it is.

  In step S10 shown in FIG. 4, the CPU 11 executes a memory read check process for the designated memory area including the error occurrence confirmation routine as described above.

  On the other hand, if it is determined in step S7 that the number of read accesses of the target block does not exceed the threshold TA2, the CPU 11 determines whether or not the target block is registered in the memory check area designation register 22 of the interface unit 12. (Step S11). Whether the target block corresponds to, for example, a memory block that has not been subjected to the memory check process due to an unexpected operation even though it has been registered in the register as the target area for the memory check process during the previous startup check process It is the process which determines. If it is determined that it is registered in the memory check area designation register 22, the CPU 11 proceeds to execution of a memory check target offset page update process in step S9.

  When it is determined in step S11 that the target block is not registered in the memory check area designation register 22, or the process of saving the refresh target block information 402 to the flash memory 14 (step S6) or the memory reading check process of the designated memory area After executing (Step S10), the CPU 11 executes an update process of the block access count information offset (Step S12).

  FIG. 7 is a flowchart showing a routine for updating the block access count information offset.

  First, the CPU 11 sets a number obtained by incrementing the target block number indicated by the block access count information 301 stored in the RAM 13 by 1 as a new block number as an access count check target (step S41). For example, when the access frequency check target is the block number “M”, the block number “M + 1” obtained by incrementing 1 is set as a new block number. Next, the CPU 11 determines whether or not the incremented block number has exceeded the last block number L (step S42). If it is determined in step S42 that the number L of the last block has been exceeded, that is, if all the access count checks have been completed, the CPU 11 sets the offset of the block access count information to 0 (step S42). S43).

  The CPU 11 determines whether or not the check processing in steps S4 to S12 has been completed for all blocks (step S13). If it is determined that the process has been completed, the CPU 11 proceeds to the execution of the refresh process (step S14). If it determines with having not completed, CPU11 will return to step S4 and will perform the process of step S4-S12 again.

  FIG. 8 is a flowchart showing a refresh processing routine. The CPU 11 determines whether there is a refresh target block based on the refresh target block information 302 in the RAM 13 (step S51). If it is determined that there is no refresh target block, the CPU 11 ends the refresh process.

  When determining that there is a block to be refreshed, the CPU 11 sends a refresh processing execution command to the interface unit 12 (step S52).

  That is, the interface unit 12 first reads the encoded data piece from the target block for the refresh process. The error detection / correction unit 20 of the interface unit 12 performs error correction processing on the encoded data piece. The interface unit 12 writes the encoded data piece for one block subjected to the error correction processing into a block different from the block in which the encoded data piece is held.

  The CPU 11 deletes the number of the block on which the refresh process has been performed from the refresh target block information 302 of the RAM 13 (step S53). Further, the CPU 11 sets the access count of the block number to 0 (step S54), and updates the block access count information 301 in the RAM 13.

  After executing the refresh process (step S14) shown in FIG. 4, the CPU 11 executes an update process of the management information 40 in the flash memory 14 via the interface unit 12. This update process of the management information 40 includes an update process of the block access count information 401.

  FIG. 9 is a flowchart showing a routine of such block access count information update processing. The CPU 11 determines whether or not there has been a read access to the flash memory 14 (step S61). When determining that there is no read access, the CPU 11 ends the block access count information update process.

  If it is determined that there is a read access, the CPU 11 increments the access count of the block in which the read access has been made (step S62). In addition, the CPU 11 increments the number of read accesses to all blocks (total number of read accesses) (step S63).

  The CPU 11 determines whether or not the total number of read accesses has exceeded the third access threshold TA3 (step S64). If it is determined that TA3 has not been exceeded, the CPU 11 ends the block access count information update process. On the other hand, when determining that TA3 is exceeded, the CPU 11 stores the incremented block access count information in the flash memory 14 as the block access count information 401 (step S65).

  As described above, in the above-described start check process, first, it is determined whether or not the refresh process and the memory check process are performed on the target block according to the number of read accesses to each memory block in the flash memory 14. When the number of read accesses exceeds the first access threshold TA1, refresh processing is performed. When the number of read accesses does not exceed the first access threshold TA1, but exceeds the second access threshold TA2, the memory is refreshed. Perform check processing. That is, when the number of read accesses does not exceed the second access threshold TA2, the memory check process and the refresh process are not performed. Thereby, since processing is not performed for a memory block with a small number of accesses, the time required for executing the memory check processing and the refresh processing can be shortened.

  In the activation check process described above, the block access count information 301 updated in the RAM 13 is stored in the flash memory 14 as the block access count information 401. As a result, the number of block accesses and the accumulated block access information during the previous activation check process can be acquired, and the activation check process, the refresh process, and the memory check process based on the accurate block access number can be performed.

  In the above-described start check process, the refresh target block information 302 updated in the RAM 13 is stored in the flash memory 14 as the refresh target block information 402. As a result, it is possible to obtain the refresh target block information at the time of the previous start check process, so that the block that was registered in the refresh target block information but was not subjected to the refresh process at the previous start check due to an unexpected operation, etc. In contrast, it is possible to perform a refresh process.

  In the above-described start check process, the memory check target block information 303 updated in the RAM 13 is stored in the flash memory 14 as the memory check target block information 403. As a result, the memory check process can be performed on a block that has been registered in the memory check target block information but has not been subjected to the memory check process at the previous activation check due to an unexpected operation or the like. In addition, it is possible to perform the memory check process on a block in which the number of error bits continuously exceeds the second error threshold TE2 from the memory check target block information at the time of the previous activation check process.

  In the above-described start check process, it is determined whether or not the reset signal R is based on the power-on reset signal PR based on the value held in the power-on reset check area 30 of the RAM 13. Only when the reset signal R based on the power-on reset signal PR is received, the activation check process is performed. That is, when the reset signal R based on the internal reset signal IR is received, it is determined not to perform the refresh process and the memory check process. Thereby, except immediately after power-on, there is no standby state for executing the start check process, the memory check process, and the refresh process when accessing the flash memory 14, so that the flash memory 14 is always accessed at high speed. Is possible. Furthermore, since the start check process, the memory check process, and the refresh process are performed only immediately after the power is turned on, it is possible to suppress the deterioration of the memory due to the frequent execution of these processes.

  The information processing apparatus according to the second embodiment is the same as the information processing apparatus 10 according to the first embodiment illustrated in FIG. 1 with respect to the configuration of each unit, and is different from the information processing apparatus 10 according to the first embodiment in block access information update processing. The block access information update process will be described below.

  FIG. 10 is a flowchart showing a routine of block access frequency information update processing. The CPU 11 determines whether or not there has been a read access to the flash memory 14 (step S71). When determining that there is no read access, the CPU 11 ends the block access count information update process.

  If it is determined that there is a read access, the CPU 11 increments the access count of the block that has been accessed (step S72).

  The CPU 11 determines whether or not the access count of the block that has undergone read access has exceeded the fourth access threshold TA4 (step S73). If it is determined that TA4 has not been exceeded, the CPU 11 ends the block access count information update process. On the other hand, if it is determined that TA4 has been exceeded, the CPU 11 stores the access count information for the block that has exceeded TA4 in the flash memory 14 as block access count information 401 (step S74).

  As described above, in the present embodiment, the block access count information is updated and stored in the flash memory 14 only for the blocks whose read access count exceeds the fourth access threshold TA4. Therefore, the offset of the block access count information can be reduced, and the time required for the activation check process can be shortened. Further, it is possible to suppress deterioration of the memory due to frequent information storage.

  The information processing apparatus according to the second embodiment is the same as the information processing apparatus 10 according to the first embodiment illustrated in FIG. 1 with respect to the configuration of each unit, and the information stored in the RAM 13 as the page / block information 31 and the flash as the management information 40. The information stored in the memory 14 is different from the information processing apparatus 10 of the first embodiment. In addition to the first mode for performing the refresh process and the memory check process determination process similar to the activation check process of the first embodiment, the second embodiment includes a second mode for performing a priority memory check process to be described later. Different from the information processing apparatus 10 of FIG. Hereinafter, a different part and operation | movement from Example 1 are demonstrated.

  As shown in FIG. 11A, the page / block information 31 stored in the RAM 13 includes priority memory check target block information 305 and priority memory check target offset page information 306 in addition to the information 301 to 304. .

  As illustrated in FIG. 11B, the management information 40 stored in the flash memory 14 includes check target offset page information 404 and priority memory check block information 405 in addition to the pieces of information 401 to 403.

  In response to the reset signal R, the CPU 11 executes the first mode process or the second mode process according to the activation check routine shown in FIG.

  First, the CPU 11 determines whether or not the value held in the power-on reset check area 30 of the RAM 13 is “0x5A” (step S1). When it is determined in step S1 that the value held in the power-on reset check area 30 is “0x5A”, the CPU 11 determines that the received reset signal R is not based on the power-on reset signal PR. This start check routine is terminated. On the other hand, if it is determined in step S1 that “0x5A” is not held in the power-on reset check area 30, the CPU 11 determines that the received reset signal R is based on the power-on reset signal PR, and the RAM 13 "0x5A" is written in the power-on reset check area 30 (step S2).

  Next, the CPU 11 reads the management information 40 shown in FIG. 11B from the flash memory 14 via the interface unit 12, and writes it into the RAM 13 as page / block information 31 (step S3). Thereby, the block access count information 401, the refresh target block information 402, the memory check target block information 403, the check target offset page information 404, and the priority memory check target block information 405 in the management information 40 are respectively converted into the block access count information 301, The refresh target block information 302, the memory check target block information 303, the memory check target offset page information 304, and the priority memory check target block information 305 are stored in the RAM 13.

  Based on the block access count information 301 stored in the RAM 13, the CPU 11 determines whether or not the total number of read accesses to all blocks in the flash memory 14 exceeds the fifth access threshold TA5, that is, more than TA5. It is determined whether it is larger (step S4).

  When it is determined that the fifth access threshold TA5 has been exceeded, the CPU 11 executes a first mode process (step S5). This first mode process is a process corresponding to steps S4 to S14 in FIG. 4 of the activation check process in the first embodiment. Therefore, description of the first mode process is omitted here.

  On the other hand, if it is determined that the total number of read accesses to all blocks does not exceed the fifth access threshold TA5, the CPU 11 proceeds to the execution of the second mode process (step S6).

  FIG. 13 is a flowchart showing a routine of the second mode process. First, based on the priority memory check target block information 305 stored in the RAM 13, the CPU 11 determines whether or not the target block (for example, block 1) in the flash memory 14 is a priority memory check target block (step S11). ). Note that the determination in step S11 is performed for all blocks 1 to L through a memory check target block and offset page information update processing described later.

  As a result of the determination in step S11, if the target block is a target block for the priority memory check, the CPU 11 sets the block as a priority memory check target area in the memory check area designation register 22 of the interface unit 12 (step S12). ). After execution of step S12, the CPU 11 proceeds to execution of a priority memory check target offset page update process (step S13).

  FIG. 14 is a flowchart showing a routine of such a priority memory check target offset page update process. The CPU 11 first increments the number indicated by the priority memory check target offset page information 306 stored in the RAM 13 by 1 and uses the number indicating the new priority memory check target offset page as the number indicating the new priority memory check target offset page. The page information 306 is overwritten and stored (step S21). For example, when the page number “N” is stored, the page number “N + 1” obtained by incrementing 1 is overwritten and stored as a new page number. Next, the CPU 11 determines whether or not the incremented page number has exceeded the last page number K (step S22). If it is determined in step S22 that the number K of the last page has been exceeded, that is, if all of the priority memory check processing (to be described later) in the priority memory check target block has been completed, the target of the priority memory check in the RAM 13 The offset page information 306 is cleared to the initial value (step S23). After execution of step S23, the CPU 11 proceeds to execution of memory check target block and offset page update processing (step S24).

  FIG. 15 is a flowchart showing a routine of such memory check target block and offset page update processing. The CPU 11 overwrites and stores in the RAM 13 a number obtained by incrementing the number indicated by the memory check target block information 303 stored in the RAM 13 by 1 as a number indicating a new memory check target block (step S31). Next, the CPU 11 determines whether or not the incremented block number has exceeded the last block number L (step S32). If it is determined in step 32 that the number L of the last block has been exceeded, that is, if the memory check processing in the target block for the normal memory check has been completed, the CPU 11 stores the memory stored in the RAM 13. The block number of the check target block information 303 is set to 0 (step S33). Next, the CPU 11 overwrites and stores in the RAM 13 a number obtained by incrementing the page number indicated by the memory check target offset page information 304 stored in the RAM 13 by 1 as a number indicating a new memory check target offset page (step S34). ). Next, the CPU 11 determines whether or not the incremented page number has exceeded the last page number K (step S35). If it is determined in step 35 that the number K of the last page has been exceeded, that is, if the memory check processing has been completed for all pages in the target block for normal memory check, the CPU 11 is stored in the RAM 13. The page number of the memory check target offset page information 304 is set to 0 (step S36).

  After execution of step S36, or when it is determined in step S32 that the final block number L has not been exceeded, or in step S35 it is determined that the final page number K has not been exceeded, the CPU 11 stores the memory shown in FIG. After exiting the check target block and offset page update routine, the flow proceeds to execution of step S16 in FIG.

  On the other hand, if it is determined in step S11 shown in FIG. 13 that the target block is not the target block for the priority memory check, the CPU 11 sets the block as a normal memory check target area and uses the memory check area designation register of the interface unit 12. Is set to 22 (step S14). After execution of step S14, the CPU 11 proceeds to execution of the memory check target block and offset page information update process shown in FIG. 15 (step S15).

  After executing the priority memory check target offset page information update process (step S13) shown in FIG. 13 or the memory check target block and offset page information update process (step S15), the CPU 11 performs a memory read check process (memory for the specified memory area). Check processing) is executed (step S16).

  That is, the CPU 11 specifies an address in the flash memory 14 and supplies a read command signal to the interface unit 12. The interface unit 12 reads the encoded data piece stored in the page corresponding to the designated address from the flash memory 14 in response to the read command signal. The error detection and correction unit 20 of the interface unit 12 performs error detection processing on the encoded data piece, and generates error information indicating the number of error bits. The CPU 11 stores the error information in the status register 21 of the interface unit 12 in association with the block number in the flash memory 14 in which the encoded data piece in which the error is detected is held.

  In the memory check process, reading and error detection are performed while incrementing the block number. For example, all blocks in the order of page N in block 1, page N in block 2, page N in block 3, and so on. The memory check is performed with the corresponding page as the target page. Further, since the offset page is incremented when the memory check is completed up to the last block, the memory check process is performed for a different page each time the power is turned on.

  On the other hand, in the priority memory check process, a check is performed while incrementing the number of pages for the target block for the priority memory check. As a result, as shown in FIG. 3B, for example, a memory check is performed on all pages of the block M.

  The CPU 11 executes an error occurrence confirmation process as shown in FIG. 16 during the memory read check process for the designated memory area in step S16.

  In FIG. 16, the CPU 11 determines whether or not there is an error, that is, whether or not the number of error bits is 1 or more, based on the error information stored in the status register 21 (step S41). When determining that there is no error, the CPU 11 ends the error occurrence confirmation process.

  On the other hand, if it is determined in step S41 that there is an error, the CPU 11 determines whether the number of error bits is larger than the third error threshold TE3 based on the error information stored in the status register 21. (Step S42). When it is determined that the number of error bits is larger than the third error threshold value TE3, the CPU 11 adds the number of the block to the priority memory check target block information 305 of the RAM 13 (step S43). Next, the CPU 11 determines whether or not the number of error bits is larger than a fourth error threshold value TE4 (TE4> TE3) (step S44). When it is determined that the number of error bits is larger than the fourth error threshold TE4, the CPU 11 adds the block number to the refresh target block information 302 of the RAM 13 (step S45).

  After execution of step S45, or when it is determined in step S44 that the number of error bits is equal to or less than the fourth error threshold value TE4, the CPU 11 ends the error occurrence confirmation routine.

  After executing the memory read check process (step S16) for the designated memory area including this error occurrence confirmation routine, the CPU 11 determines whether or not the memory read check has been completed for all blocks (step S17). If it is determined that the process has been completed, the CPU 11 proceeds to the execution of the refresh process (step S18). If it determines with having not completed, CPU11 will return to step S11 and will perform the process of step S11-S16 again.

  FIG. 17 is a flowchart illustrating a refresh processing routine. The CPU 11 determines whether there is a refresh target block based on the refresh target block information 302 in the RAM 13 (step S51). If it is determined that there is no refresh target block, the CPU 11 ends the refresh process.

  When determining that there is a block to be refreshed, the CPU 11 sends a refresh processing execution command to the interface unit 12 (step S52).

  That is, the interface unit 12 first reads the encoded data piece from the target block for the refresh process. The error detection / correction unit 20 of the interface unit 12 performs error correction processing on the encoded data piece. The interface unit 12 writes the encoded data piece for one block subjected to the error correction processing into a block different from the block in which the encoded data piece is held.

  The CPU 11 deletes the number of the block on which the refresh process has been performed from the refresh target block information 302 of the RAM 13 (step S53). Further, the CPU 11 deletes the block number from the priority memory check target block information 305 of the RAM 13 (step S54).

  After executing the refresh process, the CPU 11 executes the management information update process (step S7) of FIG. This management information update process is a process of saving the page / block information 31 stored in the RAM 13 as the management information 40 of the flash memory 14, and includes a block access count information update process similar to that in the first or second embodiment. .

  As described above, in this embodiment, the information processing apparatus 10 has a function of executing the second mode process including the priority memory check process in addition to the first mode process that performs the same process as that of the first embodiment. If the total number of read accesses to all blocks of the flash memory 14 exceeds a predetermined threshold (TA5), the first mode process is executed, and if not, the second mode process is executed. That is, the information processing apparatus 10 according to the present embodiment executes the refresh process and the memory check process according to the access count when the access count is large, and the memory check process that does not assume the access count when the access count is small. The priority memory check process and the refresh process are executed. Therefore, even when there are few accesses to the memory, the memory check can be performed, and appropriate refresh processing and memory check processing according to the situation can be executed.

  As described above, according to the present invention, it is determined whether the refresh process and the memory check process are performed on the target block according to the number of read accesses to each memory block in the memory. Only when the number of read accesses exceeds a predetermined threshold, the memory check process and the refresh process are performed. Therefore, since processing is not performed on a memory block with a small number of accesses, the time required for executing the memory check processing and the refresh processing can be shortened.

  Further, since refresh processing and memory check processing are performed according to the number of accesses in block units, refresh processing and memory processing are performed not only on memory cells where access is concentrated, but also on adjacent memory cells in the same block. Memory check processing can be performed.

  In addition, according to the present invention, only when a power-on reset signal is received, the memory check process, the refresh process, and whether to perform these processes are determined. There is no waiting state for Therefore, high speed access to the flash memory can be performed.

  In the above embodiment, as the block access count information 301 and 401, information on the read access count for each block of the flash memory 14 is managed. However, the present invention is not limited to this. For example, the information on the number of accesses may be managed in units of pages constituting a block or in units of processing data amount in error correction processing.

  Further, in the above embodiment, when the reset signal R based on the power-on reset signal PR is received, the 1-byte value “0x5A” is written in the power-on reset check area 30 and received depending on whether or not this value is held. It is determined whether or not the reset signal R is based on the power-on reset signal PR. However, it is only necessary to determine whether or not the reset signal R is based on the power-on reset signal PR based on whether or not a predetermined value is written in the power-on reset check area 30. The value to be written is “0x5A”. Not limited. In order to prevent erroneous recognition, for example, it may be determined whether or not the reset signal R is based on the power-on reset signal PR by writing a value of several bytes instead of one byte.

  In the above embodiment, the flash memory 14 stores the management information 40. However, a configuration may be adopted in which a nonvolatile memory or the like connected to the interface unit 12 is provided separately from the flash memory and the management information 40 is stored in the nonvolatile memory or the like.

  In the above embodiment, the memory check process has been described as a process for checking whether or not the data stored in the flash memory 14 can be read correctly. In addition to this, it is determined whether or not the data can be written correctly. You may perform the process to test | inspect.

  In the third embodiment, the description has been given of the configuration in which one of the first mode processing and the second mode processing is selected depending on whether the number of accesses to all blocks exceeds the fifth access threshold TA5. . However, the present invention is not limited to this, and the first mode process or the second mode process may be selected depending on whether there is a block whose access count exceeds a predetermined threshold. Alternatively, the user may select any mode after power-on of the information processing apparatus 10 and execute any processing according to the selection. Alternatively, the user's selection may be stored in a register in the interface unit 12 in advance, and the mode may be determined by referring to this after the power is turned on.

10 Information processing apparatus 11 CPU
12 Interface unit 13 RAM
14 Flash memory 15 CPU bus 16 Power-on reset generation unit 17 OR gate 18 Internal reset generation unit 20 Error detection correction unit 21 Status register 22 Memory check area specification register 30 Power-on reset check area 31 Page / block information 40 Management information

Claims (10)

A memory control device that performs data write or read control on a memory,
An interface unit connected to the memory and writing or reading the data to or from the memory;
A storage unit for storing, as block access number information, the number of times data is read for each of a plurality of blocks constituting the memory;
Based on the block access count information, a control unit that performs a refresh process on a block in which the number of data reads exceeds a first threshold among the plurality of blocks of the memory;
A memory control device comprising:   Based on the block access count information, the control unit performs a memory check process on a block in which the number of data reads out of the plurality of blocks of the memory is less than or equal to the first threshold and greater than a second threshold. The memory control device according to claim 1, wherein: The memory check process includes an error detection process for generating information indicating the number of error bits by performing error detection on the data read from the memory,
The memory control device according to claim 2, wherein the control unit performs the refresh process on a block including data in which the number of error bits exceeds a predetermined error threshold among the plurality of blocks. . A first reset signal generator for generating a first reset signal in response to power-on;
A second reset signal generator for generating a second reset signal in response to the reset request;
An initialization signal supply unit that sends the first reset signal or the second reset signal to the interface unit as an initialization signal that initializes the write or read control information of the interface unit;
Have
The control unit determines whether the initialization signal is based on the first reset signal after the control information of the interface unit is initialized according to the initialization signal. When it is determined that the data is based on one reset signal, the number of times the data is read from each block of the memory exceeds the first threshold value or the second threshold value based on the block access frequency information. 4. The memory control device according to claim 2, wherein a determination is made as to whether or not the memory control device is present. The storage unit includes a storage area for storing a power-on reset code indicating that the first initialization signal after power-on has been sent.
The control unit determines whether the power-on reset code is stored in the storage area according to the initialization signal, and determines that the power-on reset is stored in the register when it is determined that the code is not stored. 5. The memory control device according to claim 4, wherein a completed code is written and it is determined that the initialization signal is based on the first reset signal. A first mode in which the refresh process or the memory check process is performed according to the number of times of reading the data;
A second mode for performing the memory check processing on each block of the memory regardless of the number of times of reading the data;
With
The control unit selects one of the first mode and the second mode based on the block access count information, and executes the memory check process or the refresh process. Item 6. The memory control device according to any one of Items 2 to 5.   7. The interface unit according to claim 1, wherein the interface unit writes management information including the block access information into the memory, reads the management information from the memory in response to power-on, and stores the management information in the storage unit. The memory control device according to any one of the above.   The memory control device according to claim 7, wherein the interface unit writes the block access information to the memory when the number of times of reading data for all the blocks of the memory exceeds a third threshold. .   The interface unit writes the block access information into the memory when the number of times of reading for a block from which data has been read out of a plurality of blocks of the memory exceeds a fourth threshold value. The memory control device according to claim 7. A memory control method for performing data write or read control on a memory,
Storing the number of read times of data for each of a plurality of blocks constituting the memory as block access number information;
Performing a refresh process on a block in which the number of read times of data exceeds a first threshold among the plurality of blocks of the memory based on the block access count information;
A memory control method comprising:

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