JP2011055390A - Burst signal receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a burst signal receiver capable of separating a burst signal of 1 GbE from a burst signal of 10 GbE. <P>SOLUTION: In order to solve the above problem, this burst signal receiver 91 includes a separation section 12 for separating a high-speed burst signal from a low-speed burst signal using a preamble signal included in the beginning of a burst signal. The preamble signal is included in the beginning of the burst signal, and thereby used for a set signal, the end of a total burst zone from a total burst zone determination section 11 is used for a reset signal, a high-speed burst zone determination section 13 determines a high-speed burst zone, and a low-speed zone determination section 14 determines a low-speed burst zone. Thereby, a burst signal of 1 GbE being a low-speed burst signal can be separated from a burst signal of 10 GbE being a high-speed burst signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a burst signal receiver that receives burst signals, and more particularly, to a burst signal receiver that receives burst signals of both 1 GbE (Gigabit Ethernet (registered trademark)) and 10 GbE transmission rates.

  At present, in Japan, 1 GbE GE-PON (Gigabit Ethernet (registered trademark) -Passive Optical Network) as shown in FIG. 6 is generally installed. In 1GbE GE-PON, a plurality of 1G-ONUs (Optical Network Units) 52 are connected to a 1G-OLT (Optical Line Terminal) 54 through a WDM (Wavelength Division Multiplexing) filter 53, and a plurality of G1 S1 (Serial 1) (Serialize & Desalize) 51 and 1G Sades 55 transmit and receive burst-like variable length signals (hereinafter referred to as burst signals).

  In the future, as the amount of information increases, broadband and transmission capacity are expected to increase, and it is considered that 10 GbE GE-PON having a transmission speed of 10.3125 Gbps will be generalized. At present, since a 1 GbE GE-PON having a transmission rate of 1.25 Gbps has already been constructed, it is desirable to use the installed GE-PON as it is.

  As a method of utilizing the installed GE-PON, as shown in FIG. 7, a burst signal receiver 58 that receives both burst signals of 1 GbE and 10 GbE is used instead of the 1G-OLT 54 shown in FIG. There is a way.

  On the other hand, a burst signal receiver that receives a high-speed burst signal and a low-speed burst signal by reading a header using a burst signal with a low transmission rate as a basic rate has been proposed (see, for example, Patent Document 1).

JP 2009-17324 A

  An example of 1 GbE and 10 GbE burst signals is shown in FIG. FIG. 8A shows a case where the 10 GbE burst signal is 1, 0 alternating, and FIG. 8B shows a case where the 10 GbE burst signal is a PRBS (Pseudo Random Bit Stream) 31 signal, and FIG. Indicates a case where the 1 GbE burst signal is alternating between 1 and 0. Since a signal of a band of about 0.33 Gbit / s is present in the PRBS31 signal in a burst signal of 10 GbE, as shown in FIGS. 8B and 8C, depending on the filtering by the frequency filter, 1 GbE is required. It is impossible to separate the burst signal of 10 GbE and the burst signal of 10 GbE.

  Further, since the transmission speed of the header is different between 1 GbE and 10 GbE, the burst signal receiving method proposed in the cited document 1 cannot be applied.

  Although it is conceivable to separate the 1 GbE burst signal and the 10 GbE burst signal using the enable signal, at present, there is no method for generating the enable signal.

  Therefore, an object of the present invention is to provide a burst signal receiver capable of separating a 1 GbE burst signal and a 10 GbE burst signal.

  The 10 GbE burst signal, which is a high-speed burst signal, and the 1 GbE burst signal, which is a low-speed burst signal, have different code intervals of alternating codes included in the preamble signal. Utilizing this, the burst signal receiver of the present invention is characterized by separating a high-speed burst signal and a low-speed burst signal. Since the preamble signal is included at the head of the burst signal, the separated preamble signal is used as the set signal. The end of all burst sections is used as a reset signal. Accordingly, it is possible to determine a high-speed burst section that is a section of a high-speed burst signal and a low-speed burst section that is a section of a low-speed burst signal. Therefore, a 1 GbE burst signal that is a low-speed burst signal and a 10 GbE burst signal that is a high-speed burst signal can be separated.

  Specifically, the burst signal receiver of the present invention is a burst signal receiver that receives a high-speed burst signal and a low-speed burst signal, and includes all bursts including the high-speed burst signal and the low-speed burst signal. An all-burst section determination unit that detects the start and end of the signal and determines all burst sections, which are all burst signal sections, and at least a part of the preamble signal from all burst signals, and a 1,0 alternating code And a separation unit that separates the extracted part in accordance with a transmission rate, and a head of a high-speed preamble signal separated by the separation unit is used as a set signal, A high-speed burst section for determining a high-speed burst section, which is a section of the high-speed burst signal, using the end of all burst sections as a reset signal Using the beginning of the low-speed preamble signal separated by the determination unit and the separation unit as a set signal, and using the end of the entire burst interval from the all-burst interval determination unit as a reset signal, the low-speed burst signal interval And a low-speed burst section determination unit for determining a low-speed burst section.

  The separation unit separates and outputs the high-speed preamble signal and the low-speed preamble signal. An output signal from the separation unit is used as a set signal. Then, the end of each burst section determination unit is used as a reset signal. By using the high-speed burst section and the low-speed burst section obtained in this way, it is possible to separate the 1 GbE burst signal that is a low-speed burst signal and the 10 GbE burst signal that is a high-speed burst signal.

In the burst signal receiver of the present invention, the separation unit detects a head of the entire burst section from the all burst section determination unit, and when a signal is input from the rising differentiation circuit, It is preferable to include a gate circuit that allows all burst signals to pass through and a plurality of frequency filters that separate the preamble signal from the gate circuit for each frequency according to the transmission speed.
According to the present invention, the separation unit can separate and output the high-speed preamble signal and the low-speed preamble signal.

In the burst signal receiver of the present invention, when all the burst signals are input and a signal from the high-speed burst section determination unit is input, a high-speed burst signal extraction unit that passes the input burst signal; It is preferable to further include a low-speed burst signal extraction unit that allows an input burst signal to pass when all burst signals are input and a signal from the low-speed burst section determination unit is input.
By providing a low-speed burst signal extraction unit, a low-speed burst signal can be extracted. By providing a high-speed burst signal extraction unit, a high-speed burst signal can be extracted. Therefore, it is possible to receive a 1 GbE burst signal that is a low-speed burst signal and a 10 GbE burst signal that is a high-speed burst signal.

  The above inventions can be combined as much as possible.

  According to the present invention, a 1 GbE burst signal that is a low-speed burst signal and a 10 GbE burst signal that is a high-speed burst signal can be separated.

It is a block diagram which shows an example of the burst signal receiver which concerns on this embodiment. It is an example of the signal which concerns on this embodiment, (a) shows the input signal to a burst signal receiver, (b) shows the output signal from all the burst area determination parts, (c) shows from a separation part. A high-speed preamble signal is shown, (d) is an output signal from the high-speed burst section determination unit, (e) is a low-speed preamble signal from the separation unit, and (f) is an output from the low-speed burst section determination unit Signals are shown. It is a block diagram which shows an example of a isolation | separation part. It is an example of the signal which concerns on a isolation | separation part, (a) shows the input signal to a burst signal receiver, (b) shows the output signal from all the burst area determination parts, (c) is from a rising differentiation circuit. The differential signal SDT is shown, (d) shows the output signal from the gate circuit, (e) shows the output signal from the high-pass filter, and (f) shows the output signal from the low-pass filter. 1 is a configuration diagram illustrating an example of a burst signal receiver according to Embodiment 1. FIG. An example of the conventional GE-PON is shown. An example of GE-PON using an installed optical fiber is shown. An example of 1 GbE and 10 GbE burst signals is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

  FIG. 1 is a configuration diagram illustrating an example of a burst signal receiver according to the present embodiment. The burst signal receiver 91 shown in FIG. 1 includes an OLT unit 95 and a sades unit 96. The OLT unit 95 generates a high speed SD (Signal Detect) signal SDH and a low speed SD signal SDL from all burst signals SGA including the high speed burst signal SGH and the low speed burst signal SGL shown in FIG. The result is output to the sardice unit 96. Here, the high-speed SD signal is a signal indicating a high-speed burst interval, and the low-speed SD signal is a signal indicating a low-speed burst interval. Then, the saddes unit 96 acquires all the burst signals SGA, the high-speed SD signal SDH, and the low-speed SD signal SDL, and receives the high-speed burst signal SGH and the low-speed burst signal SGL, respectively.

  The OLT unit 95 includes, for example, an all burst section determination unit 11, a separation unit 12, a high speed burst section determination unit 13, and a low speed burst section determination unit 14. The Sardes unit 96 includes a high-speed burst signal extraction unit 16 and a low-speed burst signal extraction unit 17.

  The all burst section determination unit 11 detects the beginning and end of all burst signals SGA, determines all burst sections that are all burst signal sections, and displays all burst sections as shown in FIG. All SD signals SDA indicating intervals are generated. The all burst section determination unit 11 uses a circuit that detects and outputs a signal input.

  The separation unit 12 extracts a part including at least a part of the preamble signal and including the 1, 0 alternating code from all the burst signals SGA, and separates the extracted part according to the transmission rate. For example, the preamble signal PRH included in the high-speed burst signal and the preamble signal PRL included in the low-speed burst signal are separated. Then, the preamble signal PRH and the preamble signal PRL are output from different output terminals.

  Here, at least a part of the preamble signal including the 1,0 alternating code may include a part other than the 1,0 alternating code in the preamble, but only the 1,0 alternating code is extracted. It is preferable to do. Furthermore, it is preferable that the 1, 0 alternating is continuous to such an extent that a stable frequency can be obtained.

FIG. 3 shows an example of the separation unit. The separation unit 12 includes a rising differentiation circuit 21, a gate circuit 22, a high pass filter 23, and a low pass filter 24.
The rising differentiation circuit 21 detects the head of all burst sections from the all burst section determination unit 11. For example, the rising edge of all SD signals SDA is detected. And the differential signal SDT as shown in FIG.4 (c) is output. Here, the section of the differential signal SDT includes a section in which a preamble signal including 1, 0 alternatings can be extracted.

  The gate circuit 22 passes all burst signals SGA when the differential signal SDT is input from the rising differential circuit 21. For example, using the differential signal SDT as an enable signal, all burst signals SGA are allowed to pass only during the differential signal SDT. Here, since the preamble signal is included in the head portion of the burst signal, by extracting the head portion of the burst signal, the gate circuit 22 has a plurality of transmission rates as shown in FIG. It is possible to output a signal PRA obtained by extracting a preamble signal included in the head portion of the burst signal.

  The high-pass filter 23 and the low-pass filter 24 separate the preamble signal from the gate circuit 22 for each frequency according to the transmission speed. For example, the high-pass filter 23 is higher than the frequency of the 1, 0 alternating code of the preamble signal included in the low-speed burst signal SGL and equal to or higher than the frequency of the 1, 0 alternating code of the preamble signal included in the high-speed burst signal SGH. Let the frequency pass. On the other hand, the low-pass filter 24 is lower than the frequency of the 1, 0 alternating code of the preamble signal included in the high-speed burst signal SGH and is equal to or lower than the frequency of the 1, 0 alternating code of the preamble signal included in the low-speed burst signal SGL. Let the frequency pass.

  In particular, when the high-speed burst signal is a 10 GbE burst signal and the low-speed burst signal is a 1 GbE burst signal, the high-pass filter 23 passes a frequency of 1.3 GHz or more, and the low-pass filter 24 is 1.25 GHz or less. It is preferable to pass the frequency.

  The high-speed burst section determination unit 13 uses the head of the high-speed preamble signal PRH separated by the separation unit 12 as a set signal, and uses the end of all SD signals SDA indicating all burst sections from all burst section determination units 11 as a reset signal. The high-speed burst signal, which is the high-speed burst signal, is determined, and the high-speed SD signal SDH indicating the high-speed burst signal is output. For example, using a latch circuit, a signal that is “High” is generated from the beginning of the preamble signal PRL shown in FIG. 2C to the end of the high-speed SD signal SDH and the low-speed SD signal SDL shown in FIG. . Thereby, the high-speed SD signal SDH as shown in FIG. 2D can be generated.

  The low-speed burst interval determination unit 14 uses the beginning of the low-speed preamble signal separated by the separation unit 12 as a set signal, and uses the end of all SD signals SDA indicating all burst intervals from the all-burst interval determination unit 11 as a reset signal. Thus, the low-speed burst section that is the low-speed burst signal section is determined, and the low-speed SD signal SDL indicating the low-speed burst section is output. For example, using a latch circuit, a signal that is “High” is generated from the beginning of the preamble signal PRL shown in FIG. 2E to the end of the high-speed SD signal SDH and the low-speed SD signal SDL shown in FIG. . Thereby, the low-speed SD signal SDL as shown in FIG. 2F can be generated.

  The high-speed burst signal extraction unit 16 allows the input burst signal to pass when all burst signals SGA are input and the signal from the high-speed burst section determination unit 13 is input. The timing at which the burst signal input to the burst signal receiver 91 is input to the high-speed burst signal extraction unit 16 and the timing at which the high-speed SD signal SDH from the high-speed burst section determination unit 13 is input to the high-speed burst signal extraction unit 16 , The high-speed burst signal SGH can be extracted from all the burst signals SGA input to the burst signal receiver 91.

  The low-speed burst signal extraction unit 17 allows the input burst signal to pass when all the burst signals SGA are input and the signal from the low-speed burst section determination unit 14 is input. The timing at which the burst signal input to the burst signal receiver 91 is input to the low-speed burst signal extraction unit 17 and the timing at which the low-speed SD signal SDL from the low-speed burst section determination unit 14 is input to the low-speed burst signal extraction unit 17 Can be extracted from all the burst signals SGA inputted to the burst signal receiver 91.

  FIG. 5 is a configuration diagram illustrating an example of the burst signal receiver according to the first embodiment. All burst signals SGA including 10 GbE high-speed burst signal SGH and 1 GbE low-speed burst signal SGL are input to burst signal receiver 191, and 10 GbE high-speed burst signal SGH and 1 GbE low-speed burst signal SGL are received. To do.

  In this embodiment, 10G_PA111 is provided as the entire burst section determination unit 11 shown in FIG. 1, a rising differentiation circuit 121 is provided as the rising differentiation circuit 21, 10G_PA122 is provided as the gate circuit 22, and a highpass filter 123 is provided as the highpass filter 23. The low-pass filter 124 is provided as the low-pass filter 24, the latch circuit 113 is provided as the high-speed burst section determination unit 13, the latch circuit 114 is provided as the low-speed burst section determination unit 14, and the high-speed burst signal extraction unit 16 and the low-speed burst signal extraction unit 17 are provided. An integrated sades 144 is provided.

  10G_PA111, 10G_PA122, and 10G_PA131 are 10GbE compatible amplifiers, and their frequencies are, for example, 0 Hz or more and 10.7 GHz. 10G_PA111 and 10G_PA122 receive all burst signals SGA and output all SD signals SDA. Therefore, in this embodiment, the supply of all SD signals SDA to the rising differentiation circuit 121 and the supply of all SD signals SDA to the latch circuit 113 and the latch circuit 114 use all SD signals SDA output from different amplifiers. Yes.

  The 10G_PA 111 outputs a signal obtained by amplifying all the input burst signals SGA and outputs all SD signals SDA. The rising differentiation circuit 121 detects the rising of all SD signals SDA from 10G_PA 111 and outputs a differential signal SDT. The 10G_PA 122 receives the differential signal SDT from the rising differentiation circuit 121 as an enable signal, and outputs a signal PRA obtained by extracting the preamble signal included in the head portion of all the burst signals SGA from the 10G_PA 111.

  The high-pass filter 123 extracts the preamble signal included in the high-speed burst signal from the signal PRA from the 10G_PA 122, and outputs the high-speed preamble signal PRH. The latch circuit 113 determines the high-speed burst period by using the head of the high-speed preamble signal PRH as a set signal and the end of all SD signals SDA from 10G_PA 122 as a reset signal, and outputs the high-speed SD signal SDH. The high-speed SD signal SDH is input to the integrated sades part 144 through the electrical interface 142.

  The low-pass filter 124 extracts a preamble signal included in the low-speed burst signal from the signal PRA from the 10G_PA 122, and outputs a low-speed preamble signal PRL. The latch circuit 114 uses the beginning of the low-speed preamble signal PRL as a set signal, uses the end of all SD signals SDA from the 10G_PA 122 as a reset signal, determines the low-speed burst period, and outputs the low-speed SD signal SDL. The low-speed SD signal SDL is input to the integrated sades unit 144 via the electrical interface 143.

  The 10G_PA 131 amplifies all burst signals SGA input from the 10G_PA 111 and outputs the amplified burst signals SGA to the integrated sades unit 144 via the electrical interface 141. The integrated cerdes 144 receives all burst signals from the electrical interface 141, receives the high-speed SD signal SDH from the electrical interface 142, and receives the low-speed SD signal SDL from the electrical interface 143. Using the high-speed SD signal SDH and the low-speed SD signal SDL as enable signals, the integrated cerdes 144 can individually perform 1 GbE reception processing and 10 GbE reception processing. As described above, the burst signal receiver 191 can receive 1 GbE reception processing and 10 GbE.

  Since this generation receives a burst signal, it can be applied to the information communication industry.

11: All burst section determination section 12: Separation section 13: High speed burst section determination section 14: Low speed burst section determination section 16: High speed burst signal extraction section 17: Low speed burst signal extraction section 21, 121: Rise differentiation circuit 22: Gate circuit 23, 123: High-pass filter 24, 124: Low-pass filter 51, 55: 1G Sades 52: 1G-ONU
53: WDM filter 54: 1G-OLT
56, 59: 10G Sades 57: 10G-ONU
58: 1G / 10G dual rate OLT
91, 191: Burst signal receiver 95, 195: OLT unit 96, 196: Sardes unit 111, 122, 131: 10G_PA
113, 114: Latch circuit 144: Integrated Serdes

Claims (3)

A burst signal receiver for receiving a high-speed burst signal and a low-speed burst signal,
An all burst section determination unit that detects the start and end of all burst signals including the high-speed burst signal and the low-speed burst signal, and determines all burst sections that are sections of the all burst signals;
A separation unit that extracts at least a part of a preamble signal including a 1, 0 alternating code from all the burst signals, and separates the extracted part according to a transmission rate;
A high-speed burst that is a section of the high-speed burst signal is obtained by using a head of a high-speed preamble signal separated by the separation section as a set signal and using a tail of the burst section from the all-burst section determination section as a reset signal. A high-speed burst section determination unit for determining a section;
A low-speed burst that is a section of the low-speed burst signal is obtained by using a head of a low-speed preamble signal separated by the separation section as a set signal and using a tail of the burst section from the all-burst section determination section as a reset signal. A low-speed burst section determination unit for determining a section;
A burst signal receiver. The separation unit is
A rising differentiating circuit for detecting a head of all burst sections from the all burst section determination unit;
A gate circuit that passes all the burst signals when a signal is input from the rising differentiation circuit;
A plurality of frequency filters for separating the preamble signal from the gate circuit for each frequency according to a transmission rate;
The burst signal receiver according to claim 1, further comprising: When all the burst signals are input and a signal from the high-speed burst section determination unit is input, a high-speed burst signal extraction unit that passes the input burst signal;
When all the burst signals are input and a signal from the low-speed burst section determination unit is input, a low-speed burst signal extraction unit that passes the input burst signal;
The burst signal receiver according to claim 1, further comprising:

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