JP2011054897A - Thin film transistor and display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor capable of reducing a defect generated in a film of the thin-film transistor and also reducing variations in a defect generation position in a substrate plane, and to provide a display device using the same. <P>SOLUTION: The thin-film transistor includes a semiconductor layer where a drain region and a source region are formed, a silicon oxide film layer formed under the semiconductor layer and preventing an impurity from being mixed with the semiconductor layer, and a silicon nitride film layer formed under the silicon oxide film layer and preventing an impurity from being mixed with the semiconductor layer together with the silicon oxide film layer, wherein the silicon oxide film layer includes a first silicon oxide film interface layer formed over the silicon nitride film layer, a silicon oxide film bulk layer formed over the first silicon oxide film, and a second silicon oxide film interface layer formed over the silicon oxide film bulk layer, the first silicon oxide film interface layer includes a silicon oxide nitride film, and the second silicon oxide film interface layer includes an oxygen-deficit silicon oxide nitride film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a display device, and more particularly to a display device in which characteristics of thin film transistors arranged in a matrix in an electronic device such as a liquid crystal display are stabilized.

  A thin film transistor (hereinafter abbreviated as “TFT”) substrate used as a driving circuit for a liquid crystal display panel or the like has a display defect if the TFT characteristics on the same panel vary. The TFT characteristics that influence the performance of the liquid crystal display include a current during TFT operation (ON current), a current during TFT non-operation (OFF current), a threshold voltage (hereinafter referred to as Vth), and the like. A TFT panel used for an image device has TFTs arranged in an array like a semiconductor memory element. However, unlike a memory, individual TFT characteristics arranged in an array directly affect the image quality. Therefore, all TFTs in the same panel are required to have the same characteristics, and variations in TFT characteristics need to be minimized.

  In particular, recently, a glass substrate used for manufacturing a liquid crystal panel has been increased in size, and the uniformity of TFT characteristics within the substrate surface has become an issue. As a technique for making the TFT characteristics in the substrate surface uniform, there is a method of manufacturing a thin film transistor described in Patent Document 1. In the technique described in this original document 1, a channel layer is formed by two layers of microcrystalline silicon and amorphous silicon, thereby reducing characteristic fluctuations such as threshold voltage.

JP 2007-5508 A

  The technique described in Patent Document 1 is a method for suppressing variations in a method for manufacturing an inverted staggered thin film transistor by forming a light-heat conversion film and a buffer layer and microcrystallizing the underlying amorphous silicon layer with a laser. Is disclosed.

  However, in the technique described in Patent Document 1, the light-heat conversion film and the buffer layer once formed must be removed after silicon microcrystallization, and there is a concern that the process becomes complicated.

  Further, one of the causes that cause the Vth variation of the TFT is a defect in the film. It is known that if there is a defect in the film, it becomes a fixed charge and causes a Vth shift. However, even if a defect occurs in the film constituting the TFT, if the defect exists uniformly in the substrate surface, the Vth shift occurs uniformly in the substrate surface. It is considered that there is no variation.

  The present invention has been made in view of these problems, and an object of the present invention is to reduce defects generated in the thin film transistor film and to reduce variations in defect occurrence positions in the substrate surface. It is an object to provide a thin film transistor and a display device using the same.

  (1) In order to solve the above problem, a semiconductor layer in which a drain region and a source region are formed, a silicon oxide film layer formed under the semiconductor layer to prevent impurities from being mixed into the semiconductor layer, and the silicon A thin film transistor including a silicon nitride film layer that is formed under the oxide film layer and prevents impurities from entering the semiconductor layer together with the silicon oxide film layer, wherein the silicon oxide film layer is formed of the silicon nitride film layer. A first silicon oxide film interface layer formed as an upper layer; a silicon oxide film bulk layer formed as an upper layer of the first silicon oxide film; and a second layer formed as an upper layer of the silicon oxide film bulk layer. The first silicon oxide film interface layer is made of a silicon oxynitride film, and the second silicon oxide film interface layer is an oxygen deficient silicon layer. A thin film transistor made of an oxide film.

  (2) In order to solve the above-described problem, a plurality of video signal lines, a plurality of scanning signal lines intersecting with the video signal lines, and a scanning signal from the scanning signal line are used to output the video signal lines. And a thin film transistor according to (1) that controls the capture of the video signal, and a region surrounded by the video signal line and the scanning signal line is a pixel device.

  According to the present invention, it is possible to reduce defects generated in the thin film transistor film and to reduce variations in defect occurrence positions in the substrate surface.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is sectional drawing for demonstrating the whole structure of the thin-film transistor of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the thin-film transistor of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the thin-film transistor of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the thin-film transistor of Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing method of the thin-film transistor of Embodiment 1 of this invention. It is a figure which shows the evaluation result of the defect (unpaired electron) in a film | membrane in the silicon oxide film in the conventional thin-film transistor. It is a figure which shows the evaluation result of the defect (unpaired electron) in a film | membrane in the silicon oxide film in the thin-film transistor of Embodiment 1 of this invention. It is a top view for demonstrating schematic structure of the liquid crystal display device of Embodiment 3 of this invention.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

<Embodiment 1>
FIG. 1 is a cross-sectional view for explaining the overall configuration of the thin film transistor of Embodiment 1 of the present invention. Hereinafter, the configuration of the thin film transistor of Embodiment 1 will be described with reference to FIG. However, in the following description, only the configuration of the silicon nitride film and the silicon oxide film, which are the base protective layer formed between the glass substrate and the semiconductor layer, is different, and the configuration of the other thin film layers is the same as the conventional configuration. It becomes. Therefore, in the following description, the structure of the base protective layer will be described in detail.

  As shown in FIG. 1, the thin film transistor of Embodiment 1 has a configuration in which a silicon nitride film 2 is formed on a glass substrate 1. A silicon oxide film 3 according to the present invention is formed on the silicon nitride film 2. In the thin film transistor of the first embodiment, by forming a base protective layer composed of the silicon nitride film 2 and the silicon oxide film 3, Na (sodium) or K ( It is configured to prevent mixing of ions such as potassium). Furthermore, the silicon oxide film 3 of the first embodiment is composed of three layers of thin films formed so as to cover the upper surface of the silicon nitride film 2, and in order from the upper layer side of the silicon nitride film 2, that is, the transparent substrate 1 side, A silicon oxide film lower layer interface layer (first silicon oxide film interface layer) 3a, a silicon oxide film bulk layer 3b, and a silicon oxide film upper layer interface layer (first silicon oxide film interface layer) 3c are formed. Yes. The detailed structure of the silicon oxide film 3 of the first embodiment will be described in detail later.

  Further, a source region 4, a drain region 5, and a channel region 6 made of a polycrystalline silicon layer are formed on the silicon oxide film 3. In other words, the thin film transistor of Embodiment 1 has a configuration in which a polycrystalline silicon layer serving as a semiconductor layer of the top gate type thin film transistor is formed on the silicon oxide film 3. In this polycrystalline silicon layer, the source region 4 is formed in one of the channel regions 6 and the drain region 5 is formed in the other so that the channel region 6 is sandwiched in the plane direction of the glass substrate 1. It has a configuration.

  A gate insulating film 7 is formed so as to cover the source region 4, the drain region 5, and the channel region 6, and a gate region 8 is formed at a position corresponding to the channel region 6 on the upper layer. An interlayer insulating layer 9 is formed so as to cover a part. That is, the gate insulating film 7 that functions as a gate insulating film in the region of the semiconductor layer in which the source region 4, the drain region 5, and the channel region 6 are formed and covers the upper surface of the substrate so as to function as an insulating film in other regions. Is formed. A conductive thin film that becomes the gate region 8 is formed at a position corresponding to the channel region 6, which is an upper layer of the gate insulating film 7. Further, an interlayer insulating layer 9 that covers the gate insulating film 7 together with the gate region 8 is formed on the gate region 8. Note that a gate electrode connected to the gate region 8 is omitted.

  The source region 4, the drain region 5, and the gate region 8 are electrically connected by the respective electrodes 11 through the openings provided in the interlayer insulating layer 9. Note that the electrode connected to the gate region 8 in FIG. 1, that is, the gate electrode is not shown.

  Next, FIGS. 2 to 5 are diagrams for explaining the thin film transistor manufacturing method according to the first embodiment of the present invention. Hereinafter, the thin film transistor manufacturing method according to the first embodiment will be described with reference to FIGS. However, since the thin film layers can be formed by a well-known photolithography technique, detailed description thereof is omitted. Further, the manufacturing process of the silicon oxide film 3 shown below is related to the thin film forming process, the defects in the film, and the threshold voltage Vth of the thin film transistor, which the present inventor has discovered by analyzing the defects in the underlying silicon oxide film. Based on this, it is an example of a manufacturing process that can realize the reduction of the defects in the film and the fluctuation of the threshold voltage Vth accompanying the generation of the defects in the film.

Step 1. (Figure 2)
First, a silicon nitride film 2 having a thickness of 150 nm is formed on a glass substrate 1 by using a well-known plasma CVD (Chemical Vapor Deposition) method. For example, nitrogen, ammonia, or monosilane is used as the source gas for forming the silicon nitride film 2 in the step 1. The purpose of forming the silicon nitride film 2 is that impurities, for example, sodium ions contained in the glass substrate 1 diffuse into the semiconductor layer of the thin film transistor formed on the upper surface of the transparent substrate 1, causing a shift of the threshold voltage Vth and the like. This is to prevent this.

Step 2. (Figure 3)
Next, the source gas type is switched to form a silicon oxide film 3 having a thickness of 100 nm. In forming the silicon oxide film 3, in the first embodiment, first, the amount of nitrogen and ammonia, which are the raw material gases of the silicon nitride film, is reduced, and dinitrogen monoxide and argon are added together with the raw material gas of the silicon nitride film. Then, plasma is generated here to form a silicon oxide lower layer interface layer 3a having a thickness of 20 nm. At this time, the composition of the source gas in forming the silicon oxide film lower layer interface layer 3a is made constant, and the film composition is also made constant, so that the silicon oxide film lower layer interface layer 3a becomes a silicon oxynitride film.

  The formation of the silicon oxide film lower layer interface layer 3a stops the introduction of nitrogen and ammonia, which are the raw material gases of the silicon nitride film that have been continuously introduced, and increases the flow rates of dinitrogen monoxide and argon, thereby dinitrogen monoxide. Then, plasma is generated using argon, monosilane, and a silicon oxide bulk layer 3b having a thickness of 60 nm is formed.

  Next, after reducing the amount of dinitrogen monoxide introduced, plasma is generated to form a silicon oxide film upper interface layer 3c having a thickness of 20 nm, whereby the silicon oxide film upper interface layer 3c becomes an oxygen deficient silicon oxide film. It becomes.

  By this step 2, a silicon oxide film 3 having a thickness of 100 nm is formed as a whole silicon oxide film.

  Thus, in the formation of the silicon oxide film 3 in the thin film transistor of the first embodiment, the silicon nitride film 2, the silicon oxide film lower layer interface layer 3 a that forms the silicon oxide film 3, the silicon oxide film bulk layer 3 b, and the silicon oxide film upper layer When forming each thin film layer to be the interface layer 3c, the next thin film layer (desired) is left in a state where a predetermined amount of the raw material gas (gas species) for forming the thin film layer disposed in the lower layer is left (introduced). The upper thin film layer is sequentially formed while introducing the raw material gas for forming the thin film layer. That is, when the next thin film layer is formed, the raw material gas used for forming the lower thin film layer is completely shut off, and the next thin film layer is formed without replacing the raw material gas in the chamber of the manufacturing apparatus. It has a configuration.

  By the step of forming the silicon oxide film 3 of the first embodiment, it is possible to reduce defects in the silicon oxide film lower layer interface layer 3a and the silicon oxide film upper layer interface layer 3c as compared with the silicon oxide film bulk layer 3b.

Step 3. (Fig. 4)
In the formation of the polycrystalline silicon layer 10 after the formation of the silicon oxide film upper interface layer 3c, the introduction of dinitrogen monoxide during the formation of the silicon oxide film upper interface layer 3c is stopped. As a result, an amorphous silicon film is first formed using the plasma CVD method using only argon and monosilane as source gases and a processing temperature of 300 to 500 ° C. Next, the formed amorphous silicon film is made into a polycrystalline silicon film by excimer laser annealing, and a polycrystalline silicon layer 10 having a desired shape is formed through a photolithography process.

Step 4. (Fig. 5)
Next, after forming the gate insulating layer 7 with TEOS (Tetra Ethoxy Silane) so as to cover the polycrystalline silicon layer 10, a conductive film (for example, a metal thin film) is formed, and the conductive film is formed into a desired shape. The gate region 8 is formed by processing. Next, the source region 4 and the drain region 5 are formed by implanting the group 3b or 5b group ions into the polycrystalline silicon layer 10 using the gate region 8 as a mask. However, the implanted ion species may be selected depending on whether the thin film transistor (TFT) to be manufactured is an n-channel MOS or a p-channel MOS.

  After the source region 4 and the drain region 5 are formed, an interlayer insulating layer 9 made of a silicon oxide film is formed by plasma CVD at 300 to 500 ° C., and the source region 4 and the drain region 5 are formed from the upper surface side of the interlayer insulating film 9. A reaching opening is formed. Thereafter, a conductive thin film is formed on the interlayer insulating film 9 including the opening, and the thin film is formed into a desired shape, whereby the source electrode which is the electrode 11 electrically connected to the source region 4 Then, a drain electrode which is an electrode 11 electrically connected to the drain region 5 is formed, and the thin film transistor shown in FIG. 1 is formed.

<Description of effects>
In the thin film transistor of Embodiment 1 formed in this manner, when forming the silicon oxide film lower layer interface layer, dinitrogen monoxide and argon are introduced together with the source gas of the silicon nitride film formed in the lower layer. Since it is formed, the silicon oxide lower layer interface layer becomes a silicon oxynitride film. Similarly, when forming the upper interface layer of the silicon oxide film, the amount of dinitrogen monoxide introduced in the source gas of the silicon oxide bulk layer formed in the lower layer is dinitrogen monoxide and argon. Since it is formed after the reduction, the silicon oxide upper interface layer becomes an oxygen-deficient silicon oxide film.

  Thereby, defects in the silicon oxide film lower layer interface layer and the silicon oxide film upper layer interface layer can be reduced as compared with the silicon oxide film bulk layer, and as a result, variations in the threshold voltage Vth of the thin film transistor can be reduced.

  Next, FIG. 6 is a view showing the evaluation results of defects (unpaired electrons) in the silicon oxide film in the conventional thin film transistor, and FIG. 7 is in the film in the silicon oxide film in the thin film transistor of Embodiment 1 of the present invention. The figure which shows the evaluation result of a defect (unpaired electron) is shown, and hereafter, the defect in a film in the conventional silicon oxide film and the defect in a film in the silicon oxide film of Embodiment 1 are demonstrated based on FIG.6 and FIG.7. To do. However, the evaluation of defects in the film in FIGS. 6 and 7 is performed by evaluating unpaired electrons as defects in the silicon oxide film by a well-known electron spin resonance method (hereinafter referred to as ESR). That is, the evaluation object is an unpaired electron on a silicon atom to which three oxygen atoms are bonded, and is a defect called an Eγ ′ center. Further, in order to investigate the distribution of the Eγ ′ centers in the film, ESR was measured while removing the upper film in order by etching.

  In the formation of a silicon oxide film in a conventional thin film transistor, after forming a silicon nitride film on a transparent substrate serving as a substrate, a gas species for forming the silicon oxide film is introduced, and the inside of the chamber is sufficiently filled with a silicon oxide film source gas. After the replacement, plasma was generated to form a film. Similarly, after the formation of the silicon oxide film is completed, a gas for forming the amorphous silicon layer is introduced, and after the chamber is sufficiently replaced with the amorphous silicon source gas, the amorphous silicon film is formed. Started. At this time, the upper and lower sides of the silicon oxide film, that is, the interface layer sandwiching the silicon oxide film is not formed.

  In the conventional silicon oxide film formed by such a process and the silicon oxide film of the first embodiment formed by the process described above, as is apparent from the comparison between FIG. 6 and FIG. It can be seen that there is a large difference in the density distribution.

  That is, in the conventional silicon oxide film shown in FIG. 6, the graph 62 of the film thickness indicated by the dotted line and the amount of defects is substantially proportional, and as is apparent from the graph 61 indicated by the solid line, the defects are uniformly present in the film. You can see that it exists. On the other hand, in the silicon oxide film 3 having the configuration of the first embodiment shown in FIG. 7, the silicon oxide film 3 is formed rather than the graph 72 of the film thickness and the amount of defects in the bulk layer (silicon oxide film bulk layer 3b) indicated by the dotted line. In the graph 73 shown by the dotted lines in the upper and lower interface layers (the silicon oxide film lower layer interface layer 3a and the silicon oxide film upper layer interface layer 3c), the inclination of the graph is gentler, and as is clear from the graph 71 shown by the solid line There are fewer defects than the silicon oxide bulk layer 3b.

  Further, when the transistor characteristics of the TFT including each of the silicon oxide films described above were examined, it was found that the TFT manufactured without providing the interface layer (the silicon oxide film lower layer interface layer 3a and the silicon oxide film upper layer interface layer 3c) The variation in the substrate surface was larger than that of a TFT manufactured by providing a layer.

  From the above, by providing the silicon oxide film lower layer interface layer 3a and the silicon oxide film upper layer interface layer 3c having fewer defects than the bulk layer (silicon oxide film bulk layer 3b), the variation in the threshold voltage Vth of the TFT can be reduced. It became clear that it could be reduced.

  In particular, in the mass production process, there is a possibility that the film formation parameters always fluctuate and uniformity in the plane cannot be ensured. On the other hand, by providing an interface layer composed of the silicon oxide film lower layer interface layer 3a and the silicon oxide film upper layer interface layer 3c, it is possible to supply TFTs with less fluctuation in characteristics with respect to variations in film formation parameters and non-uniformity. I found

As described above, the variation of the threshold voltage Vth of the thin film transistor is suppressed by devising the structure and manufacturing method of the silicon nitride film and the silicon oxide film, which are the base insulating layers formed between the glass substrate and the TFT. It becomes possible. In particular, when producing a top gate type low-temperature polycrystalline silicon TFT, it is necessary to form a silicon nitride film (SiN film) in order to suppress diffusion of mobile ions such as Na (sodium) from the glass substrate into the film. is there. However, since the silicon nitride film (SiN film) forms an interface state at the interface with the polycrystalline silicon layer (Si film), a silicon oxide film (SiO ₂ film) is formed above the silicon nitride film (SiN film). Further, by forming a polycrystalline silicon layer (Si film) as an active layer of the thin film transistor on the upper layer, it is possible to form a thin film transistor TFT in which the diffusion of mobile ions and the interface state are suppressed.

  Up to this point, the variation in the threshold voltage Vth of the thin film transistor TFT due to the variation in the film quality in the substrate surface caused by the nonuniformity of the atmosphere in the chamber during film formation cannot be eliminated. For example, in a CVD process when forming a silicon nitride film or silicon oxide film that serves as a base insulating layer (base protective layer), in-plane variations such as a source gas in a vacuum chamber and a substrate temperature have a threshold voltage Vth. Causes internal variation. On the other hand, the present inventor analyzed defects in the film and analyzed the behavior of unpaired electrons (called Eγ ′ center) of silicon in the silicon oxide film in the structure of silicon oxide film / silicon nitride film / glass substrate. It was discovered that variation in in-plane TFT characteristics can be suppressed by controlling the Eγ ′ center at the interface. Accordingly, the threshold voltage Vth characteristic variation of the thin film transistor can be reduced by reducing the amount of defects in the silicon oxide film at the silicon layer / silicon oxide film interface and the silicon oxide film / silicon nitride film interface. Suppress. This is because the defects at the interface affect the TFT characteristics more sensitively than in the film, and the variation in characteristics can be reduced by reducing the absolute amount of defects near the interface.

  On the other hand, the role of the underlying silicon oxide film is to suppress the interface state between the silicon nitride film and the polycrystalline silicon layer as described above. In order to maintain the optical characteristics when the liquid crystal panel or the like is maintained while ensuring the interface state suppressing effect, the base silicon oxide film 3 preferably has a thickness of about 50 to 100 nm. In particular, the thickness of the silicon oxide lower layer interface layer 3a is suitably about 5 to 30 nm. This makes it possible to obtain an effect of suppressing defects (Eγ ′) in the interface layer under the silicon oxide film without significantly increasing the film thickness of the entire silicon oxide film 3 and without losing the effect of suppressing the interface state. Because it becomes. Similarly, the film thickness of the silicon oxide film upper interface layer 3c is suitably about 5 to 30 nm.

<Embodiment 2>
The thin film transistor of the second embodiment is different from the thin film transistor of the first embodiment in the configuration of the silicon oxide film and the method for forming the silicon oxide film. That is, the thin film transistor of Embodiment 1 has a configuration in which the concentration of the source gas is not changed during the formation of the thin film layers of the silicon oxide film lower layer interface layer, the silicon oxide film bulk layer, and the silicon oxide film upper layer interface layer. In contrast, in the second embodiment, the silicon oxide film lower layer interface layer, the silicon oxide film bulk layer, and the silicon oxide film upper layer interface layer are formed while changing the concentration of the source gas during formation. Different.

  For this reason, the manufacturing method of the thin film transistor of Embodiment 2 is different only in Step 2 of the embodiment, and the explanatory diagram thereof is the same as FIG. Therefore, in the following, based on FIG. 3, the manufacturing method and the configuration of the thin film transistor of Embodiment 2 will be described.

  In the manufacturing method of the thin film transistor of the second embodiment, as in the first embodiment, a well-known plasma CVD (Chemical Vapor Deposition) method is used on the glass substrate 1, nitrogen and ammonia are used as source gases, and the thickness is 150 nm. A silicon nitride film 2 is formed.

  Next, after the silicon nitride film 2 is formed, the silicon oxide film is generated by gradually reducing the flow rates of nitrogen and ammonia and generating plasma while gradually increasing the flow rates of nitrogen monoxide and argon. Lower interface layer 3a is formed. When the silicon oxide film lower layer interface layer 3a is formed, if the film formation rate is high, the in-plane variation of the substrate increases. Therefore, the plasma power is adjusted so that the film formation rate decreases. Further, when the silicon oxide film lower layer interface layer 3a becomes 20 nm, the rate of reduction (reduction rate) of the flow rates of the nitrogen gas and ammonia is adjusted so that the introduction of the nitrogen gas and ammonia is stopped.

  After the formation of this silicon oxide film lower layer interface layer 3a, a silicon oxide film bulk layer 3b is subsequently formed with a thickness of 60 nm using nitrogen monoxide, argon, and monosilane. Thereafter, the silicon oxide film 3 having a thickness of 100 nm is formed by forming the silicon oxide film upper interface layer 3c having a thickness of 20 nm while continuously reducing the amount of introduced dinitrogen monoxide continuously.

  After the formation of the silicon oxide film 3, an amorphous silicon layer is formed using only argon and monosilane as source gases, and the amorphous silicon film is formed into a polycrystalline silicon film by excimer laser annealing, as in step 3 of the first embodiment. A polycrystalline silicon layer 10 having a desired shape is formed through a photolithography process.

  Thereafter, in the same manner as in step 4 of the first embodiment, the gate insulating layer 7 is formed by TEOS so as to cover the polycrystalline silicon layer 10 and processed into a desired shape, thereby forming the gate region 8. Next, after the 3b group or 5b group ion implantation is performed on the polycrystalline silicon layer 10 to form the source region 4 and the drain region 5, an interlayer insulating layer 9 made of a silicon oxide film is formed by plasma CVD. Next, after forming an opening reaching the source region 4 and the drain region 5 from the upper surface side of the interlayer insulating film 9, a conductive thin film is formed on the upper layer of the interlayer insulating film 9 including the opening. By forming the source electrode and the drain electrode having the shape, the thin film transistor of Embodiment 2 is formed.

In the silicon oxide lower layer interface layer 3a of the thin film transistor of Embodiment 2, the composition continuously changes from SiN to SiO ₂ , and in the silicon oxide upper layer interface layer 3c, SiO ₂ to SiO _2−δ (0 <δ <2). After that, the composition changes to Si. By providing an interface layer having such a composition gradient, distortion on the atomic bond is reduced, so that the generation of defects (unpaired electrons) due to dangling bonds in the film is suppressed, as in the thin film transistor of Embodiment 1. It is possible to form a thin film transistor TFT with little variation in the threshold voltage Vth.

<Embodiment 3>
In Embodiment 3 of the present invention, a liquid crystal display device using the thin film transistor of Embodiments 1 and 2 of the present invention will be described. FIG. 8 is a plan view for explaining a schematic configuration of the liquid crystal display device using the thin film transistor of Embodiment 1 of the present invention. However, the application range of the thin film transistor of the present invention is not limited to the liquid crystal display device. For example, the present invention can be applied to a thin film transistor in another display device such as an organic EL display device in which a plurality of light emitting elements are formed in a matrix on a transparent substrate.

  The liquid crystal display device according to the third embodiment shown in FIG. 1 includes a first substrate (TFT side substrate) 81 on which pixel electrodes and the like are formed, and a color filter (colored layer) and the like that are arranged to face the first substrate 81. A liquid crystal display panel is constituted by a second substrate (counter substrate) 82 to be formed and a liquid crystal layer (not shown) sandwiched between the first substrate 81 and the second substrate 82, and the liquid crystal display panel and a light source are shown. A liquid crystal display device can be obtained by combining with a backlight unit that does not. The first substrate 81 and the second substrate 82 are fixed (fixed) and the liquid crystal sandwiched between the two substrates 81 and 82 is fixed by a sealant 84 formed around the display region 83, and the liquid crystal Is also configured to be sealed. In the following description, the liquid crystal display panel is also referred to as a liquid crystal display device.

  The first substrate 81 and the second substrate 82 are not limited to known glass substrates that are transparent substrates, and may be other insulating substrates such as quartz glass and plastic (resin).

  In the liquid crystal display device of the third embodiment, the thin film transistor of the first embodiment is used as the thin film transistor 85, and a video signal drive circuit (drain driver) 86 is formed on the first substrate 81 in the lower part of the figure. A scanning signal driving circuit (gate driver) 87 is formed on the first substrate 81 on the middle left side. In the following description, the drain driver 86 and the gate driver 87 are simply abbreviated as a drive circuit (driver) when it is not necessary to distinguish between them.

  As shown in FIG. 1, in the liquid crystal display device according to the third embodiment, scanning is performed on the liquid crystal side surface of the first substrate 81 and in the display region 83, extending in the X direction in FIG. A line (gate line) 88 is formed. Further, a video signal line (drain line) 89 extending in the Y direction and juxtaposed in the X direction is formed.

  A rectangular region surrounded by the drain line 88 and the gate line 89 constitutes a region in which pixels are formed, whereby each pixel is arranged in a matrix in the display region 83. On the other hand, in the pixel region on the second substrate 82 side, any one of red (R), green (G), and blue (B) color filters (not shown) is formed. Further, the second substrate 82 has a configuration in which a black matrix and an alignment film in the extending direction of the gate lines 88 are formed.

  Further, each pixel has a thin film transistor 85 which is turned on by a scanning signal from the gate line 88 and a drain through the turned on thin film transistor 85 as shown in an enlarged view A ′ in a circle A in FIG. A pixel electrode 90 to which a video signal from a line 89 is supplied and a common electrode 92 connected to a common line 91 and supplied with a reference signal having a reference potential with respect to the potential of the video signal are provided. An electric field having a component parallel to the surface of the first substrate 81 is generated between the pixel electrode 90 and the common electrode 92, and liquid crystal molecules are driven by this electric field. Such a liquid crystal display device is known to be capable of so-called wide viewing angle display, and is referred to as an IPS system or a horizontal electric field system because of the peculiarity of application of an electric field to the liquid crystal.

  In the third embodiment, each drain line 89 and each gate line 88 extend beyond the sealing material 84 at the ends thereof and are connected to the drain driver 86 or the gate driver 87, respectively. Control signals including drive signals for the drain driver 86 and the gate driver 87 are input to the drain driver 86 and the gate driver 87 via a flexible printed circuit board (not shown) connected to the electrode terminal 93.

  Note that the configuration of the common electrode 92 shown in the enlarged view A ′ is not limited to the configuration described above. For example, the common electrode 92 of the pixels adjacently arranged in the X-axis direction is directly connected. The electrode 92 may be formed and a reference signal may be input from one end of the left and right (end portion of the first substrate 81) in the X-axis direction or from both sides via the common line 91.

  In the liquid crystal display device formed in this way, the thin film transistors 85 are arranged in a matrix on the liquid crystal side of the first substrate 81, but the variation of the threshold voltage Vth of each thin film transistor 85 in the substrate is reduced. Therefore, it is possible to prevent display quality deterioration such as display unevenness and to significantly reduce the number of liquid crystal display devices that cause display defects.

  However, even when the thin film transistor of the second embodiment is used, the same effect as that of the third embodiment can be obtained because the configuration is the same as that of the liquid crystal display device of the third embodiment.

  In the first and second embodiments, the case where the present invention is applied to the silicon oxide film of the top gate type thin film transistor has been described. However, the present invention is not limited thereto, and the present invention is applied to the gate oxide film of the bottom gate type thin film transistor. May be applied.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. It can be changed.

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Silicon nitride film, 3 ... Silicon oxide film 3a ... Silicon oxide film lower layer interface layer, 3b ... Silicon oxide film bulk layer 3c ... Silicon oxide film upper layer interface layer, 4 ... Source region, 5 ... Drain region 6 ... Channel region, 7 ... Gate insulating layer, 8 ... Gate region, 9 ... Interlayer insulating layer 10 ... Polycrystalline silicon layer, 11 ... Electrode, 81 ... First 1 substrate, 82 ... 2nd substrate 83 ... display area, 84 ... sealing material, 85 ... thin film transistor 86 ... video signal drive circuit, 87 ... scanning signal drive circuit, 88 ... gate line 89 ... video Signal line, 90... Pixel electrode, 91 ... common line, 92 ... common electrode 93 ... electrode terminal

Claims (9)

A semiconductor layer in which a drain region and a source region are formed; a silicon oxide film layer formed in a lower layer of the semiconductor layer to prevent entry of impurities into the semiconductor layer; and the semiconductor layer formed in a lower layer of the silicon oxide film layer A thin film transistor comprising a silicon nitride film layer for preventing impurities from being mixed into the layer together with the silicon oxide film layer,
The silicon oxide film layer includes a first silicon oxide film interface layer formed on the silicon nitride film layer, a silicon oxide bulk layer formed on the first silicon oxide film, and the silicon A second silicon oxide film interface layer formed on the oxide film bulk layer, and
A thin film transistor, wherein the first silicon oxide film interface layer is made of a silicon oxynitride film, and the second silicon oxide film interface layer is made of an oxygen-deficient silicon oxide film. The thin film transistor according to claim 1, wherein
A thin film transistor, wherein the first silicon oxide film interface layer has a thickness of 5 nm to 30 nm, and the second silicon oxide film interface layer has a thickness of 5 nm to 30 nm. The thin film transistor according to claim 1 or 2,
A thin film transistor, wherein an Eγ ′ center defect density of the first silicon oxide film interface layer and the second silicon oxide film interface layer is smaller than an Eγ ′ center defect density in the silicon oxide film. The thin film transistor according to claim 3,
The Eγ ′ center defect density in the first silicon oxide film interface layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ , and the Eγ ′ center defect density in the second silicon oxide film interface layer is 1. A thin film transistor, which is × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ and has an Eγ ′ center defect density in the silicon oxide bulk layer of 3 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . The thin film transistor according to any one of claims 1 to 4,
The semiconductor layer is formed on a transparent substrate;
A protective film comprising the silicon oxide film layer, and a silicon oxide film comprising the first silicon oxide film interface layer, the silicon oxide film bulk layer, and the second silicon oxide film interface layer; A thin film transistor formed between the semiconductor layer and the semiconductor layer. The thin film transistor according to claim 5,
The thin film transistor, wherein the transparent substrate is made of a glass substrate. A plurality of video signal lines and a plurality of scanning signal lines intersecting the video signal lines;
The thin film transistor according to any one of claims 1 to 6, which controls capturing of a video signal from the video signal line in accordance with a scanning signal from the scanning signal line,
A display device in which a region surrounded by the video signal line and the scanning signal line is a pixel region. The display device according to claim 7,
The display device is a liquid crystal display device. The display device according to claim 7,
The display device is an organic EL display device.

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