JP2011054658A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of securing a short-margin between a contact and an active area. <P>SOLUTION: In the nonvolatile semiconductor memory 1, STIs are formed to the upper layer of a silicon substrate, and the upper layer of the silicon substrate is partitioned into a plurality of active areas AA that extend in the Y direction. Bit-line contacts CB are formed on the active areas AA, and the lower ends thereof are connected to the active areas AA. Here, the bit-line contacts CB are arranged zigzag. The top faces of parts 7 have positions in the Y direction which is identical to those of the parts 6 of one active areas AA as parts of the other active areas AA arranged adjacent to one active areas AA, and the positions are disposed to the parts lower than the top faces of the parts 6 connecting the bit-line contacts CB in one of the active areas AA. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a NAND type nonvolatile semiconductor memory device.

  Conventionally, a NAND type storage device has been used as a nonvolatile semiconductor storage device. In a NAND type memory device, an upper layer portion of a silicon substrate is divided into a plurality of line-shaped portions, and these line-shaped portions are used as an active area. A plurality of memory cells are formed in each active area, and a pair of select gate electrodes are provided on both sides of the plurality of memory cells. A bit line and a source line are provided above the silicon substrate and connected to both sides of the pair of select gate electrodes. At this time, at least the bit line is connected to the active area via a contact.

  However, when the miniaturization of the NAND type storage device advances, there is a problem that the short margin between adjacent contacts is lowered. That is, if the position of the contact shifts due to variations in the manufacturing process, the two contacts connected to the adjacent active areas may be short-circuited. For this reason, a technique has been proposed in which contacts are arranged in a staggered pattern when viewed from above (see, for example, Patent Document 1).

  However, by arranging the contacts in a staggered manner, the short margin between the contacts can be improved, but the short margin between the contacts and the active area cannot be improved. That is, when the interval between the active areas is reduced, there is a possibility that a contact connected to a certain active area and an active area arranged next to the active area are short-circuited. For this reason, if the NAND memory device is miniaturized, the yield of the product is lowered.

JP 2009-54941 A (FIG. 1)

  An object of the present invention is to provide a nonvolatile semiconductor memory device capable of ensuring a short margin between a contact and an active area.

  According to one aspect of the present invention, a semiconductor substrate, and a plurality of element isolation insulators formed in an upper layer portion of the semiconductor substrate and partitioning the upper layer portion into a plurality of active areas extending in a first direction, A contact provided on the active area and having a lower end connected to the active area, and the positions of the two contacts respectively connected to the adjacent active areas are shifted from each other in the first direction. Each active area has a first part to which the contact is connected and a second part whose upper surface is lower than the upper surface of the first part, and the first part of one active area Is disposed next to the second portion of the other active area disposed next to the one active area. Apparatus is provided.

  According to the present invention, it is possible to realize a nonvolatile semiconductor memory device that can secure a short margin between a contact and an active area.

1 is a block diagram illustrating a nonvolatile semiconductor memory device according to a first embodiment of the invention. It is sectional drawing by the A-A 'line | wire shown in FIG. 1 is a cross-sectional view illustrating a nonvolatile semiconductor memory device according to a comparative example of the first embodiment. FIG. 6 is a cross-sectional view illustrating a nonvolatile semiconductor memory device according to a second embodiment of the invention. FIG. 6 is a plan view illustrating a nonvolatile semiconductor memory device according to a third embodiment of the invention. FIG. 6 is a plan view illustrating a nonvolatile semiconductor memory device according to a fourth embodiment of the invention. FIG. 9 is a plan view illustrating a nonvolatile semiconductor memory device according to a fifth embodiment of the invention. It is sectional drawing by the B-B 'line shown in FIG. It is sectional drawing by the C-C 'line shown in FIG. FIG. 9 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to a fifth embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment. (A)-(c) is a figure which illustrates the manufacturing method of the non-volatile semiconductor memory device which concerns on 5th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
1st Embodiment is embodiment which shows the characteristic part of this invention roughly. A detailed configuration and manufacturing method of the nonvolatile semiconductor memory device will be described in detail in a fifth embodiment to be described later.

FIG. 1 is a plan view schematically illustrating the nonvolatile semiconductor memory device according to this embodiment.
2 is a cross-sectional view taken along line AA ′ shown in FIG.
FIG. 3 is a cross-sectional view illustrating a nonvolatile semiconductor memory device according to a comparative example of this embodiment.
FIG. 3 shows a cross section corresponding to FIG. Moreover, in FIGS. 1-3, only the electroconductive part is shown in order to simplify a figure, and the insulation part is abbreviate | omitted. The same applies to FIGS. 4 to 6 described later.

  As shown in FIGS. 1 and 2, the nonvolatile semiconductor memory device 1 according to the present embodiment (hereinafter also simply referred to as “device 1”) is a NAND flash memory. In the device 1, a silicon substrate is provided, and a plurality of STIs (shallow trench isolation: element isolation insulator, not shown) extending in one direction are formed in an upper layer portion of the silicon substrate. These STIs partition the upper layer portion of the silicon substrate into a plurality of active areas AA.

  In this specification, for convenience of explanation, an XYZ orthogonal coordinate system is adopted. That is, of the directions parallel to the upper surface of the silicon substrate, the direction in which the STI and the active area AA extend is the Y direction, and the direction orthogonal to the Y direction is the X direction. The direction perpendicular to the upper surface of the silicon substrate is taken as the Z direction.

  In the device 1, a memory string is formed along the active area AA, and a plurality of memory cells are connected in series. A pair of select gate electrodes SG is provided above the silicon substrate and on both sides of the plurality of memory cell groups belonging to the memory string. The memory string is connected between a bit line contact CB connected to a bit line (not shown) extending in the Y direction and a source line (not shown) extending in the X direction.

  The bit lines are arranged immediately above the active area AA, and each bit line is connected to each active area AA via a bit line contact CB. That is, each bit line contact CB is disposed on each active area AA, and the lower end is connected to the active area AA and the upper end is connected to the bit line. The shape of the bit line contact CB is, for example, a cylindrical shape, and for example, the lower end portion is thinner than the other portions.

  The bit line contact CB is connected to a portion of the active area AA located between two select gate electrodes SG belonging to different memory strings. Further, when viewed from above (Z direction), the bit line contacts CB are arranged in a staggered manner. That is, the positions in the Y direction of the two bit line contacts CB respectively connected to the adjacent active areas AA are shifted from each other.

  In the design, the central axis of the bit line contact CB is positioned on the central line of the active area AA. However, when the device 1 is actually manufactured, the central axis of the bit line contact CB is active due to variations in the manufacturing process. There may be a case where it deviates from the center line of the area AA.

  In the device 1, a part of another active area AA arranged adjacent to the active area AA rather than the upper surface of the part 6 to which the bit line contact CB is connected in a certain active area AA, and in the Y direction. The upper surface of the portion 7 that is the same as the portion 6 of the active area AA at the position of is located below, that is, on the silicon substrate side. That is, the portion 7 is dug with respect to the portion 6. Since the portion 6 includes a region immediately below the bit line contact CB, the portion 6 is arranged in a staggered manner as with the bit line contact CB when viewed from above. In other words, each active area AA has a portion 6 to which the bit line contact CB is connected and a portion 7 whose upper surface is lower than the upper surface of the portion 6, and the portion 6 of one active area AA is It can be said that it is arranged next to a part 7 of another active area AA arranged next to one active area AA. In the present embodiment, for example, a portion excluding the portion 6 is a portion 7 among the portions located between two select gate electrodes SG belonging to mutually different memory strings in the active area AA. Accordingly, the portions 7 are arranged in a staggered manner so as to supplement the portion 6.

  Here, the portion 6 is a partial region of the active area AA, and is a region having a predetermined length in the Y direction in addition to the portion to which the bit line contact CB is connected. This predetermined length is preferably such that at least the bit line contact CB contacts the upper surface of the portion 6 even when misalignment occurs in the Y direction when the bit line contact CB is formed.

  Moreover, since the part 6 and the part 7 are arranged in a staggered pattern, the part 6 and the part 7 are also arranged along the Y direction in each active area AA. Furthermore, in each active area AA adjacent in the X direction, the part 6 and the part 7 are in contact with each other.

Next, the effect of this embodiment is demonstrated.
As described above, in the device 1 according to the present embodiment, the upper surface of the portion 7 located on both sides in the X direction of the portion 6 is recessed with respect to the upper surface of the portion 6 to which the bit line contact CB is connected in the active area AA. It is. For this reason, the shortest distance L1 between the bit line contact CB connected to the portion 6 and the adjacent portion 7 is large. Thereby, a short margin between the bit line contact CB and the active area AA can be secured. Further, since the diameter of the bit line contact CB can be increased, the contact resistance between the bit line contact CB and the active area AA can be reduced. Furthermore, the width at the top of the portion 7, that is, the length in the X direction is substantially the same as the width at the top of the portion 6. Therefore, the cross-sectional area of the upper part of the active area AA through which the cell current mainly flows is substantially the same in the part 6 and the part 7. For this reason, the cell current flowing through the active area AA is not reduced by forming the portion 7.

  On the other hand, as shown in FIG. 3, in the nonvolatile semiconductor memory device 101 according to the comparative example of this embodiment, the entire upper surface of the active area AA is flat. For this reason, the shortest distance L2 between the bit line contact CB connected to the portion 6 of the active area AA and the adjacent portion 7 is smaller than the shortest distance L1 in the device 1. For this reason, it is difficult to ensure a short margin between the bit line contact CB and the active area AA.

  Here, in the comparative example shown in FIG. 3, it is conceivable to improve the short margin between the bit line contact CB and the active area AA by narrowing the bit line contact CB. However, in this case, the contact resistance between the bit line contact CB and the active area AA increases, and the cell current decreases. On the other hand, in the device 1 of the present embodiment, a short margin between the bit line contact CB and the active area AA can be ensured without making the bit line contact CB thin.

  Note that the portion 7, that is, the portion where the depression in the active area AA is formed may be provided at least on both sides in the X direction of the portion 6 to which the bit line contact CB is connected. Accordingly, it is not always necessary to form a depression in the entire portion excluding the portion 6 among the portions located between the select gate electrodes SG.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a cross-sectional view illustrating the nonvolatile semiconductor memory device according to this embodiment.
FIG. 4 shows a cross section corresponding to FIG. 2 in the first embodiment described above.
As shown in FIG. 4, the nonvolatile semiconductor memory device 2 according to the present embodiment (hereinafter also simply referred to as “device 2”) is compared with the device 1 according to the first embodiment described above (see FIG. 1). In the portion 7 of the active area AA, the corner portion 8 between the upper surface and the side surface facing in the X direction is rounded. That is, the radius of curvature r of the corner 8 of the portion 7 is larger than the radius of curvature of the corner of the portion 6. Other configurations in the present embodiment are the same as those in the first embodiment.

Next, the effect of this embodiment is demonstrated.
According to this embodiment, since the corner 8 of the portion 7 is rounded in the device 2, the shortest distance L3 between the bit line contact CB and the adjacent portion 7 in the device 2 is the same as that in the device 1. It is larger than the shortest distance L1. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

Next, a third embodiment of the present invention will be described.
FIG. 5 is a plan view illustrating the nonvolatile semiconductor memory device according to this embodiment.
As shown in FIG. 5, the nonvolatile semiconductor memory device 3 according to the present embodiment (hereinafter also simply referred to as “device 3”) is compared with the device 1 according to the first embodiment described above (see FIG. 1). Thus, the arrangement of the bit line contacts CB is different. For this reason, the arrangement of the portion 6 located immediately below the bit line contact CB is also different. Therefore, the arrangement of the part 7 is also different from that of the device 1.

  More specifically, in this embodiment as well, the bit line contact CB is disposed between two select gate electrodes SG belonging to different memory strings, as in the first embodiment. However, in the present embodiment, there are three positions in the Y direction: a position P1 on one select gate electrode SG side, an intermediate position P2, and a position P3 on the other select gate electrode SG side. And it arrange | positions so that it may reciprocate between the position P1 and the position P3 in order of position P1, P2, P3, P2, P1, P2, P3, ... along the X direction.

  According to the present embodiment, the distance between the bit line contacts CB in the X direction can be further increased at the positions P1 and P3. As a result, a short margin between the bit line contacts CB can be increased. Configurations and operational effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a fourth embodiment of the present invention will be described.
FIG. 6 is a plan view illustrating the nonvolatile semiconductor memory device according to this embodiment.
As shown in FIG. 6, the nonvolatile semiconductor memory device 4 according to the present embodiment (hereinafter also simply referred to as “device 4”) is compared with the device 3 according to the third embodiment described above (see FIG. 5). Thus, the arrangement of the bit line contacts CB is different. That is, the bit line contacts CB are repeatedly arranged in the order of positions P1, P2, P3, P1, P2, P3,... Along the X direction. According to the present embodiment, the distance between the bit line contacts CB can be increased not only at the positions P1 and P3 but also at the position P2. Configurations and operational effects other than those described above in the present embodiment are the same as those in the third embodiment described above.

Next, a fifth embodiment of the present invention will be described.
This embodiment is an embodiment more specifically showing the first embodiment described above.
The nonvolatile semiconductor memory device according to this embodiment is, for example, a NAND flash EEPROM (erasable programmable ROM).
FIG. 7 is a plan view illustrating the nonvolatile semiconductor memory device according to this embodiment.
8 is a cross-sectional view taken along line BB ′ shown in FIG.
FIG. 9 is a cross-sectional view taken along line CC ′ shown in FIG.
FIG. 10 is a circuit diagram illustrating the nonvolatile semiconductor memory device according to this embodiment.

  As shown in FIGS. 7 to 9, in the nonvolatile semiconductor memory device 5 (hereinafter also simply referred to as “device 5”) according to the present embodiment, a p-type silicon substrate 11 is provided, An n-type well (not shown) is formed in the silicon substrate 11, and a p-type well (not shown) is formed above the n-type well. As viewed from above (Z direction), the p-type well is disposed inside the n-type well. In the p-type well, a plurality of memory string regions Rms are set apart from each other along the Y direction. Every other region between the memory string regions Rms is a bit line contact region. Rbc or source line contact region Rsc. A plurality of STIs (element isolation insulators) 13 extending in the Y direction are formed in the upper layer portion of the p-type well so as to connect the plurality of memory string regions Rms. It is divided into a plurality of active areas AA by the STI 13.

  In the memory string region Rms, a tunnel insulating film 14 made of silicon oxide is formed on the silicon substrate 11, and a plurality of stacked bodies 21 extending in the X direction are formed thereon. Further, one laminated body 22 extending in the X direction is formed on each side of the set of the plurality of laminated bodies 21. The stacked bodies 21 and 22 are arranged so as to straddle a plurality of active areas AA. Further, an n-type diffusion layer 23 into which, for example, arsenic is introduced is formed in a region excluding the region directly below the stacked bodies 21 and 22 in the uppermost layer portion of the silicon substrate 11.

  Each stacked body 21 is provided with a floating gate electrode FG made of a conductive material, for example, polysilicon doped with impurities as a charge storage member. The floating gate electrode FG is divided along the X direction for each active area AA. In the stacked body 21, an insulating film 17 made of silicon oxide is provided so as to cover the floating gate electrode FG, and a conductive material, for example, polysilicon doped with impurities is formed thereon. A control gate electrode CG is provided and constitutes a word line WL. The control gate electrode CG is provided in a line extending in the X direction. A silicide layer 32 made of silicide such as cobalt silicide or tungsten silicide is formed on the control gate electrode CG.

  On the other hand, each stacked body 22 is provided with a select gate electrode SG extending in the X direction. The select gate electrode SG is formed by integrating polysilicon forming the floating gate electrode FG and polysilicon forming the control gate electrode CG through the opening 15 of the insulating film 17 directly above the active area AA. ing. A silicide layer 32 is formed on the select gate electrode SG.

In the bit line contact region Rbc, a portion 6 and a portion 7 are provided in each active area AA, and a recess 26 is formed in the portion 7 and the surrounding STI 13. As a result, the upper surface of the portion 7 is positioned below the upper surface of the portion 6. Further, in the active areas AA adjacent in the X direction, the portions 6 and the portions 7 are alternately arranged. Thereby, the adjacent active area AA portion 7 is arranged on both sides in the X direction when viewed from the portion 6 of a certain active area AA. Furthermore, an n ⁺ -type diffusion layer 28 into which, for example, arsenic is introduced is formed in the uppermost layer portion of the active area AA as an impurity diffusion region whose conductivity type is different from that of the active area. In each active area AA, the portion 6 and the portion 7 are arranged so as to be adjacent in the Y direction. Further, the n ⁺ -type diffusion layer 28 is formed continuously to the portion 6 and the portion 7 in each active area AA. The impurity concentration of the portion formed in the portion 7 in the n ⁺ -type diffusion layer 28 is lower than the impurity concentration of the portion formed in the portion 6. The “impurity concentration” means an effective impurity concentration that contributes to electrical conduction in the portion.

Also in the source line contact region Rsc, for example, arsenic is introduced into the uppermost layer portion of the active area AA to form the n ⁺ -type diffusion layer 28. On the silicon substrate 11, a source line SL made of a conductive material, for example, polysilicon doped with impurities is formed. The source line SL straddles a plurality of active areas AA, contacts these active areas AA, and is commonly connected.

  Then, on the entire surface of the memory string region Rms, the bit line contact region Rbc, and the source line contact region Rsc, an interlayer insulating film 33 made of, for example, silicon oxide is formed on the silicon substrate 11 so as to cover the stacked bodies 21 and 22. Is provided. A bit line contact CB made of tungsten, for example, is buried in a part of the region immediately above the portion 6 of the active area AA in the interlayer insulating film 33. The lower end of each bit line contact CB is connected to each portion 6. When viewed from above, the bit line contacts CB are arranged in a staggered manner. A bit line BL extending in the Y direction is provided in a region on the interlayer insulating film 33 and including a region immediately above the active area AA. Each bit line BL is connected to the upper end of each bit line contact CB. An interlayer insulating film 35 made of, for example, a silicon oxide film is provided on the interlayer insulating film 33 so as to embed the bit line BL. In FIG. 7, the illustration of the interlayer insulating film 35, the interlayer insulating film 33, and the tunnel insulating film 14 is omitted for convenience of illustration.

In the device 5, in the bit line contact region Rbc, the bit line BL is connected to the n ⁺ type diffusion layer 28 of the portion 6 of the active area AA through the bit line contact CB. On the other hand, in the source line contact region Rsc, the source line SL is directly connected to the n ⁺ type diffusion layer 28 of the active area AA. In the memory string region Rms, a memory cell transistor MT is formed for each closest portion between the control gate electrode CG and the active area AA. Further, a select transistor ST is formed at the closest portion between the select gate electrode SG and the active area AA. Thereby, as shown in FIG. 10, between the bit line BL and the source line SL, a plurality of memory cell transistors MT are connected in series for each active area AA, and select transistors ST are connected on both sides thereof. A memory string MS is configured.

Further, in each active area AA, the portion 6 and the portion 7 are arranged adjacent to each other in the Y direction, and the n ⁺ -type diffusion layer 28 is continuously formed, so that they are formed in the same active area AA and are different from each other. Two select transistors ST belonging to the memory string MS are electrically connected. Thereby, one bit line contact CB can be shared by two memory strings MS. A memory cell array MCA is configured by a plurality of memory strings MS.

Next, a method for manufacturing the nonvolatile semiconductor memory device 5 according to this embodiment will be described.
11 to 24 are diagrams illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment. FIG. 11A is a process plan view, and FIG. 11B is a diagram (a). FIG. 4C is a process cross-sectional view taken along the line BB ′ shown in FIG.
Since the feature of this embodiment is in the bit line contact region Rbc, FIGS. 11 to 24 show only the bit line contact region Rbc and a part of the memory string region Rms adjacent thereto.

  First, as shown in FIGS. 11A to 11C, a silicon substrate 11 is prepared. For example, the silicon substrate 11 is a part of a p-type silicon wafer. In the silicon substrate 11, a plurality of memory string regions Rms are set apart from each other along the Y direction. Every other region between the memory string regions Rms is a bit line contact region Rbc or a source line contact region Rsc (see FIG. 7).

  An n-type well (not shown) is formed in the silicon substrate 11. Next, a p-type well (not shown) is formed on the n-type well. The memory string region Rms, the bit line contact region Rbc, and the source line contact region Rsc described above are disposed inside one p-type well. Next, for example, silicon oxide is deposited to form the tunnel insulating film 14. The tunnel insulating film 14 is a film that is normally insulative but allows a tunnel current to flow when a predetermined voltage within the drive voltage range of the device 5 is applied. Next, a conductive material, for example, a polysilicon film containing impurities is deposited on the tunnel insulating film 14. Thereafter, the polysilicon film, the tunnel insulating film 14 and the silicon substrate 11 are selectively etched to form a plurality of line-shaped trenches 12 extending in the Y direction. Each trench 12 is formed so as to pass through the plurality of memory string regions Rms and the bit line contact region Rbc and source line contact region Rsc therebetween.

  Next, silicon oxide is buried in the trench 12 to form the STI 13. The portion between the STIs 13 in the upper layer portion of the silicon substrate 11 becomes the active area AA. That is, the upper layer portion of the silicon substrate 11 is made of p-type single crystal silicon by the STI 13 and is divided into a plurality of active areas AA extending in the Y direction and spaced apart from each other. At this time, the floating gate electrode FG is formed immediately above the active area AA in the memory string region Rms.

  Next, an insulating film 17 made of, for example, an ONO film is deposited so as to cover the floating gate electrode FG. Thereafter, an opening 15 is formed in a region of the insulating film 17 where the select gate electrode SG (see FIG. 10) is to be formed. Next, a polysilicon film and a silicon nitride film are stacked in this order. At this time, the polysilicon film deposited later is also buried in the opening 15 and contacts the previously deposited polysilicon film. Next, the silicon nitride film is processed into a plurality of lines extending in the X direction by lithography to form the stopper film 16. Thereafter, dry etching is performed using the stopper film 16 as a mask, and the above-described polysilicon film and silicon oxide film are patterned.

  As a result, in the region other than both ends in the Y direction of the memory string region Rms, the insulating film 17 fills the floating gate electrode FG made of polysilicon and divided along the X direction on the tunnel insulating film 14. A plurality of stacked bodies 21 each having a control gate electrode CG made of polysilicon and a stopper film 16 are formed. Each stacked body 21 extends in the X direction across a plurality of active areas AA. In addition, a pair of stacked bodies 22 are formed on both ends of the memory string region Rms in the Y direction, that is, on both sides of the set of the stacked bodies 21 arranged along the Y direction. The basic layer structure of the stacked body 22 is the same as that of the stacked body 21, but the polysilicon film forming the floating gate electrode FG and the polysilicon film forming the control gate electrode CG are connected through the opening 15. As a whole, the select gate electrode SG is formed. In addition, the width of the stacked body 22 is larger than the width of the stacked body 21. Further, in the bit line contact region Rbc, the floating gate electrode FG, the insulating film 17, the control gate electrode CG, and the stopper film 16 are removed by etching.

  Next, an impurity such as arsenic (As) is ion-implanted into the silicon substrate 11 using the stacked bodies 21 and 22 as a mask. As a result, the n-type diffusion layer 23 is formed in a region excluding the region directly below the stacked bodies 21 and 22 in the uppermost layer portion of the silicon substrate 11.

  Next, as shown in FIGS. 12A to 12C, an insulating material such as silicon oxide is deposited on the entire surface to form a silicon oxide film 24. In the memory string region Rms, the silicon oxide film 24 is embedded between the stacked bodies 21 and between the stacked bodies 21 and 22, and the bit line contact region Rbc side and the source line contact region of the stacked body 22. It is also formed on the side surface on the Rsc side. In the bit line contact region Rbc and the source line contact region Rsc, the silicon oxide film 24 is formed on the upper surface of the tunnel insulating film 14.

  Next, as shown in FIGS. 13A to 13C, anisotropic etching, for example, RIE (reactive ion etching) is performed. Thereby, the silicon oxide film 24 is removed from the upper surfaces of the stacked bodies 21 and 22 in the memory string region Rms. In the bit line contact region Rbc and the source line contact region Rsc, the silicon oxide film 24 and the tunnel insulating film 14 are removed from the silicon substrate 11, and the active areas AA and STI 13 are exposed.

  Next, as shown in FIGS. 14A to 14C, a resist mask 25 is formed so as to cover a part of the silicon substrate 11 and the stacked bodies 21 and 22. The resist mask 25 includes a main body portion 25a and a plurality of extending portions 25b extending from the main body portion 25a in the Y direction. The main body portion 25a is formed so as to cover the entire source line contact region Rsc and a portion of the memory string region Rms excluding the end of the stacked body 22 on the bit line contact region Rbc side. The extending portion 25b is formed so as to cover a region that is to be the portion 6 of the active area AA in the bit line contact region Rbc. At this time, the portion on the bit line contact region Rbc side in the stacked body 22, the STI 13, and the portion to be the portion 7 in the active area AA are not covered with the resist mask 25 and exposed.

  Next, as shown in FIGS. 15A to 15C, anisotropic etching is performed by, for example, RIE. As a result, portions of the active areas AA and STI 13 that are not covered by the resist mask 25, the stacked body 22, and the silicon oxide film 24 are dug. As a result, a recess 26 is formed on the upper surface of the silicon substrate 11 in the bit line contact region Rbc. In the active area AA, the portion corresponding to the bottom of the recess 26 is the portion 7. As an example of the digging amount, when the depth of the trench 12 is 200 nm, the digging amount of the recess 26 is 100 nm or less, for example, 50 nm or less.

  Next, as shown in FIGS. 16A to 16C, after removing the resist mask 25, silicon oxide is deposited on the entire surface. This silicon oxide is integrated with the silicon oxide film 24 remaining in the memory string region Rms to form a silicon oxide film 27. The silicon oxide film 27 is formed to protect the silicon substrate 11 exposed in the bit line contact region Rbc.

Next, as shown in FIGS. 17A to 17C, arsenic (As) is ion-implanted through the silicon oxide film 27. As a result, the n ⁺ -type diffusion layer 28 is formed in the uppermost layer portion of the active area AA in the bit line contact region Rbc and the source line contact region Rsc. Here, in the portion 6, the n-type diffusion layer 23 and the n ⁺ -type diffusion layer 28 are overprinted. On the other hand, in the portion 7, only the n ⁺ -type diffusion layer 28 is implanted. As a result, the impurity concentration of the portion formed in the portion 7 of the impurity diffusion layer is lower than the impurity concentration of the portion formed in the portion 6.

  Next, as shown in FIGS. 18A to 18C, a silicon nitride film 29 is formed on the entire surface. The silicon nitride film 29 prevents diffusion of impurities and functions as a stopper when performing CMP (chemical mechanical polishing) in a later process. Of the silicon nitride film 29, the portion formed in the memory string region Rms is formed almost flat so as to cover the stacked bodies 21 and 22, and the portions formed in the bit line contact region Rbc and the source line contact region Rsc are , Recessed with respect to the portion formed in the memory string region Rms. In the silicon nitride film 29, the portion covering the recess 26 in the bit line contact region Rbc is recessed reflecting the shape of the recess 26.

  Next, as shown in FIGS. 19A to 19C, an insulating material such as silicon oxide is deposited on the entire surface. Thereafter, CMP is performed using the silicon nitride film 29 as a stopper, and the insulating material deposited on the silicon nitride film 29 is removed in the memory string region Rms. Thus, the interlayer insulating member 30 is embedded in the bit line contact region Rbc and the source line contact region Rsc.

  Next, as shown in FIGS. 20A to 20C, etching is performed on the entire surface. This etching is performed until the upper surfaces of the control gate electrode CG of the stacked body 21 and the select gate electrode SG of the stacked body 22 are exposed. As a result, portions of the interlayer insulating member 30, the silicon nitride film 29, and the silicon oxide film 27 that are located above the upper surfaces of the stacked bodies 21 and 22 are removed. Next, a silicidation process is performed, and a silicide layer 32 is formed on the control gate electrode CG and the select gate electrode SG. The silicide layer 32 is formed of, for example, cobalt silicide or tungsten silicide.

  Next, as shown in FIGS. 21A to 21C, an insulating material such as silicon oxide is deposited on the entire surface. This insulating material is integrated with the silicon oxide film 27 and the interlayer insulating member 30 to form the interlayer insulating film 33. Although a part of the silicon nitride film 29 remains in the interlayer insulating film 33, the illustration is omitted in FIGS.

  Next, as shown in FIGS. 22A to 22C, a plurality of contact holes 34 are formed in the interlayer insulating film 33. The contact holes 34 are formed in a zigzag shape immediately above the portion 6 of the active area AA and reach the portion 6. A similar contact hole is also formed in the source line contact region Rsc.

  Next, as shown in FIGS. 23A to 23C, a plug material, for example, tungsten is buried in the contact hole 34 to form a bit line contact CB. Similarly, tungsten is buried in the contact hole in the source line contact region to form a source line contact. Thereafter, by forming a source line, each source line contact is electrically connected in common by the source line.

  Next, as shown in FIGS. 24A to 24C, a plurality of bit lines BL are formed on the interlayer insulating film 33. The bit line BL is formed to extend in the Y direction directly above the active area AA and is connected to the bit line contact CB. Next, an interlayer insulating film 35 is formed on the interlayer insulating film 33 by depositing an insulating material such as silicon oxide so as to fill the bit line BL. Thereafter, the silicon wafer is diced and cut into silicon substrates 11. In this way, the nonvolatile semiconductor memory device 5 according to this embodiment is manufactured.

  Also in this embodiment, by digging the portion 7 of the active area AA in the bit line contact region Rbc, the shortest distance between the active area AA and the bit line contact CB is the same as in the first embodiment described above. Can be lengthened. Thereby, even if the arrangement period of the active area AA is shortened, a short margin between the bit line contact CB and the active area AA can be secured without reducing the bit line contact CB. Further, since the diameter of the bit line contact CB can be increased, the contact resistance between the bit line contact CB and the active area AA can be reduced. Furthermore, since a matching margin in the lithography process can be secured and the reduction of the diameter of the bit line contact CB can be suppressed, the processing difficulty can be reduced. As a result, the yield of the device 5 is improved.

In this embodiment, in the steps shown in FIGS. 17A to 17C, the n-type diffusion layer 23 and the n ⁺ -type diffusion layer 28 are formed so as to overlap the portion 6, and the portion 7 Only the n ⁺ -type diffusion layer 28 is formed. Thereby, the contact resistance between the bit line contact CB and the portion 6 can be reduced, and voltage modulation of the bit line BL during the write operation can be prevented.

For example, with respect to a plurality of memory units each composed of one memory string MS, a potential of 3V is applied to the bit line contact CB of the memory unit NU1 shown in FIG. 10, and the bit line contact CB of the memory unit NU2 is applied. Assume that a potential of 0 V is applied. The distance from the bottom of the n ⁺ -type diffusion layer 28 to the bottom of the STI 13 is shorter in the portion 7 than in the portion 6. For this reason, if the impurity concentration of the impurity diffusion layer is the same between the portion 6 and the portion 7, the depletion layer is easily connected between the memory unit NU1 and the portion 7 of the memory unit NU2, and the memory unit NU1 and the memory Modulation occurs between the bit lines BL respectively connected to the unit NU2.

Therefore, in the present embodiment, the impurity concentration of the impurity diffusion layer in the portion 7 is set lower than the impurity concentration of the impurity diffusion layer in the portion 6. Thereby, the width of the depletion layer formed on the silicon substrate 11 side from the interface between the n ⁺ -type diffusion layer 28 and the silicon substrate 11 in the portion 7 can be shortened. That is, the distance from the bottom of the depletion layer to the bottom of the STI 13 can be increased to prevent the depletion layer from being connected between the memory unit NU1 and the memory unit NU2. In this way, voltage modulation of the bit line BL during the write operation can be prevented while lowering the contact resistance between the bit line contact CB and the portion 6.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. The above-described embodiments can be implemented in combination with each other. In addition, the above-described embodiments include those in which those skilled in the art appropriately added, deleted, or changed the design, or added, omitted, or changed conditions as appropriate to the above-described embodiments. As long as it is provided, it is included in the scope of the present invention. For example, in each of the above-described embodiments, the floating gate electrode type memory device in which the charge storage member is made of a conductive material has been shown. A trap type storage device, for example, a MONOS (metal-oxide-nitride-oxide-silicon) type storage device may be used.

1, 2, 3, 4, 5 Nonvolatile semiconductor memory device, 6 and 7 portions, 8 corners, 11 silicon substrate, 12 trench, 13 STI, 14 tunnel insulating film, 15 opening, 16 stopper film, and 17 insulating film , 21, 22 Laminated body, 23 n-type diffusion layer, 24 silicon oxide film, 25 resist mask, 25a body part, 25b extension part, 26 recess, 27 silicon oxide film, 28 n ⁺ type diffusion layer, 29 silicon nitride film , 30 Interlayer insulating member, 32 Silicide layer, 33 Interlayer insulating film, 34 Contact hole, 35 Interlayer insulating film, AA active area, BL bit line, CB bit line contact, CG control gate electrode, FG floating gate electrode, L1, L2 , L3 shortest distance, MCA memory cell array, MS memory string, MT memory cell transition Data, NU1, NU2, NU3 memory unit, P1, P2, P3 position, r the radius of curvature, Rbc bit line contact region, Rms memory string region, Rsc source line contact regions, SG select gate electrode, SL source line, ST selection transistor

Claims (5)

A semiconductor substrate;
A plurality of element isolation insulators formed in an upper layer portion of the semiconductor substrate and partitioning the upper layer portion into a plurality of active areas extending in a first direction;
A contact provided on the active area and having a lower end connected to the active area;
With
The positions in the first direction of the two contacts respectively connected to the adjacent active areas are shifted from each other,
Each said active area is
A first portion to which the contact is connected;
A second portion whose upper surface is lower than the upper surface of the first portion;
Have
The non-volatile semiconductor memory device, wherein the first part of one active area is arranged next to the second part of another active area arranged next to the one active area.   The non-volatile device according to claim 1, wherein a radius of curvature of a corner portion between the upper surface and the side surface of the second portion is larger than a radius of curvature of a corner portion between the upper surface and the side surface of the first portion. Semiconductor memory device. An impurity diffusion layer formed on the active area and having a conductivity type different from that of the active area;
In each active area, the first portion and the second portion are disposed so as to contact each other along the first direction, and the impurity diffusion layer is formed on the first portion and the second portion. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed continuously.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the impurity concentration of the portion formed in the second portion in the impurity diffusion layer is lower than the impurity concentration of the portion formed in the first portion. A plurality of control gate electrodes provided on the active area and extending in a second direction intersecting the first direction;
A charge storage member provided for each closest part of the active area and the control gate electrode;
A tunnel insulating film provided between the active area and the charge storage member;
A pair of select gate electrodes on the active area, disposed on both sides of the set of the plurality of control gate electrodes, and extending in the second direction;
Further comprising
5. The nonvolatile semiconductor memory according to claim 1, wherein the first portion and the second portion are disposed on the opposite side of the set as viewed from the select gate electrode. 6. apparatus.

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