JP2011053811A - Multi-board unit and resetting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To release reset signals of a plurality of circuit boards at the same time in a multi-board unit. <P>SOLUTION: The multi-board unit which is constituted of a plurality of circuit boards connected to one another via connection cables receives power supply from a wired board when the plurality of circuit boards are mounted to the wired board. A plurality of circuit boards having reset signal generation means supply removal signals which are canceled at the detection of the installation of the circuit boards to the wired board via the connection cables. The reset signal generation means in the respective circuit boards generate reset signals to release reset after a lapse of a predetermined time when the removal signals of a plurality of circuit boards are canceled. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a multi-board unit including a plurality of circuit boards and a reset method.

  Generally, an electric circuit unit (hereinafter referred to as “unit”) used in a network device such as a transmission device, an exchange, a repeater, or a router is mounted by inserting each unit into a predetermined mounting position (slot) of the network device. Thus, power is supplied to the unit, and a reset signal is supplied to each electric component in the unit from a reset circuit mounted on the unit so that the unit starts up.

  Power is supplied from a BWB (Back Wired Board) of the network device, and power is supplied to the circuit board when the connector terminal of the circuit board of the unit comes into contact with the connector terminal of the BWB.

  In addition, the circuit board has a removal signal for detecting mounting / non-mounting on the network device, and generally generates a reset signal when the removal signal is released, that is, mounted. The removal signal is a signal for recognizing that the connector terminal of the circuit board and the connector terminal of the BWB are in contact. Usually, the connector terminal pin (RMV pin) for the removal signal is the pin of all the connector terminals. Shortest. For this reason, when the unit is mounted on the network device, the RMV pin finally comes into contact with the pin of the BWB connector terminal and the removal signal is released. That is, when this pin can contact, all the other pins are energized. On the other hand, when the unit is removed from the network device, it first leaves the connector terminal pin of the BWB.

  Therefore, by supervising this removal signal, it is possible to recognize whether the unit is mounted on the network device. When the removal signal is released, all signals are in the energized state. In response to this, a reset signal can be generated to reset the electrical components mounted on the circuit board.

  FIG. 1 shows a circuit configuration diagram of an example of a conventional single board unit. When the unit 1 is mounted on the network device, the power supply terminal 2 of the primary power supply of −48V, which is longer than the RMV pin, comes into contact with the connector terminal on the BWB side to supply power. The on-board power supply (OBP) 3 on the unit side generates a required power supply voltage Vdd (for example, +3.3 V, +2.5 V, etc.) from the −48 V power supply. The RMV terminal 4 which is a connector terminal for the removal signal is pulled up to the voltage Vdd, and the short RMV terminal 4 is brought into the ground level when it comes into contact with the BWB connector terminal later. Thus, the generation of the reset signal is triggered by the change of the removal signal from the voltage Vdd to the ground level.

  The reset IC 5 is a general-purpose chip for generating a reset signal, and generates a reset pulse for releasing the reset after a predetermined time (for example, about 200 msec) triggered by a change in the removal signal that is a monitoring signal.

  By the way, some multifunctional and high-density units have two circuit boards. There are various reasons for this, depending on the network device, such as using two components because all components could not be mounted on a limited circuit board, and using two slots from the BWB.

  In such a unit composed of two or more circuit boards (hereinafter referred to as “multi-board unit”), when power and removal signals are supplied to each circuit board, Each requires a reset signal generation circuit.

  FIG. 2 is a perspective view of the multi-board unit. Two circuit boards of the main board 11 and the sub board 12 are fixed by the front panel 13 to realize one unit 14. FIG. 3 is a perspective view in which the front panel of the unit having the multi-board configuration of FIG. 2 is removed. The main board 11 and the sub board 12 are connected by a connection cable 15 in order to exchange signals with each other.

  FIG. 4 shows how a unit is mounted on a network device. The unit 16 having a single board configuration is directly mounted in a card slot 18a provided in the shelf 17 of the network apparatus, and is mounted in a BWB connector on the back of the shelf. Since the unit 14 of the two-board configuration has twice the width of the unit 16, it is mounted in the card slots 18b and 18c for two sheets of the network device, and the BWB connector on the rear surface of the shelf is connected to the individual circuit boards 11 and 12, respectively. Power and removal signal are supplied from

  FIG. 5 is a circuit configuration diagram of a conventional multi-substrate unit. The main board 11 and the sub board 12 have the power supply terminal 2 and the RMV terminal 4, respectively, and the main board 11 and the sub board 12 have the reset generation circuit 5 respectively. The electrical component 11A of the main board 11 and the electrical component 12B of the sub board 12 are connected by a connection cable 15 in order to exchange signals with each other.

  In addition, it has been conventionally known that the contact of the feeder line of the hot-wire insertion connector is divided into a long pin and a short pin and a power-on reset circuit is provided on the wiring board (see, for example, Patent Document 1).

  Further, the power-on-clear information of the first printed board on which the CPU is mounted is transmitted to the second printed board mounted on the RAM and the like, and this is folded back on the second printed board and returned to the first printed board as folded information. A technique has been proposed in which an initialization operation is started by the CPU when the return information, the power-on-clear information of the second printed board, and the power-on-clear information of the user are all prepared (see, for example, Patent Document 2).

JP-A-3-171214 JP-A-6-51869

  In the case of a multi-board unit with a two-board configuration as shown in FIG. 5 or a multi-board configuration of more than one, each circuit board has a power supply terminal and an RMV terminal, and each unit is equipped with a reset generation circuit. When mounted on the apparatus, the timing at which each RMV terminal contacts the BWB connector is not completely the same, but slightly shifts in timing. If the multi-board unit is mounted slowly or obliquely, this timing shift may become significant.

  Due to the deviation in the contact timing of the RMV terminal, the release timing of the removal signal is shifted, and the release timing of the reset signal generated by the reset circuit 5 of each of the main board 11 and the sub board 12 is also shifted.

  FIG. 6 shows a signal timing chart in the multi-substrate unit. In FIG. 6, when the multi-board unit 14 is mounted on the network device, the power supply terminals 2 of the main board 11 and the sub-board 12 are individually energized, and therefore the energization timing of the −48V power supply differs by the time T1. When each power supply terminal 2 is energized, Vdd power (+ 3.3V, + 2.5V, etc.) is supplied from the OBP 3, and the RMV terminal 4 becomes the Vdd level. Thereafter, the RMV terminal 4 is energized with the BWB connector terminal and falls to the ground level. However, the timing of energizing the main board 11 and the sub board 12 is different, and therefore the timing at which the removal signal becomes the ground level is also shifted by the time T2.

  Since the reset signal is released after the reset release time elapses when the removal signal falls to the ground level, the shift of the removal signal becomes the reset release shift (time T3) as it is.

  If the reset signal release timing is deviated, the signals transferred between the circuit boards 11 and 12 are affected. For example, in the case of the configuration of FIG. 5, even if the reset signal is canceled on the main board and a signal is sent from the electrical component 11A mounted on the main board to the electrical component 12B mounted on the sub board, the sub board is still being reset. The electrical component 12B cannot receive a signal. If the electrical component 11A sends an important signal necessary for starting the electrical component 12B, there is a problem that the unit cannot be normally started at this point.

  As shown in FIG. 5, the reset signal generated by the reset generation circuit 5 of the main board 11 is supplied to the sub-board 12 and the reset signal generated by the reset generation circuit 5 of the sub-board 12 in FIG. Is supplied to the main board 11. Then, the main board 11 takes the logical product of the reset signal generated on its own board and the reset signal received from the sub board 12 (the receiving end is pulled up) and supplies it to the electrical component 11A, and the sub board 12 is the own board. Consider a case where the logical product of the generated reset signal and the reset signal received from the main board 11 (the receiving end is pulled up) is taken and supplied to the electrical component 12B.

  In this case, if the connection of the reset signal is disconnected in the connection cable 15 that connects the main board 11 and the sub board 12, there is a problem that the release of each reset signal is shifted. Also, if one of the main board 11 and the sub board 12 is not securely mounted, and only one of the circuit boards cannot be energized with the BWB connector and the -48V power is not supplied, the Vdd power is supplied from the OBP. The reset signal passed to the other side is in an open state (the receiving side becomes high level by pull-up). Then, there is a problem that only the circuit board that is normally mounted releases the reset signal, and the circuit board that is not supplied with Vdd cannot start up.

  An object of the disclosed multi-board unit is to simultaneously cancel reset signals of a plurality of circuit boards.

A multi-board unit according to an embodiment of the present disclosure includes a plurality of circuit boards connected to each other by connection cables, and the plurality of circuit boards are mounted on a wired board and supplied with power from the wired board. In the unit
Each of the plurality of circuit boards has reset signal generation means,
The connection cable mutually supplies a removal signal for detecting and releasing mounting of each of the plurality of circuit boards on the wired board,
The reset signal generation means for each circuit board generates a reset signal for releasing the reset after a predetermined time triggered by the release of the removal signals of the plurality of circuit boards.

  According to this embodiment, the reset signals of a plurality of circuit boards can be canceled simultaneously.

It is a block diagram of an example of the conventional board | substrate unit. It is a perspective view of a multi substrate unit. It is the perspective view which removed the front panel of the multi substrate unit. It is a figure which shows a mode that a unit is mounted in a network apparatus. It is a circuit block diagram of the conventional multi board | substrate unit. It is a signal timing chart in a multi substrate unit. It is a block diagram of 1st Embodiment of a multi board | substrate unit. It is a block diagram of 2nd Embodiment of a multi board | substrate unit. It is a block diagram of the modification of 2nd Embodiment of a multi-substrate unit. It is a block diagram of another modification of 2nd Embodiment of a multi board | substrate unit.

  Embodiments will be described below with reference to the drawings.

<First Embodiment>
FIG. 7 is a configuration diagram of a first embodiment of a multi-substrate unit having a two-substrate configuration. In FIG. 7, the main board 20 and the sub board 30 are connected to each other by a connection cable 40 to form a two-board unit.

  In the main board 20, a power supply terminal 21 a and a ground terminal 21 b of a primary power supply of −48V longer than the RMV pin are connected to an on-board power supply (OBP) 23 through a noise filter circuit 22. When the terminals 21a and 22b are brought into contact with the connector terminal on the BWB side and supplied with power, the OBP 23 generates a power supply voltage Vdd such as + 3.3V or + 2.5V from the −48V power supply.

  The RMV terminal 21c for the removal signal is pulled up (set) to the voltage Vdd via the resistor R21, and the short RMV terminal 21c comes into contact with the BWB connector terminal (ground level) after the terminals 21a and 22b. Become ground level. The removal signal is inverted by the inverter 24 and supplied to one terminal of the AND circuit 25, and also supplied to the other terminal of the AND circuit 35 of the sub-board 30 through the connection cable 40. The other terminal of the AND circuit 25 is pulled down (set) via the resistor R22, and an inverted removal signal is supplied from the inverter 34 of the sub-board 30.

  The reset IC 26 is a general-purpose chip for generating a reset signal. The reset IC 26 is reset after a predetermined time (for example, about 200 msec) when the output signal of the AND circuit 25 as a monitoring signal changes from a low level to a high level. A reset pulse that is released and becomes high level is generated. The output terminal of the reset IC 26 is pulled up to the voltage Vdd via the resistor R23, and the reset pulse is supplied to the electric component 27 and other electric components of the main board 20.

  In the sub-board 30, the power supply terminal 31 a and the ground terminal 31 b of the primary side power supply of −48 V longer than the RMV pin are connected to the on-board power supply (OBP) 33 through the noise filter circuit 32. When the terminals 31a and 32b are brought into contact with the connector terminal on the BWB side and supplied with power, the OBP 33 generates a power supply voltage Vdd such as + 3.3V or + 2.5V from the −48V power supply.

  The RMV terminal 31c for the removal signal is pulled up to the voltage Vdd via the resistor R31, and the short RMV terminal 31c comes into contact with the BWB connector terminal (ground level) after the terminals 31a and 32b to reach the ground level. Become. The removal signal is inverted by the inverter 34 and supplied to one terminal of the AND circuit 35, and also supplied to the other terminal of the AND circuit 25 of the main board 20 through the connection cable 40. The other terminal of the AND circuit 35 is pulled down via the resistor R32, and an inverted removal signal is supplied from the inverter 24 of the main board 20.

  The reset IC 36 is a general-purpose chip for generating a reset signal. The reset IC 36 is set to a low level for a predetermined time (for example, about 200 msec) when the output signal of the AND circuit 35 that is a monitoring signal changes from a low level to a high level. A reset pulse is generated. The output terminal of the reset IC 36 is pulled up to the voltage Vdd via the resistor R33, and the reset pulse is supplied to the electric component 37 and other electric components of the sub board 30.

  In this embodiment, when one of the main board 20 and the sub board 30 (for example, the sub board 30) is not properly mounted (cannot be connected to the BWB connector terminal) and -48V power is not supplied, The Vdd power is not supplied from the OBP 33, and the inverted removal signal passed to the other party, that is, the main board 20, becomes a low level. For this reason, in the main board 20 on the receiving side, the removal signal supplied from the AND circuit 25 to the reset IC 26 remains at the low level and the removal is not released. Therefore, the reset signal remains at the low level and the reset is not released. Both the main board 20 and the sub board 30 are not activated, and it can be recognized that there is an abnormality.

  Further, even when a failure occurs in the connection cable 40 and the inverted removal signal cannot be supplied between the main board 20 and the sub board 30, the receiving circuit 25 (or 35) to the reset IC 26 (or 36) on the receiving side. Since the removal signal supplied to the signal remains at a low level and the removal is not released, the reset signal is maintained at a low level and the reset is not released, and neither the main board 20 nor the sub board 30 is activated, which is abnormal. I can recognize that.

Second Embodiment
FIG. 8 is a configuration diagram of a second embodiment of a multi-substrate unit having a two-substrate configuration. In FIG. 8, the main board 20 and the sub board 30 are connected to each other by a connection cable 40 to form a two-board unit.

  In the main board 20, the power supply terminal 21 a and the ground terminal 21 b of the primary power supply of −48 V which is longer than the RMV pin are connected to the OBP 23 through the noise filter circuit 22. When the terminals 21a and 22b are brought into contact with the connector terminal on the BWB side and supplied with power, the OBP 23 generates a power supply voltage Vdd such as + 3.3V or + 2.5V from the −48V power supply.

  The RMV terminal 21c for the removal signal is pulled up to the voltage Vdd via the resistor R21, and the short RMV terminal 21c comes into contact with the BWB connector terminal (ground level) after the terminals 21a and 22b to reach the ground level. Become. The removal signal is inverted by the inverter 24 and supplied to one terminal of the AND circuit 25, and also supplied to the other terminal of the AND circuit 35 of the sub-board 30 through the connection cable 40. Further, the other terminal of the AND circuit 25 is pulled down via the resistor R22, and an inverted removal signal is supplied from the inverter 34 of the sub-board 30.

  The reset IC 26 is a general-purpose chip for generating a reset signal. The reset IC 26 is reset after a predetermined time (for example, about 200 msec) when the output signal of the AND circuit 25 as a monitoring signal changes from a low level to a high level. A reset pulse that is released and becomes high level is generated. The output terminal of the reset IC 26 is pulled up to the voltage Vdd via the resistor R23, and the reset pulse is supplied to one terminal of the AND circuit 28 and the other of the AND circuit 38 of the sub-board 30 through the connection cable 40. Are supplied to the terminals.

  The other terminal of the AND circuit 28 is pulled up via the resistor R24, and a reset signal is supplied from the reset IC 36 of the sub-board 30. The reset signal output from the AND circuit 28 is supplied to the electric component 27 and other electric components of the main board 20.

  In the sub-board 30, the power supply terminal 31 a and the ground terminal 31 b of the primary side power supply of −48 V longer than the RMV pin are connected to the on-board power supply 33 through the noise filter circuit 32. When the terminals 31a and 32b are brought into contact with the connector terminal on the BWB side and supplied with power, the OBP 33 generates a power supply voltage Vdd such as + 3.3V or + 2.5V from the −48V power supply.

  The RMV terminal 31c for the removal signal is pulled up to the voltage Vdd via the resistor R31, and the short RMV terminal 31c comes into contact with the BWB connector terminal (ground level) after the terminals 31a and 32b to reach the ground level. Become. The removal signal is inverted by the inverter 34 and supplied to one terminal of the AND circuit 35, and also supplied to the other terminal of the AND circuit 25 of the main board 20 through the connection cable 40. The other terminal of the AND circuit 35 is pulled down via the resistor R32, and an inverted removal signal is supplied from the inverter 24 of the main board 20.

  The reset IC 36 is a general-purpose chip for generating a reset signal. The reset IC 36 is set to a low level for a predetermined time (for example, about 200 msec) when the output signal of the AND circuit 35 that is a monitoring signal changes from a low level to a high level. A reset pulse is generated. The output terminal of the reset IC 36 is pulled up to the voltage Vdd via the resistor R33, and the reset pulse is supplied to one terminal of the AND circuit 38 and the other of the AND circuit 28 of the main board 20 through the connection cable 40. Are supplied to the terminals.

  The other terminal of the AND circuit 38 is pulled up via a resistor R34, and a reset signal is supplied from the reset IC 26 of the main board 20. The reset signal output from the AND circuit 38 is supplied to the electrical component 37 and other electrical components of the sub-board 30.

  In this embodiment, as in the first embodiment, when one of the main board 20 and the sub board 30 (for example, the sub board 30) is not properly mounted and −48V power is not supplied, the OBP 33 starts. The Vdd power is not supplied, and the inverted removal signal passed to the other party, that is, the main board 20, becomes low level. For this reason, the reset signal is maintained at a low level and the reset is not released, and neither the main board 20 nor the sub board 30 is activated, and it can be recognized that there is an abnormality. In addition, even when a failure occurs in the connection cable 40 and the inverted removal signals cannot be supplied to each other between the main board 20 and the sub board 30, the reset signal is maintained at the low level and the reset is not released, and the main signal is not released. Both the substrate 20 and the sub substrate 30 are not activated, and it can be recognized that there is an abnormality.

  Furthermore, even when a failure such as a longer reset release time of one of the reset ICs 26 and 36 occurs, the release timing of the reset signal for the main board 20 and the sub board 30 can be made simultaneously. Further, when the reset signal of either one of the reset ICs 26 and 36 is not released, it can be recognized that the main board 20 and the sub board 30 are not activated, so that it is abnormal.

<Modification of Second Embodiment>
FIG. 9 shows a configuration diagram of a modified example of the second embodiment of the multi-substrate unit having a two-substrate configuration. In FIG. 9, the same parts as those in FIG. As the reset ICs 26 and 36, there are generally many open-drain outputs. When the reset ICs 26 and 36 are open-drain outputs, the same operation as in FIG. 8 can be performed by wire-or-connecting the output terminal of the reset IC 26 and the output terminal of the reset IC 36 via the connection cable 40. . In this modification, the AND circuits 28 and 38 and the resistors R24 and R34 are not necessary.

  FIG. 10 shows a configuration diagram of another modification of the second embodiment of the multi-substrate unit having a two-substrate configuration. 10, the same parts as those in FIG. 8 are denoted by the same reference numerals. The reset ICs 26 and 36 have a plurality of removal signal input ports so that a plurality of removal signals can be monitored, and triggered by the fact that all the removal signals supplied from the plurality of input ports have changed to a high level. Some generate a reset pulse that is at a low level for a predetermined time. In this case, the output of the inverter 24 is supplied to the first input terminal of the reset IC 26 and also supplied to the second input terminal of the reset IC 36 via the connection cable 40. Further, the output of the inverter 34 is supplied to the first input terminal of the reset IC 36 and also supplied to the second input terminal of the reset IC 26. Then, by pulling down the second input terminals of the reset ICs 26 and 36 via the resistors R22 and R32, the same operation as in FIG. 8 can be performed. In this modified example, the AND circuits 25 and 35 are not necessary.

  As described above, in the multi-board unit, the reset release timings of the respective circuit boards are simultaneously performed, so that the start-up abnormality when mounted on the network device can be eliminated. In addition, even if there is a disconnection or an abnormal connection of the cables connecting the respective circuit boards, the reset IC can recognize the abnormality at the start-up.

  In addition, even when any circuit board is not mounted on the network device in the multi-board unit, the unmounted state can be recognized as one unit. In addition, when the connection cable for connecting the circuit board is disconnected, the operation equivalent to that when the unit is not mounted can be performed. Furthermore, when there is a failure in any of the printed circuit board OBP or reset IC of the multi-board unit, it is possible to prevent the normal circuit board from starting up and eliminate the abnormal state. Thereby, even if it is a multi-substrate unit, the operation | movement equivalent to the unit of single substrate structure can be performed.

In the above-described embodiment, a multi-board unit having a two-board configuration is described as an example. However, a multi-board unit including three or more circuit boards may be used and is limited to the above-described embodiment. is not.
(Appendix 1)
In a multi-board unit composed of a plurality of circuit boards connected to each other with a connection cable, the plurality of circuit boards being mounted on a wired board and supplied with power from the wired board,
Each of the plurality of circuit boards has reset signal generation means,
The connection cable mutually supplies a removal signal for detecting and releasing mounting of each of the plurality of circuit boards on the wired board,
The multi-board unit is characterized in that the reset signal generation means for each circuit board generates a reset signal for releasing the reset after a predetermined time triggered by the release of the removal signals of the plurality of circuit boards.
(Appendix 2)
In the multi-board unit according to appendix 1,
The reset signals generated by the reset signal generating means for each of the plurality of circuit boards are supplied to each other by the connection cable,
A multi-board unit comprising: a reset signal synthesizing unit for releasing a reset signal supplied to an electric component of the circuit board by releasing the reset signals of the plurality of circuit boards.
(Appendix 3)
In the multi-board unit according to appendix 1 or 2,
The reset signal generation means sets a receiving end of the removal signal supplied from another circuit board to a polarity opposite to the polarity of the removal signal that triggers the generation of the reset signal. unit.
(Appendix 4)
In the reset method of the multi-board unit, which is composed of a plurality of circuit boards connected to each other by a connection cable, the plurality of circuit boards are mounted on a wired board and power is supplied from the wired board,
The connection cable mutually supplies a removal signal for detecting and releasing mounting of each of the plurality of circuit boards on the wired board,
Each circuit board generates a reset signal for releasing the reset after a predetermined time triggered by the release of the removal signals of the plurality of circuit boards.
The reset method characterized by the above-mentioned.
(Appendix 5)
In the reset method described in appendix 4,
The reset signals generated by the reset signal generating means for each of the plurality of circuit boards are supplied to each other by the connection cable,
A reset method for canceling a reset signal supplied to an electric component of the circuit board by releasing reset signals of the plurality of circuit boards.
(Appendix 6)
In the multi-board unit described in appendix 3,
The reset signal generating means is an open drain output,
The multi-board unit, wherein the reset signal synthesizing means is a wired OR connection between the reset signal supplied from another circuit board and a reset signal supplied to an electric component of the circuit board.
(Appendix 7)
In the multi-board unit described in appendix 6,
The multi-board unit, wherein the reset signal generating means has a plurality of removal signal input ports, and generates the reset signal when a removal signal supplied from the plurality of input ports is released.

20 Main board 22, 32 Noise filter circuit 23, 33 On-board power supply 24, 34 Inverter 25, 35 AND circuit 26, 36 Reset IC
27, 37 Electric parts 30 Sub-board 40 Connection cable

Claims (5)

In a multi-board unit composed of a plurality of circuit boards connected to each other with a connection cable, the plurality of circuit boards being mounted on a wired board and supplied with power from the wired board,
Each of the plurality of circuit boards has reset signal generation means,
The connection cable mutually supplies a removal signal for detecting and releasing mounting of each of the plurality of circuit boards on the wired board,
The multi-board unit is characterized in that the reset signal generation means for each circuit board generates a reset signal for releasing the reset after a predetermined time triggered by the release of the removal signals of the plurality of circuit boards. The multi-board unit according to claim 1,
The reset signals generated by the reset signal generating means for each of the plurality of circuit boards are supplied to each other by the connection cable,
A multi-board unit comprising a reset signal synthesizing unit for releasing a reset signal supplied to an electric component of the circuit board by releasing the reset signals of the plurality of circuit boards. The multi-board unit according to claim 1 or 2,
The reset signal generation means sets a receiving end of the removal signal supplied from another circuit board to a polarity opposite to the polarity of the removal signal that triggers the generation of the reset signal. unit. In the reset method of the multi-board unit, which is composed of a plurality of circuit boards connected to each other by a connection cable, the plurality of circuit boards are mounted on a wired board and power is supplied from the wired board,
The connection cable mutually supplies a removal signal for detecting and releasing mounting of each of the plurality of circuit boards on the wired board,
Each circuit board generates a reset signal for releasing the reset after a predetermined time triggered by the release of the removal signals of the plurality of circuit boards.
The reset method characterized by the above-mentioned. The reset method according to claim 4,
The reset signals generated by the reset signal generating means for each of the plurality of circuit boards are supplied to each other by the connection cable,
A reset method for canceling a reset signal supplied to an electric component of the circuit board by releasing reset signals of the plurality of circuit boards.