JP2011049249A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for improving working accuracy at a time when a first conductivity type first polycrystalline silicon film and a second conductivity type second polycrystalline silicon film are etched and worked simultaneously. <P>SOLUTION: The manufacturing method includes a process forming the first polycrystalline silicon film 103-1 containing first conductivity type impurities and the second polycrystalline silicon film 103-2 containing second conductivity type impurities. The manufacturing process further includes a patterning process forming a first pattern by etching the first polycrystalline silicon film while forming a second pattern by etching the second polycrystalline silicon film. The patterning process includes a first etching process etching each side face of the first pattern and the second pattern so as to expose the side faces and an oxidation process forming oxide films on the side faces by oxidizing the exposed side faces. The patterning process further includes a second etching process completing the patternings of the first polycrystalline silicon film and the second polycrystalline silicon film by an etching in the state where the side faces are being protected by the oxide films. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

As a material for the gate electrode of the MOS transistor, it can be easily produced by CVD, has excellent adhesion and affinity with SiO ₂ , single crystal Si, Al, etc., and can control the specific resistance by doping. Polycrystalline silicon is widely used. In a semiconductor device such as an image sensor, a memory, and a logic, a dual gate structure having regions with different impurity species on the same substrate may be employed for the purpose of increasing the operation speed. The gate electrode in this dual gate structure may be formed by simultaneously etching an n-type polycrystalline silicon film and a p-type polycrystalline silicon film. In this case, the etching time from the start of etching until the polycrystalline silicon is completely removed differs depending on the etching rate difference between the n-type polycrystalline silicon and the p-type polycrystalline silicon. As a result, the shape of the gate electrode in the dual gate structure tends to deviate from the designed one.

  In Patent Document 1, after an N-type polycrystalline silicon film 10 and a P-type polycrystalline silicon film 11 are formed on a semiconductor substrate, the N-type polycrystalline silicon film 10 is selectively covered with a refractory metal alloy film 13. (See FIGS. 6, 7, and 12 of Patent Document 1). Then, an etching mask of the photoresist 6 patterned so as to remain in the gate electrode wiring formation region is formed on each of the N-type polycrystalline silicon film 10 and the P-type polycrystalline silicon film 11 (see Patent Document 1). (See FIG. 13). Then, anisotropic etching is performed (see FIG. 14 of Patent Document 1). Thus, according to Patent Document 1, since the etching rate of the refractory metal alloy film is slower than that of the N-type polycrystalline silicon film and the P-type polycrystalline silicon film, the apparent etching rate of the N-type polycrystalline silicon film (etching) It is said that the time can be set to the same level as that of the P-type polycrystalline silicon film.

  In Patent Document 2, after an N-type polysilicon 4 and a P-type polysilicon 6 are formed on a semiconductor substrate, an oxide film 5 corresponding to an etching time difference with respect to the P-type polysilicon is formed only on the N-type polysilicon 4. (Refer to FIGS. 1 to 3 of Patent Document 2). Then, the gate electrode is patterned by photolithography and etching (see FIG. 4 of Patent Document 2). Thus, according to Patent Document 2, it is said that the etching times of the N-type polysilicon 4 and the P-type polysilicon 6 can be made substantially the same.

In Patent Document 3, a polysilicon n-type region 204a and a p-type region 204b are formed on a semiconductor substrate, a mask pattern is formed thereon, and then main etching and subsequent overetching are performed. (See FIG. 2 of Patent Document 3). Specifically, in the etching apparatus 100 (see FIG. 1 of Patent Document 3), the pressure in the processing chamber 104 is set to 20 mTorr or less, and a high bias (0.15 W / cm ² or more) is applied to the lower electrode 105. Then, HBr gas and O ₂ gas are supplied as process gases. Thus, the main etching is performed until the gate insulating film 202 is exposed under the condition that the etching by the sputtering phenomenon proceeds and the etching by the chemical reaction does not proceed so much (see FIG. 2B of Patent Document 3). Subsequently, in the etching apparatus 100, the gas is supplied as a processing gas to which N ₂ gas is further added, and the flow rate ratio of N ₂ gas to HBr gas is set to 0.125 or more and 0.3 or less. Under this condition, over-etching is performed until the etching residue is removed (see FIG. 2C of Patent Document 3). Thus, according to Patent Document 3, the sidewall of the gate electrode is protected by the N ₂ gas and the progress of the etching due to the chemical reaction is suppressed, so that the side etching of the gate electrode can be suppressed even at the overetching stage. Yes.

JP 07-283323 A Japanese Patent Laid-Open No. 2000-100100 JP 2003-303817 A

  Patent Document 1 and Patent Document 2 do not describe how etching on the side wall of the gate electrode of the polycrystalline silicon film (polysilicon) is suppressed. When the sidewall of the gate electrode of the polycrystalline silicon film (polysilicon) is etched in the etching process of the polycrystalline silicon film (polysilicon), the processed shape (line width) of the N-type gate electrode and the P-type gate electrode ) Is difficult to align. On the other hand, in the technique described in Patent Document 3, it is necessary to adjust the pressure in the processing chamber, the type of processing gas, the flow rate ratio, and the like to specific conditions, so that the degree of freedom in etching conditions is low.

  An object of the present invention is to provide a semiconductor device for improving processing accuracy when simultaneously etching a first polycrystalline silicon film of a first conductivity type and a second polycrystalline silicon film of a second conductivity type. It is to provide a novel manufacturing method.

  A method for manufacturing a semiconductor device according to one aspect of the present invention includes a first polycrystalline silicon film containing a first conductivity type impurity and a second conductivity type impurity on a semiconductor substrate. Forming the first polycrystalline silicon film, patterning the first polycrystalline silicon film by etching to form a first pattern, and patterning the second polycrystalline silicon film by etching. A patterning step for forming a second pattern, wherein the patterning step includes a first etching step for performing etching so as to expose respective side surfaces of the first pattern and the second pattern, and the exposure. Oxidizing the formed side surface to form an oxide film on the side surface, and performing etching in a state where the side surface is protected by the oxide film, Characterized in that it comprises a silicon film and a second etching step to complete the patterning of the second polysilicon film.

  According to the present invention, a semiconductor device for improving processing accuracy when simultaneously etching a first conductive type first polycrystalline silicon film and a second conductive type second polycrystalline silicon film is provided. The novel manufacturing method can be provided.

FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The circuit diagram for explaining an image sensor.

  A method of manufacturing the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the semiconductor device 100 has a region R1 and a region R2. The region R1 is a region including a region where the first pattern PT1 (for example, n-type gate electrode) is to be formed, and the region R2 forms the second pattern PT2 (for example, p-type gate electrode). This is a region that includes a power region.

  In the step of FIG. 1A, a gate oxide film 102 is formed on the surface of the semiconductor substrate SB by oxidizing the surface of the semiconductor substrate SB. That is, the portion near the surface of the semiconductor substrate SB is used as the gate oxide film 102. The portion of the semiconductor substrate SB that has not been oxidized becomes the base region 101. That is, the gate oxide film 102 is a portion near the surface of the semiconductor substrate SB. Note that the gate oxide film 102 may be formed by depositing an oxide film on the surface of the base substrate using a CVD method or the like. Even in this case, the gate oxide film 102 is regarded as a portion near the surface of the semiconductor substrate SB, and the portion of the base substrate is regarded as the base region 101.

  Next (forming step), a first polycrystalline silicon film 103-1 and a second polycrystalline silicon film 103-2 are formed on the gate oxide film 102. Specifically, a polycrystalline silicon film is deposited on the gate oxide film 102. Then, n-type impurity ions are selectively implanted (doped) into the region R1 in the polycrystalline silicon film through a first mask pattern (not shown). Thereby, the region R1 in the polycrystalline silicon film is defined as the first polycrystalline silicon film 103-1. The first polycrystalline silicon film 103-1 includes an n-type (first conductivity type) impurity. In addition, p-type (second conductivity type) impurity ions are selectively implanted (doped) into the region R2 in the polycrystalline silicon film through a second mask pattern (not shown). The p-type (second conductivity type) is the opposite conductivity type to the n-type (first conductivity type). Thereby, the region R2 in the polycrystalline silicon film is defined as the second polycrystalline silicon film 103-2. Second polycrystalline silicon film 103-2 contains a p-type impurity.

  Next (patterning step), the first polycrystalline silicon film 103-1 is patterned by etching to form a first pattern, and the second polycrystalline silicon film 103-2 is patterned by etching to form a second pattern. The pattern is formed. As shown in FIG. 1A, the first polycrystalline silicon film 103-1 and the first region 103-1a that should be the first pattern PT1 (see FIG. 1D) should be removed. Second region 103-1b. The second polycrystalline silicon film 103-2 includes a third region 103-2a to be the second pattern PT2 (see FIG. 1D) and a fourth region 103-2b to be removed. . Hereinafter, the patterning process will be described in detail with reference to FIGS.

  In the step of FIG. 1A (mask formation step), a pattern of the hard mask 104-1 that selectively covers the first region 103-1a in the first polycrystalline silicon film 103-1 is formed. A pattern of a hard mask 104-2 that selectively covers the third region 103-2a in the second polycrystalline silicon film 103-2 is formed. Each of the hard mask 104-1 and the hard mask 104-2 is formed of, for example, a TEOS film.

  In the step of FIG. 1B (first etching step), etching is performed so as to expose the side surfaces of the first pattern PT1 and the second pattern PT2. That is, the second region 103-1b is etched from the surface to the first depth ED1, and the fourth region 103-2b is etched from the surface to the second depth ED2.

Specifically, the first polycrystalline silicon film 103-1 is etched using the hard mask 104-1 as a mask by plasma etching using a reactive gas containing HBr gas, Cl ₂ gas, and O ₂ gas. That is, the second region 103-1b not covered with the hard mask 104-1 in the first polycrystalline silicon film 103-1 is etched from the surface to the first depth ED1. Thereby, the exposed side surface of the first pattern PT1, that is, the exposed side surface SF1 of the first region 103-1a to be the first pattern PT1 is formed. At the same time, the second polycrystalline silicon film 103-2 is etched using the hard mask 104-2 as a mask. That is, the fourth region 103-2b not covered with the hard mask 104-2 in the second polycrystalline silicon film 103-2 is etched from the surface to the second depth ED2. Thereby, the exposed side surface of the second pattern PT2, that is, the exposed side surface SF2 of the third region 103-2a to be the second pattern PT2 is formed. The second region 103-1b1 in the first polycrystalline silicon film 103-1 is left in a state where the thickness is reduced, and has a thickness of d1, for example. The fourth region 103-2b in the second polycrystalline silicon film 103-2 is left in a state where the thickness is reduced, and has a thickness of d2, for example.

  Here, when the first polycrystalline silicon film 103-1 and the second polycrystalline silicon film 103-2 are etched simultaneously, the first polycrystalline silicon film 103-1 is more likely to be the second polycrystalline silicon film 103. Etching rate is greater than -2. Although the details of this mechanism have not been clarified, it is considered that electrons or phosphorus atoms in the conductor contribute to the etching reaction. Therefore, the n-type first polycrystalline silicon film 103-1 has a higher etching rate than the p-type second polycrystalline silicon film 103-2, and as shown in FIG. Since> ED2, d1 <d2. Note that ED1 + d1≈ED2 + d2.

  In the step (oxidation step) of FIG. 1C, the side surfaces SF1 and SF2 exposed in the step of FIG. 1B are oxidized, and a first oxide film is formed on the side surfaces SF1 and SF2. Further, the upper surfaces UF1 and UF2 of the second region 103-1b1 and the fourth region 103-2b1 left in the step of FIG. 1B are oxidized to form a second oxide film on the upper surfaces UF1 and UF2. Form. The inside where the first and second oxide films are formed, that is, the portion not oxidized is left as a polycrystalline silicon portion. In the step of FIG. 1C, oxidation is performed using a gas containing oxygen.

Specifically, plasma treatment is performed as an oxidation treatment using a reaction gas in which an inert gas such as Ar or Kr is attached to O ₂ gas. Then, the side surface SF1 of the first region 103-1a and the upper surface UF1 of the second region 103-1b in the first polycrystalline silicon film 103-1 are oxidized. As a result, the oxidized portion in the first region 103-1a becomes the oxide film 105-1a, and the unoxidized portion in the first region 103-1a remains as the polycrystalline silicon portion 103-1a2. Further, the oxidized portion in the vicinity of the upper surface in the second region 103-1b becomes an oxide film (second oxide film) 105-1b, and the non-oxidized portion in the second region 103-1b is a polycrystalline silicon portion. It remains as 103-1b2. That is, the exposed portion of the first polycrystalline silicon film 103-1 becomes the oxide film 105-1 including the oxide film 105-1a and the oxide film 105-1b. At the same time, the side surface SF2 of the third region 103-2a and the upper surface UF2 of the fourth region 103-2b in the second polycrystalline silicon film 103-2 are oxidized. Thereby, the oxidized portion near the side surface in the third region 103-2a becomes the oxide film 105-2a, and the non-oxidized portion in the third region 103-2a remains as the polycrystalline silicon portion 103-2a2. The oxidized portion in the vicinity of the upper surface in the fourth region 103-2b becomes an oxide film (second oxide film) 105-2b, and the non-oxidized portion in the fourth region 103-2b is a polycrystalline silicon portion. It remains as 103-2b2. That is, the exposed portion of the second polycrystalline silicon film 103-2 becomes the oxide film 105-2 including the oxide film 105-2a and the oxide film 105-2b. The oxide films 105-1a and 105-1b formed in the step of FIG. 1C have, for example, thicknesses t1 and t1 ′, respectively. The oxide films 105-2a and 105-2b formed in the process of FIG. 1C have, for example, thicknesses t2 and t2 ′, respectively.

  Here, when the first polycrystalline silicon film 103-1 and the second polycrystalline silicon film 103-2 are oxidized at the same time, the first polycrystalline silicon film 103-1 is more likely to be the second polycrystalline silicon film 103. The oxide film formation rate becomes larger than -2. Although details of this mechanism have not been clarified, it is thought that donating electrons to oxygen molecules adsorbed on the surface of polycrystalline silicon promotes oxidation. Therefore, the n-type first polycrystalline silicon film 103-1 has a higher oxide film formation rate than the p-type second polycrystalline silicon film 103-2, and as shown in FIG. T1> t2 and t1 ′> t2 ′.

  Note that in the step of FIG. 1C, oxidation may be performed using a gas containing water vapor instead of performing oxidation using a gas containing oxygen. When oxidizing a polycrystalline silicon film, it is necessary to supply oxygen atoms to the surface of the polycrystalline silicon film, but the diffusion coefficient in silicon oxide is larger for hydroxide ions than for oxygen ions. For this reason, by performing the oxidation using the gas containing water vapor, the time required for the oxidation treatment can be shortened as compared with the case of performing the oxidation using the gas containing oxygen.

In the step of FIG. 1D (second etching step), etching is performed with the side surfaces SF1, SF2 protected by the oxide films 105-2a, 105-2b, and the first polycrystalline silicon film 103-1. Then, the patterning of the second polycrystalline silicon film 103-2 is completed. Specifically, the first polycrystalline silicon film 103-1 is etched using the hard mask 104-1 as a mask by an anisotropic plasma etching process using a reaction gas containing HBr gas, Cl ₂ gas, and O ₂ gas. To do. Thus, the oxide film 105-1b is etched until the polycrystalline silicon portion 103-1b2 in the second region 103-1b is exposed (first step). Thereafter, the polycrystalline silicon portion 103-1b2 in the second region 103-1b is etched until the surface of the semiconductor substrate SB is exposed (second step). That is, the second region 103-1b including the oxide film 105-1b and the polycrystalline silicon portion 103-1b2 is removed by etching, and the surface SB1 of the semiconductor substrate SB adjacent to the first region 103-1a is exposed. Let At the same time, the second polycrystalline silicon film 103-2 is etched using the hard mask 104-2 as a mask. Accordingly, the oxide film 105-2b in the fourth region 103-2b is etched until the polycrystalline silicon portion 103-2b2 in the fourth region 103-2b is exposed (first step). Thereafter, the polycrystalline silicon portion 103-2b2 in the fourth region 103-2b is etched until the surface of the semiconductor substrate SB is exposed (second step). That is, the fourth region 103-2b including the oxide film 105-2b and the polycrystalline silicon portion 103-2b2 is removed by etching, and the surface SB2 of the semiconductor substrate SB adjacent to the third region 103-2a is exposed. Let

  Here, in the oxide films 105-1a and 105-2a included in the first regions 103-1a and 103-2a, the etching process in the step of FIG. , Remain substantially unremoved. Therefore, the oxide films 105-1a and 105-2a function as side wall protective films for the polycrystalline silicon portions 103-1a2 and 103-2a2 in the first regions 103-1a and 103-2a, respectively. As a result, the side walls of the polycrystalline silicon portions 103-1a2 and 103-2a2 are suppressed from being exposed to the etching atmosphere, and the progress of lateral etching on the side walls can be suppressed. As a result, it is possible to suppress the occurrence of a difference in processing shape (line width) due to a difference in etching rate between the first polycrystalline silicon film and the second polycrystalline silicon film. That is, it is possible to improve processing accuracy when simultaneously etching the n-type first polycrystalline silicon film and the p-type second polycrystalline silicon film.

  Further, even after the step of FIG. 1D is completed, the polycrystalline silicon portion in the first region 103-1a is used as an n-type gate electrode, and the oxide film 105-1a portion is used as part of the sidewall. Can function. Similarly, the polycrystalline silicon portion in the third region 103-2a can function as a p-type gate electrode, and the oxide film 105-2a portion can function as a part of a sidewall.

  Note that the timing of shifting from the step of FIG. 1B (first etching step) to the step of FIG. 1C (oxidation step) is not particularly limited, but an n-type gate having a high etching rate. It can be immediately before the exposure of the gate oxide film adjacent to the electrode begins. As a means for shifting to the oxidation step, a method of performing the step of FIG. 1B for a predetermined time based on a previously confirmed etching rate of the polycrystalline silicon film may be used, or the plasma emission intensity may be monitored. It is also possible to use a method for determining the timing of transition by doing so. A more appropriate method is selected and implemented according to the layout pattern of the target sample and, if the semiconductor device includes an image sensor, the aperture ratio of each pixel in the image sensor.

  Further, as described above, the oxide film 105-1b in the second region 103-1b is thicker than the oxide film 105-2b in the fourth region 103-2b. Therefore, since the removal of the oxide film 105-2b is completed earlier than the removal of the oxide film 105-1b, the etching of the polycrystalline silicon portion in the fourth region 103-2b is performed in the polycrystalline region in the second region 103-1b. Start faster than etching the silicon part. Thereby, the difference in etching rate between the first polycrystalline silicon film and the second polycrystalline silicon film is offset. As a result, in the second region 103-1b and the fourth region 103-2b, the difference in etching time from the start of etching until the polycrystalline silicon is removed is compared with the case where the oxidation treatment is not performed. Become smaller. That is, it is easy to set so that the etching of the second region 103-1b and the fourth region 103-2b is completed simultaneously. Therefore, excessive etching of the gate oxide film, which is a portion in the vicinity of the surface of the semiconductor substrate SB, is suppressed, and it is possible to suppress the film loss of the gate oxide film.

  In the present embodiment, the case where the n-type first polycrystalline silicon film and the p-type second polycrystalline silicon film are etched at the same time has been described as an example. It is expressed by the difference in the amount of electrons. Therefore, the first polycrystalline silicon film is n + type (first conductivity type) containing n-type impurities at a high concentration, and the second polycrystalline silicon film is n− containing n-type impurities at a low concentration. Even in the case of a mold (second conductivity type), the same effects as in the present embodiment can be obtained. The n type impurity concentration in the n + type is higher than the n type impurity concentration in the n− type.

  Next, a method for manufacturing the semiconductor device 100i according to the second embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different part from 1st Embodiment.

  In the step of FIG. 2B (first etching step), the second region is etched until the second region is removed and the surface SB1 of the semiconductor substrate SB is exposed. Specifically, the first polycrystalline silicon film 103-1i is etched using the hard mask 104-1 as a mask. That is, the second region is etched until the second region not covered with the hard mask 104-1 in the first polycrystalline silicon film 103-1i is removed. Thereby, the exposed side surface of the first pattern PT1i, that is, the exposed side surface SF1i of the first region 103-1ai to be the first pattern PT1i is formed and adjacent to the first region 103-1ai. The surface SB1 of the semiconductor substrate SB is exposed. Here, the exposed side surface SF1i corresponds to substantially the entire side surface of the first pattern PT1i.

  In the step (oxidation step) of FIG. 2C, the side surface SF1i of the first region 103-1ai in the first polycrystalline silicon film 103-1i and the semiconductor substrate SB exposed in the step of FIG. The surface SB1 is oxidized. Thereby, the oxidized portion near the side surface in the first region 103-1ai becomes the oxide film 105-1ai, and the non-oxidized portion in the first region 103-1ai remains as the polycrystalline silicon portion 103-1a2i. In addition, the thickness of the gate oxide film 102i adjacent to the first region 103-1ai increases.

  Here, if the step of FIG. 2C is not performed, the region 105-5 adjacent to the first polycrystalline silicon film having a high etching rate in the base region becomes the region adjacent to the second polycrystalline silicon film. In comparison, it takes a longer time to be exposed to the plasma through the thin gate oxide film, and the plasma is more easily damaged. Therefore, in the present embodiment, the thickness of the gate oxide film 102i adjacent to the first region 103-1ai is increased. At this time, the region 105-5 adjacent to the first polycrystalline silicon film can also be oxidized. This has the effect of reducing defects (damage) in the region 105-5. This effect becomes greater as the gate oxide film becomes thinner.

  Next, an example of an imaging sensor (MOS type sensor) included in the semiconductor device of the present invention is shown in FIG. The imaging sensor 30 shown in FIG. 3 includes a pixel array region 100, a constant current source region 200, a column amplifier region 300, a storage capacitor region 400, an output amplifier region 450, a vertical scanning circuit 500, and a horizontal scanning circuit 600.

  In the pixel array region 100, a plurality of pixels 6 are arranged in a matrix in the XY direction. Each pixel 6 includes a photoelectric conversion unit 1, a transfer unit 2, a charge / voltage conversion unit FD, a reset unit 3, an output unit 4, and a selection unit 5. The photoelectric conversion unit 1 generates and accumulates charges corresponding to light. The photoelectric conversion unit 1 is, for example, a photodiode. The transfer unit 2 transfers the charge generated in the photoelectric conversion unit 1 to the charge voltage conversion unit FD. The transfer unit 2 is, for example, a transfer transistor, and is turned on when an active level transfer control signal is received by the gate from the vertical scanning circuit 500, whereby the charge generated in the photoelectric conversion unit 1 is transferred to the charge-voltage conversion unit FD. Forward. The charge-voltage converter FD converts the transferred charge into a voltage. The charge-voltage conversion unit FD is, for example, a floating diffusion. The reset unit 3 resets the charge-voltage conversion unit FD. The reset unit 3 is, for example, a reset transistor, and resets the charge-voltage conversion unit FD by turning on when receiving an active level reset control signal from the vertical scanning circuit 500 at the gate. The output unit 4 outputs a signal corresponding to the voltage of the charge-voltage conversion unit FD to the column signal line PV. The output unit 4 is, for example, an amplification transistor, and performs a source follower operation together with the constant current source 7 connected to the column signal line PV, so that a signal corresponding to the voltage of the charge voltage conversion unit FD is sent to the column signal line PV. Output. That is, the output unit 4 outputs a noise signal corresponding to the voltage of the charge voltage conversion unit FD to the column signal line PV in a state where the charge voltage conversion unit FD is reset by the reset unit 3. The output unit 4 outputs an optical signal corresponding to the voltage of the charge voltage conversion unit FD to the column signal line PV in a state where the charge of the photoelectric conversion unit 1 is transferred to the charge voltage conversion unit FD by the transfer unit 2. The selection unit 5 puts the pixel 6 into a selected state / non-selected state. The selection unit 5 is, for example, a selection transistor, and is turned on when an active level selection control signal is received by the gate from the vertical scanning circuit 500 to place the pixel 6 in a selected state. When the selection unit 5 receives a non-active level selection control signal from the vertical scanning circuit 500 at the gate, the selection unit 5 turns off the pixel 6.

  The vertical scanning circuit 500 scans the pixel array region 100 in the vertical direction (Y direction) to select a readout row from which a signal in the pixel array region 100 is to be read, and from the pixels in the readout row to the plurality of column signal lines PV. A signal is output. For example, the vertical scanning circuit 500 drives the transistors in the pixels in the readout row of the pixel array region 100 as described above. The vertical scanning circuit 500 includes, for example, a shift register and a decoder.

  The constant current source region 200 is a region in which a plurality of constant current sources 7 respectively connected to a plurality of column signal lines PV are arranged in the X direction. The column amplifier region 300 is a region where a plurality of column amplifier units 11 are arranged in the X direction. Each column amplifier unit 11 may be configured to include, for example, a differential amplifier 8, a clamp capacitor 9, a feedback capacitor 10, and a clamp control switch CS. Each column amplifier unit 11 can be a difference circuit (clamp CDS circuit) that outputs a difference signal between an optical signal and a noise signal. The storage capacitor region 400 is a region in which a plurality of storage capacitor units 18 are arranged in the X direction. Each holding capacitor unit 18 can include a noise signal writing transistor 12, an optical signal writing transistor 13, a noise signal holding capacitor 14, an optical signal holding capacitor 15, a noise signal transfer transistor 16, and an optical signal transfer transistor 17. . The output amplifier area 450 includes the output amplifier 19.

  The horizontal scanning circuit 600 is a scanning circuit for driving the reset level transfer transistor 16 and the optical signal level transfer transistor 17 in each storage capacitor region 400. The horizontal scanning circuit 600 includes, for example, a shift register and a decoder.

  In the MOS type sensor as shown in FIG. 3, one type of conductive transistor is often used in the pixel array region 100. On the other hand, different types of conductive transistors are often used for the differential amplifier 8 and the scanning circuits 500 and 600 in the column amplifier region 300. In the column amplifier region 300, transistors of different conductive types are unevenly distributed. Exists. In a MOS type sensor in which transistors of different conductivity types are present in a non-uniform distribution, the manner in which the etching gas contributes to the surface of the polycrystalline silicon differs depending on the location. As a result, the difference in etching rate when the first polycrystalline silicon film and the second polycrystalline silicon film are simultaneously etched is further expanded. Therefore, by applying the etching method of the present invention to the MOS type sensor, the effect of reducing the difference in the processing shape (width) of the polycrystalline silicon in the MOS type sensor becomes remarkable.

Claims (7)

Forming a first polycrystalline silicon film containing a first conductivity type impurity and a second polycrystalline silicon film containing a second conductivity type impurity on a semiconductor substrate;
Patterning the first polycrystalline silicon film by etching to form a first pattern, and patterning the second polycrystalline silicon film by etching to form a second pattern; and
With
The patterning step includes
A first etching step of performing etching so as to expose each side surface of the first pattern and the second pattern;
An oxidation step of oxidizing the exposed side surface to form an oxide film on the side surface;
Etching in a state where the side surface is protected by the oxide film, and completing a patterning of the first polycrystalline silicon film and the second polycrystalline silicon film;
A method for manufacturing a semiconductor device, comprising: The first polycrystalline silicon film is
A first region to be the first pattern;
A second region to be removed;
Including
The second polycrystalline silicon film is
A third region to be the second pattern;
A fourth region to be removed;
Including
In the first etching step, the second region is etched from the surface to the first depth, and the fourth region is etched from the surface to the second depth.
In the oxidation step, the upper surface of each of the second region and the fourth region left in the first etching step is oxidized to form a second oxide film on the upper surface, and a portion that has not been oxidized is removed. Leave as crystalline silicon part,
The second etching step includes
A first step of etching the second oxide film until the polycrystalline silicon portion is exposed;
A second step of etching the polycrystalline silicon portion until a surface of the semiconductor substrate is exposed;
The method of manufacturing a semiconductor device according to claim 1, comprising: The n-type impurity concentration in the first conductivity type is higher than the n-type impurity concentration in the second conductivity type,
The first depth is greater than the second depth;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the second oxide film in the second region is thicker than the second oxide film in the fourth region. The n-type impurity concentration in the first conductivity type is higher than the n-type impurity concentration in the second conductivity type,
The first polycrystalline silicon film is
A first region to be the first pattern;
A second region to be removed;
Including
The second polycrystalline silicon film is
A third region to be the second pattern;
A fourth region to be removed;
Including
In the first etching step, the second region is etched until the surface of the semiconductor substrate is exposed by removing the second region, and the fourth region is etched from the surface to the second depth. And
In the oxidation step, the surface of the semiconductor substrate exposed in the first etching step is oxidized, and the upper surface of the fourth region left in the first etching step is oxidized to form a second surface on the upper surface. The portion that was not oxidized by forming the oxide film was left as a polycrystalline silicon portion,
The second etching step includes
A first step of etching the second oxide film until the polycrystalline silicon portion is exposed;
A second step of etching the polycrystalline silicon portion until a surface of the semiconductor substrate is exposed;
The method of manufacturing a semiconductor device according to claim 1, comprising: 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the oxidation step, oxidation is performed using a gas containing oxygen. 6. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the oxidation step, oxidation is performed using a gas containing water vapor. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes an imaging sensor.

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