JP2010010402A - Method of manufacturing semiconductor device and method of manufacturing solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in contact resistance by securing stability of the contact resistance. <P>SOLUTION: A method of manufacturing a semiconductor device includes steps of: forming a first metal silicide layer 13 on the silicon region 12 of a substrate 11; forming an insulating film 14 covering the first metal silicide layer 13 on the substrate 11; forming a contact hole 15 communicating with the first metal silicide layer 13 in the insulating film 14; forming a second metal layer 16 to be silicified on the internal surface of the contact hole 15 and the insulating film 14; and forming a second metal silicide layer 17 on the first metal silicide layer 13 by making the second metal layer 16 react with silicon of a bottom portion of the contact hole 15. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a metal silicide layer in a contact portion and a method for manufacturing a solid-state imaging device.

As a conventional semiconductor device, a MOS transistor will be described with reference to a schematic sectional view of FIG.
As shown in FIG. 12, in the MOS transistor 301, for example, a gate electrode 313 is formed on a silicon substrate 311 via a gate insulating film 312. Source / drain regions 323 and 324 are formed on the silicon substrate 311 on both sides of the gate electrode 313 via low-concentration diffusion layers 321 and 322. Side walls 314 and 315 are formed on both sides of the gate electrode 313. Metal silicide layers 325 and 326 are formed on the source / drain regions 323 and 324, respectively. Further, an interlayer insulating film 331 is formed on the silicon substrate 311 so as to cover the MOS transistor 301 having the above configuration. In the interlayer insulating film 331, contact holes 332, 333, etc., which communicate with the source / drain regions 323, 324, etc. are formed. Although not shown, a contact hole leading to the gate electrode 313 and the like is also formed. In the contact holes 332 and 333, wirings 341 and 342 are formed.

In the MOS transistor 301, since the metal silicide layers 325 and 326 are formed on the source / drain regions 323 and 324, the contact resistance is reduced as compared with the case where the metal silicide layer is not formed.
However, with the miniaturization of the contact holes 332 and 333, the stability of the contact resistance may be insufficient and the contact resistance may vary.

As a conventional solid-state imaging device, for example, in a logic part of a CMOS sensor, a metal silicide layer is formed on a silicon region where a contact is formed in order to reduce the contact resistance. For example, in the MOS transistor in the logic portion, a metal silicide layer is formed on the source / drain region of the MOS transistor as described with reference to FIG. 12 (see, for example, Patent Document 1).
However, with the miniaturization of the contact hole, the stability of the contact resistance may be insufficient and the contact resistance may vary.

  Further, when a metal silicide layer is formed in the contact portion of the pixel portion of the solid-state imaging device, there is a concern about contamination (contamination) with respect to the photoelectric conversion portion of the pixel portion, and there is a concern about deterioration of imaging characteristics due to the contamination.

Further, in the conventional CMOS sensor, the contact with the shi region in the pixel portion is reduced in resistance by using a titanium barrier film formed on the inner surface of the contact hole when the contact is formed.
However, in the method using the titanium barrier film, there is a limit to the reduction in resistance with respect to the silicon region as the contact hole is miniaturized. As a result, the transfer rate is also deteriorated.

JP 2003-273343 A

  The problem to be solved is that, as the contact hole is miniaturized, the stability of the contact resistance may be insufficient and the contact resistance varies.

  The present invention makes it possible to ensure the stability of contact resistance and suppress variations in contact resistance.

  The semiconductor device of the present invention includes a step of forming a first metal silicide layer on a silicon region of a substrate, a step of forming an insulating film covering the first metal silicide layer on the substrate, and the step of forming the insulating film on the insulating film. Forming a contact hole leading to the first metal silicide layer; forming a metal layer to be silicided on the inner surface of the contact hole and on the insulating film; and silicon at the bottom of the metal layer and the contact hole; And a step of forming a second metal silicide layer on the first metal silicide layer.

  In the semiconductor device of the present invention, the two metal silicide layers of the first metal silicide layer and the second metal silicide layer are formed at the bottom of the contact hole, so that the stable metal silicide layer can be obtained without changing the transistor characteristics. Is formed.

  The solid-state imaging device according to the present invention includes a step of forming a pixel portion having a photoelectric conversion portion on a silicon substrate, a logic portion that processes signal charges output from the pixel portion, and a silicon region on the logic portion. Forming a first metal silicide layer; forming an insulating film covering the first metal silicide layer on the silicon substrate; and a first contact hole communicating with the first metal silicide layer in the insulating film; Forming a second contact hole that communicates with the contact region of the pixel portion; and forming a silicided metal layer on the inner surface of the first contact hole, the inner surface of the second contact hole, and the insulating film; And reacting the metal layer with silicon at the bottom of the first contact hole and silicon at the bottom of the second contact hole. And a step of forming a third metal silicide layer on the bottom of the second contact hole to form a second metal silicide layer on the first metal silicide layer.

  In the solid-state imaging device of the present invention, two metal silicide layers of the first metal silicide layer and the second metal silicide layer are formed at the bottom of the first contact hole. As a result, a stable metal silicide layer is formed without changing transistor characteristics, and variations in contact resistance are suppressed. In the pixel portion, since the third metal silicide layer is formed only at the bottom of the second contact hole, the contact resistance of the pixel portion can be reduced. In the step of forming the third metal silicide layer, since the photoelectric conversion portion formed on the silicon substrate is covered with the insulating film formed on the silicon substrate, the step of forming the third metal silicide layer. Therefore, the photoelectric conversion part is not contaminated.

  The semiconductor device of the present invention has an advantage that variation in contact resistance can be suppressed because a stable metal silicide layer is formed without changing transistor characteristics.

  The solid-state imaging device of the present invention has an advantage that variations in contact resistance can be suppressed because a stable metal silicide layer is formed in the logic portion without changing transistor characteristics. Further, since the contact resistance can be reduced in the pixel portion, there is an advantage that the transfer rate of image information (photoelectrically converted signal charge) from the pixel portion can be increased. In addition, since the contact resistance can be reduced, the element can be miniaturized. Furthermore, when the third metal silicide layer is formed only at the bottom of the second contact hole of the pixel portion, it is possible to prevent contamination of the photoelectric conversion portion, so that the high-quality pixel without impairing the photoelectric conversion characteristics. The part can be formed.

  An embodiment (example) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional view of FIG. 1 and the flowcharts of FIGS.

As shown in FIG. 1A, a first metal silicide layer 13 is formed on the silicon region 12 of the substrate 11. For example, a silicon substrate is used as the substrate 11. For example, the active region formed in the silicon substrate becomes the silicon region 12. Alternatively, although not shown, an SOI (Silicon on insulator) substrate is used as the substrate 11. The silicon layer of this SOI substrate becomes the silicon region 12. Alternatively, although not shown, a gate electrode made of polysilicon formed on the substrate 11 via a gate insulating film can be used as the silicon region 12.
Hereinafter, as an example, the case where the substrate 11 made of a silicon substrate has the silicon region 12 made of an active region will be described.

Next, a first metal layer (not shown) for silicidation is formed on the surface of the silicon region 12 by a normal silicidation process, and then heat treatment is performed, so that the metal of the first metal layer and the silicon region are formed. The first metal silicide layer 13 is formed by reacting with 12 silicon.
For example, cobalt or nickel is used for the first metal layer. Moreover, the said other metal which can form metal silicide can also be used. For example, a so-called refractory metal such as hafnium, titanium, molybdenum, or tungsten, platinum, or the like can be used.

As an example, the first metal layer is formed of cobalt by sputtering. For example, cobalt is formed to a thickness of 8 nm. Next, a titanium nitride film (not shown) is formed to a thickness of, for example, 20 nm by sputtering.
Next, the first metal layer is made to react with the underlying silicon by rapid thermal annealing (RTA) to form the first metal silicide layer 13 made of cobalt silicide. This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 500 ° C. and 30 seconds.
Thereafter, the titanium nitride film (not shown) and the first metal layer (not shown) are removed.
Furthermore, cobalt silicide is stabilized by rapid thermal processing (RTA: Rapid Thermal Annealing). This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 850 ° C. and 30 seconds.
The heat treatment conditions are appropriately changed depending on the material, film thickness, etc. of the first metal layer to be silicided. Further, the present invention is not limited to lamp annealing, and other heat treatment methods can be used.
Note that the first metal layer can be silicided without forming the titanium nitride film.

  After the first metal silicide layer 13 is formed, the first metal layer that has not undergone a silicide reaction is removed.

  Next, an insulating film 14 that covers the first metal silicide layer 13 is formed on the substrate 11. For example, the insulating film 14 is formed of a silicon nitride film and a silicon oxide film.

  For example, as shown in the flowchart of FIG. 2, “Formation of the first insulating film” S12 is performed after “Formation of the first metal silicide layer” S11. In the “formation of the first insulating film” S 12, a first insulating film that covers the first metal silicide layer 13 is formed on the substrate 11. This first insulating film is formed of, for example, a silicon nitride film, and has a thickness of, for example, 50 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 400 ° C., for example.

  Next, “formation of the second insulating film” S13 is performed. In the “formation of second insulating film” S13, a second insulating film is formed on the first insulating film. This second insulating film is formed of, for example, a silicon oxide film and has a thickness of, for example, 650 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 480 ° C., for example.

  Next, the surface of the second insulating film is planarized in “planarization” S14. For this planarization, for example, chemical mechanical polishing (CMP) is used.

  Next, in the “first heat treatment” S15, the first heat treatment is performed. The first heat treatment is performed by, for example, rapid thermal annealing (RTA), and is performed in a nitrogen atmosphere at 450 ° C., for example.

Next, “formation of a third insulating film” S16 is performed. In this “formation of the third insulating film” S16, a third insulating film is formed on the second insulating film. This third insulating film is formed of, for example, a silicon oxide film, and has a thickness of, for example, 250 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 400 ° C., for example.
In this way, the insulating film 14 is formed.

Next, “contact hole formation” S17 is performed. In “contact hole formation” S17, a resist mask (not shown) for forming a contact hole is formed by resist coating and lithography.
Next, the insulating film 14 is etched using the resist mask to form a contact hole 15 leading to the first metal silicide layer 13.
Note that a part of the insulating film 14 may be formed of an organic insulating film. When the uppermost layer of the insulating film 14 is formed of an organic insulating film, the mask is formed of an inorganic material such as silicon oxide or silicon nitride, or an organic film having etching selectivity with respect to the organic insulating film. .
In the etching, first, the third insulating film and the second insulating film made of silicon oxide are etched, and the etching is temporarily stopped on the first insulating film made of silicon nitride. In this etching, for example, a fluorocarbon gas can be used as an etching gas. Thereafter, the first insulating film is selectively etched away with respect to the third insulating film and the second insulating film to complete the contact hole 15. In this etching, for example, a fluorocarbon gas can be used as an etching gas. By etching in this way, etching damage to the base of the contact hole 15 can be minimized.
After the contact hole 15 is formed, the resist mask is removed.
Thereafter, “formation of second metal silicide layer” S18 is performed. This “formation of the second metal silicide layer” S18 will be described below with reference to the flowcharts of FIGS.

  Next, as shown in FIGS. 1 (2) and 3, “preprocessing” S21 is performed. In the “pretreatment” S21, for example, a natural oxide film, organic matter, and the like on the bottom surface of the contact hole 15 where the second metal layer is to be formed next are removed. For example, a post-cleaning process after the lithography process can be substituted.

Next, “formation of second metal layer” S22 is performed. In the “formation of the second metal layer” S22, the second metal layer 16 to be silicided is formed on the inner surface of the contact hole 15 and the insulating film. For example, the second metal layer 16 is the same as the first metal layer used to form the first metal silicide layer 13.
For example, cobalt or nickel is used for the second metal layer 16. Further, the above-described metals capable of forming metal silicide can also be used.

  As an example, the second metal layer 16 is formed of cobalt by sputtering. For example, cobalt is formed to a thickness of 8 nm. Next, a titanium nitride film (not shown) is formed to a thickness of, for example, 20 nm by sputtering.

Next, as shown in FIGS. 1 (3) and 3, "first heat treatment" S23 is performed. In the “first heat treatment” S23, the second metal layer 16 (see FIG. 1B) and the bottom silicon of the contact hole 15 are reacted to form a second metal on the first metal silicide layer 13. A silicide layer 17 is formed.
For example, the second metal layer 16 is reacted with the underlying silicon by rapid thermal annealing (RTA) to form the second metal silicide layer 17 made of cobalt silicide. This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 500 ° C. and 30 seconds.

  Thereafter, “removal of unreacted second metal layer” S24 is performed. In this “removal of the unreacted second metal layer” S24, the titanium nitride film (not shown) and the unreacted second metal layer 16 (see FIG. 1B) which is not silicided are removed.

Further, “second heat treatment” S25 is performed. In this “second heat treatment” S25, cobalt silicide (CoSi) is stabilized by rapid thermal processing (RTA: Rapid Thermal Annealing) to form CoSi ₂ . This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 850 ° C. and 30 seconds.
The heat treatment conditions are appropriately changed depending on the material, film thickness, etc. of the second metal layer 16 (see FIG. 1B) to be silicided. Further, the present invention is not limited to lamp annealing, and other heat treatment methods can be used.
Note that the second metal layer 16 can be silicided without forming the titanium nitride film.

  The formation process of the second metal silicide layer 17 can also be applied to the formation process of the first metal silicide layer 13.

  Next, as shown in FIG. 1 (4), a barrier film 18 is formed on the inner surface of the contact hole 15 and the insulating film 14. Further, a conductive film 19 is formed so as to fill the inside of the contact hole 15. The barrier film 18 is formed of, for example, a laminated film of a titanium film and a titanium nitride film or a tantalum nitride film. The conductive film 19 is made of, for example, tungsten.

Thereafter, although not shown in the drawing, the excess conductive film 19 and barrier film 18 on the insulating film 14 are removed, and a plug made of the conductive film 19 is formed in the contact hole 15 through the barrier film 18.
Then, by performing a heat treatment, a natural oxidation-reduction reaction occurs between the second metal silicide layer 17 (including the first metal silicide layer 13) and titanium which is the barrier film 18 to obtain a low-resistance contact. it can.

  The mechanism of silicidation in the above embodiment will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 4A, a second metal layer 16 (only the bottom of the contact hole 15 is shown in the drawing) is formed on the bottom of the contact hole 15 and the surface of the insulating film 14.
Thereafter, heat treatment is performed as shown in FIG. This heat treatment is, for example, 500 ° C. for 30 seconds. In this heat treatment, silicon in the first metal silicide layer 13 is supplied into the second metal layer 16. At the same time, silicon in the silicon region 12 is supplied into the first metal silicide layer 13.
The supply of silicon from the first metal silicide layer 13 to the second metal layer 16 and the supply of silicon from the silicon region 12 to the first metal silicide layer 13 proceed in stages.
However, since the above reaction is very slight, the layer on the first metal silicide layer 13 side of the second metal layer 16 is merely converted into a metal silicide, and as shown in FIG. Including the portion of the second metal silicide layer 17 in which the metal layer 16 is silicided hardly affects the film thickness of the first metal silicide layer 13.

  Next, the silicidation technique based on the semiconductor device manufacturing method was applied to the source / drain regions of the insulated gate field effect transistor. Then, the relationship between the on-current and the threshold voltage was examined. The result is shown in FIG. In FIG. 5, open circles are transistors in which the first metal silicide layer 13 and the second metal silicide layer 17 are formed of cobalt silicide layers by the manufacturing method of the present invention (hereinafter referred to as the transistor of the present invention). The black circles indicate that the first metal silicide layer 13 and the second metal silicide layer 17 are formed by the cobalt silicide layer by the manufacturing method of the present invention, but the second heat treatment after the formation of the second metal silicide layer 17 is performed. This is a transistor that was not used (hereinafter referred to as the transistor of the first comparative example). Open triangles are transistors in which only the first metal silicide layer 13 is formed of a cobalt silicide layer by a conventional manufacturing method (hereinafter referred to as a transistor of the second comparative example).

  As shown in FIG. 5, there was no difference in on-current-threshold voltage characteristics between the transistor of the present invention and the transistors of the first and second comparative examples. That is, even when the method for manufacturing a semiconductor device of the present invention is applied to the source / drain region of an insulated gate field effect transistor, the second metal silicide layer 17 does not slip through the source / drain region. It was found that such problems did not occur.

  Next, for the transistor of the present invention and the transistors of the first and second comparative examples, the relationship between the contact resistance variation σ and the contact resistance value was examined. The result will be described with reference to FIG. In FIG. 6, white square marks are transistors (hereinafter referred to as transistors of the present invention) in which the first metal silicide layer 13 and the second metal silicide layer 17 are formed of cobalt silicide layers by the manufacturing method of the present invention. In the white circles, the first metal silicide layer 13 and the second metal silicide layer 17 are formed by the cobalt silicide layer by the manufacturing method of the present invention, but the second heat treatment after the formation of the second metal silicide layer 17 is performed. This is a transistor that was not used (hereinafter referred to as the transistor of the first comparative example). A triangle mark is a transistor (hereinafter referred to as a transistor of the second comparative example) in which only the first metal silicide layer 13 is formed of a cobalt silicide layer by a conventional manufacturing method.

As shown in FIG. 6, when the contact resistance variation state is the same, it was found that the transistor of the present invention has the greatest contact resistance reduction effect.
Further, by performing the silicidation process twice without performing the second heat treatment as shown in the first comparative example, the contact resistance is improved compared to the case of the single silicidation process as in the second comparative example. When the variation state is the same, the effect of reducing the contact resistance is large.

  Therefore, by forming the first metal silicide layer 13 and the second metal silicide layer 17 as in the method of manufacturing a semiconductor device of the present invention, the contact resistance can be greatly reduced as compared with the case of only one silicidation step. . Therefore, the operation speed of the transistor can be improved. Further, since the contact resistance can be reduced, the contact area can be reduced while maintaining the contact resistance. As a result, the size of the transistor can be reduced.

  In the method for manufacturing the semiconductor device, the first metal silicide layer 13 and the second metal silicide layer 17 are formed of cobalt silicide, but may be formed of nickel silicide.

  When the first metal silicide layer 13 and the second metal silicide layer 17 are formed of nickel silicide, the following is performed.

  The first metal layer and the second metal layer are formed of a nickel layer instead of a cobalt layer.

  For example, as shown in the flowcharts of FIGS. 1B and 7, “preprocessing” S31 is performed. This “pretreatment” S31, for example, removes a natural oxide film, organic matter, etc. on the surface of the silicon region 12 where the second metal layer to be formed next is formed. For example, a post-cleaning process after the lithography process can be substituted.

Next, “formation of second metal layer” S32 is performed. In this “formation of the second metal layer” S 32, the second metal layer 16 to be silicided is formed on the inner surface of the contact hole 15 and on the insulating film 14. For example, the second metal layer 16 is the same as the first metal layer used to form the first metal silicide layer 13.
For example, nickel is used for the second metal layer 16. For example, nickel is formed to a thickness of 10 nm by sputtering, for example. Next, a titanium nitride film (not shown) is formed to a thickness of, for example, 20 nm by sputtering.

Next, as shown in FIGS. 1 (3) and 7, "first heat treatment" S33 is performed. In the “first heat treatment” S33, the second metal layer 16 (see FIG. 1B) and the bottom silicon of the contact hole 15 are reacted to form a second metal on the first metal silicide layer 13. A silicide layer 17 is formed.
For example, the second metal layer 16 and the underlying silicon are reacted by rapid thermal processing (RTA: Rapid Thermal Annealing) to form the second metal silicide layer 17 made of nickel silicide. This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 350 ° C. and 30 seconds.

  Thereafter, “removal of unreacted second metal layer” S34 is performed. In this “removal of the unreacted second metal layer” S34, the titanium nitride film (not shown) and the unreacted second metal layer 16 (see FIG. 1B) that has not been silicided are removed.

Further, “second heat treatment” S35 is performed. In this “second heat treatment” S35, NiSi ₂ is formed by stabilizing nickel silicide (NiSi) by rapid thermal annealing (RTA). This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 500 ° C. and 30 seconds.
The heat treatment conditions are appropriately changed depending on the film thickness of the second metal layer 16 to be silicided. Further, the present invention is not limited to lamp annealing, and other heat treatment methods can be used.
Note that the second metal layer 16 can be silicided without forming the titanium nitride film.

  The nickel silicide layer forming step can also be applied to the first metal silicide layer 13 forming step.

  Next, an embodiment (example) according to the method for manufacturing a solid-state imaging device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 8 and the cross-sectional views of the manufacturing steps of FIGS.

  First, as shown in FIG. 8, a pixel portion 112 having a photoelectric conversion portion 121, a transfer portion 122, an in-pixel transistor 123, and the like on a silicon substrate 111, and a plurality of signal charges output from the pixel portion 112 are processed. A logic portion 113 including transistors 131 and 132 is formed.

  At that time, first metal silicide layers 141 to 144 are formed in the source / drain regions 133 to 136 of the transistors 131 and 132 of the logic unit 113.

Next, an insulating film 151 that covers the pixel portion 112 and the logic portion 113 is formed.
Further, first contact holes 152 and 153 communicating with the source / drain regions 134 of the transistor 131 and the gate electrode 138 of the transistor 132 in the logic portion 113 are formed in the insulating film 151. In addition, second contact holes 154 and 155 that are connected to the gate electrode 124 of the transfer unit 122 and the source / drain region 126 of the in-pixel transistor 123, which are contact regions of the pixel unit 112, are formed. The first contact holes 152 and 153 and the second contact holes 154 and 155 are formed simultaneously, for example.

  Thereafter, second metal silicide layers 161 and 162 are formed at the bottoms of the first contact holes 152 and 153 formed in the logic unit 113. At the same time, third metal silicide layers 165 and 166 are formed at the bottoms of the second contact holes 154 and 155 formed in the pixel portion 112.

  In the insulating film 151, contact holes that lead to the source / drain regions, the gate electrode, and the like are also formed in the source / drain regions, the gate electrode, and the like (not shown). Further, a second metal silicide layer is formed at the bottom of the contact holes in the same manner as described above.

  Hereinafter, a detailed method for forming the second metal silicide layers 161 and 162 and the third metal silicide layers 165 and 166 will be described with reference to FIGS. In the drawings, the source / drain regions 126 of the transistors in the pixel are representatively shown on the left side of each drawing, and the source / drain regions 134 of the transistors in the logic portion are typically shown on the right side of the drawings.

First, as shown in FIG. 9A, a first metal layer (not shown) for silicidation is formed on the source / drain region 134 of the transistor, which is a silicon region of the logic portion, by a normal silicidation process. Then, heat treatment is performed to react the metal of the first metal layer with the silicon of the source / drain region 134 to form the first metal silicide layer 142.
For example, cobalt or nickel is used for the first metal layer. Moreover, the said other metal which can form metal silicide can also be used. For example, a so-called refractory metal such as hafnium, titanium, molybdenum, or tungsten, platinum, or the like can be used.

As an example, the first metal layer is formed of cobalt by sputtering. For example, cobalt is formed to a thickness of 8 nm. Next, a titanium nitride film (not shown) is formed to a thickness of, for example, 20 nm by sputtering.
Next, the first metal layer and the underlying silicon are reacted by rapid thermal processing (RTA: Rapid Thermal Annealing) to form a first metal silicide layer 142 made of cobalt silicide. This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 500 ° C. and 30 seconds.
Thereafter, the titanium nitride film (not shown) and the first metal layer (not shown) are removed.
Further, cobalt silicide is modified to CoSi ₂ and stabilized by rapid thermal annealing (RTA). This rapid heating process is performed by lamp annealing, for example. The heating conditions are, for example, 850 ° C. and 30 seconds.
The heat treatment conditions are appropriately changed depending on the material, film thickness, etc. of the first metal layer to be silicided. Further, the present invention is not limited to lamp annealing, and other heat treatment methods can be used.
Note that the first metal layer can be silicided without forming the titanium nitride film.

  After the first metal silicide layer 142 is formed, the first metal layer that has not undergone a silicide reaction is removed.

Next, an insulating film 151 that covers the first metal silicide layer 142 is formed on the silicon substrate 111. The insulating film 151 is formed of, for example, a silicon nitride film and a silicon oxide film.
For example, a first insulating film that covers the first metal silicide layer 142 is formed on the silicon substrate 111. This first insulating film is formed of, for example, a silicon nitride film, and has a thickness of, for example, 50 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 400 ° C., for example.
Next, a second insulating film is formed on the first insulating film. This second insulating film is formed of, for example, a silicon oxide film and has a thickness of, for example, 650 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 480 ° C., for example.
Next, the surface of the second insulating film is planarized. For this planarization, for example, chemical mechanical polishing (CMP) is used.
Next, heat treatment is performed. This heat treatment is performed by, for example, rapid heat treatment (RTA), for example, in a nitrogen atmosphere at 450 ° C.
Next, a third insulating film is formed on the second insulating film. This third insulating film is formed of, for example, a silicon oxide film, and has a thickness of, for example, 250 nm. A CVD method is used as the film forming method, and the film forming temperature is set to 400 ° C., for example.
In this way, the insulating film 151 is formed.

Next, a resist mask (not shown) for forming contact holes is formed by resist coating and lithography techniques. Next, using the resist mask, the insulating film 151 is etched to form a second contact hole 155 that communicates with the source / drain region 126. At the same time, a first contact hole 152 leading to the first metal silicide layer 142 is formed.
Note that part of the insulating film 151 can be formed of an organic insulating film. When the uppermost layer of the insulating film 151 is formed of an organic insulating film, the mask is formed of an inorganic material such as silicon oxide or silicon nitride, or an organic film having etching selectivity with respect to the organic insulating film. .
In the etching, first, the third insulating film and the second insulating film made of silicon oxide are etched, and the etching is temporarily stopped on the first insulating film made of silicon nitride. In this etching, for example, a fluorocarbon gas can be used as an etching gas. Thereafter, the first insulating film is selectively removed by etching with respect to the third insulating film and the second insulating film, whereby the first contact hole 152 and the second contact hole 155 are completed. In this etching, for example, a fluorocarbon gas can be used as an etching gas. By etching in this way, etching damage to the base of the first contact hole 152 and the second contact hole 155 can be minimized.
After forming the first contact hole 152 and the second contact hole 155, the resist mask is removed.

Next, as shown in FIG. 9B, the second metal layer 16 to be silicided is formed on the inner surfaces of the first contact hole 152 and the second contact hole 155 and on the insulating film 151. For example, the second metal layer 16 is the same as the first metal layer used to form the first metal silicide layer 142.
As an example, the second metal layer 16 is formed of cobalt by sputtering. For example, cobalt is formed to a thickness of 8 nm. Next, a titanium nitride film (not shown) is formed to a thickness of, for example, 20 nm by sputtering.

Next, as shown in FIG. 10 (3), the second metal layer 16 (see FIG. 9 (2)) and the first contact hole 152 are then formed by a first heat treatment (for example, RTA: Rapid Thermal Annealing). Then, the second metal silicide layer 161 is formed on the first metal silicide layer 142 by reacting with silicon at the bottom of the second contact hole 155. At the same time, a third metal silicide layer 166 is formed on the source / drain region 126.
This first heat treatment is performed by lamp annealing, for example. The heating conditions are, for example, 500 ° C. and 30 seconds.
Thereafter, the titanium nitride film (not shown) and the second metal layer 16 are removed. For this removal processing, for example, wet etching is used.
Further, the cobalt silicide is stabilized by a second heat treatment (for example, RTA: Rapid Thermal Annealing). This second heat treatment is performed by lamp annealing, for example. The heating conditions are, for example, 850 ° C. and 30 seconds.
The heat treatment conditions are appropriately changed depending on the material, film thickness, etc. of the second metal layer 16 to be silicided. Further, the present invention is not limited to lamp annealing, and other heat treatment methods can be used.
The second metal layer 16 can be silicided without forming a titanium nitride film.

  Next, as shown in FIG. 10 (4), a barrier film 18 is formed on the inner surfaces of the first contact hole 152 and the second contact hole 155 and the insulating film 151. Further, the conductive film 19 is formed so as to fill the insides of the first contact hole 152 and the second contact hole 155. The barrier film 18 is formed of, for example, a laminated film of a titanium film and a titanium nitride film or a tantalum nitride film. The conductive film 19 is made of, for example, tungsten.

Thereafter, although not shown in the drawing, the excess conductive film 19 and the barrier film 18 on the insulating film 151 are removed, and the first contact hole 152 and the second contact hole 155 are made conductive through the barrier film 18. A plug made of the film 19 is formed.
Then, by performing heat treatment, a natural oxidation-reduction reaction occurs between the second metal silicide layer 161, the third metal silicide layer 166, and titanium which is the barrier film 18, and a low-resistance contact can be obtained.

  In the method for manufacturing the solid-state imaging device, only the bottom of the first contact hole 152 of the pixel portion 112 can be silicided. At this time, since the pixel portion 112 other than the first contact hole 152 is covered with the insulating film 151, for example, the photoelectric conversion portion 121 is not contaminated. In the logic unit 113, even if the second metal silicide layer 161 is formed on the first metal silicide layer 142, as described in the method for manufacturing the semiconductor device, junction leak (junction leak) or on-current (Ion ) And other transistor characteristics are not affected. In the pixel portion, a natural oxidation-reduction reaction occurs between the formed silicide and titanium (Ti) as a barrier metal, and a low-resistance contact can be obtained.

  In the above description, the transistor formed in the logic unit 113 is a MOS transistor. For example, even if a bipolar transistor or a vertical MOS transistor is used instead of this MOS transistor, the method for manufacturing a semiconductor device of the present invention is applied when a contact is formed in a silicon region or a region containing silicon of these transistors. be able to.

  Here, as an example of a CMOS solid-state imaging device, an example of a pixel portion and a logic portion will be described with reference to a circuit configuration diagram of FIG.

  As shown in FIG. 11, a solid-state imaging device (CMOS type image sensor) 201 includes a pixel unit 210 in which pixels 211 including photoelectric conversion elements are two-dimensionally arranged in a matrix, and a control signal line as a peripheral circuit thereof. The logic unit 220 includes a drive circuit 221, a pixel vertical scanning circuit 223, a timing generation circuit 225, and a horizontal scanning circuit 227 that are independently controlled.

  An output signal line 241 is wired for each column and a control signal line is wired for each row of the pixels 211 with respect to the matrix arrangement of the pixels 211. For example, a transfer control line 242, a reset control line 243, and a selection control line 244 are wired as these control signal lines. Further, a reset line 245 for supplying a reset voltage is wired to each of the pixels 211.

  An example of the circuit configuration of the pixel 211 is shown. The unit pixel according to this circuit example includes, for example, a photodiode as a photoelectric conversion element in the light receiving unit 231, and is a pixel circuit having four transistors, for example, a transfer transistor 232, a reset transistor 233, an amplification transistor 234, and a selection transistor 235. Yes. Here, as the transfer transistor 232, the reset transistor 233, the amplification transistor 234, and the selection transistor 235, for example, N-channel MOS transistors are used. In the above description, these transistors are referred to as intra-pixel transistors 123 [see, for example, FIG. 8].

  The transfer transistor 232 is connected between the cathode electrode of the photodiode of the light receiving portion 231 and the floating diffusion portion 236 that is a charge-voltage conversion portion, and is subjected to photoelectric conversion by the light receiving portion 231 and accumulated signal charges (here, , Electrons) are transferred to the floating diffusion portion 236 when a transfer pulse is applied to the gate electrode (control electrode).

  The reset transistor 233 has a drain electrode connected to the reset line 245 and a source electrode connected to the floating diffusion portion 236, and a reset pulse RST is applied to the gate electrode prior to transfer of signal charges from the light receiving portion 231 to the floating diffusion portion 236. When applied, the potential of floating diffusion portion 236 is reset to reset voltage Vrst.

  The amplification transistor 234 has a gate electrode connected to the floating diffusion portion 236, a drain electrode connected to the pixel power supply Vdd, and outputs the potential of the floating diffusion portion 236 after being reset by the reset transistor 233 as a reset level. The potential of the floating diffusion portion 236 after the signal charge is transferred by the H.232 is output as a signal level.

  For example, the selection transistor 235 has a drain electrode connected to the source electrode of the amplification transistor 234 and a source electrode connected to the output signal line 241. When the selection pulse SEL is applied to the gate electrode, the transistor is turned on, and the pixel 211 is selected and a signal output from the amplification transistor 234 is output to the output signal line 241. Note that the selection transistor 235 may be configured to be connected between the pixel power supply Vdd and the drain electrode of the amplification transistor 234.

  The drive circuit 221 is configured to perform a read operation for reading the signal of each pixel 211 in the read row of the pixel portion 210.

  The pixel vertical scanning circuit 223 is configured by a shift register, an address decoder, or the like, and appropriately generates a reset pulse, a transfer pulse, a selection pulse, etc. While scanning in the vertical direction (vertical direction) on a row-by-row basis, an electronic shutter operation is performed for the electronic shutter row in order to sweep out the signals of the pixels 211 in that row. Then, the electronic shutter operation is performed on the same row (electronic shutter row) by the time corresponding to the shutter speed before the reading scan by the drive circuit 221.

The horizontal scanning circuit 227 is configured by a shift register, an address decoder, or the like, and performs horizontal scanning sequentially for each pixel column of the pixel unit 210.
The timing generation circuit 225 generates a timing signal and a control signal that serve as a reference for operations of the driving circuit 221, the pixel vertical scanning circuit 223, and the like.

  The configuration of the solid-state imaging device (CMOS type image sensor) 201 is an example, and is not limited to the above configuration. The present invention can be applied to a solid-state imaging device having any configuration as long as the solid-state imaging device includes a pixel unit 210 and a logic unit 220 and includes transistors in the pixel unit 210 and the logic unit 220.

It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is a flowchart of the formation process of an insulating film. It is a flowchart of the formation process of a metal silicide layer (cobalt silicide layer). It is the typical sectional view showing the mechanism of silicidation. It is drawing which showed the relationship between on-current and threshold voltage. 6 is a diagram showing a relationship between a contact resistance variation σ and a contact resistance value. It is a flowchart of the formation process of a metal silicide layer (nickel silicide layer). It is a schematic sectional drawing which showed one embodiment (Example) which concerns on the manufacturing method of the solid-state imaging device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the solid-state imaging device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (Example) which concerns on the manufacturing method of the solid-state imaging device of this invention. It is the circuit block diagram which showed an example of the CMOS type solid-state imaging device. It is the typical sectional view showing the conventional MOS transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Substrate, 12 ... Silicon region, 13 ... First metal silicide layer, 14 ... Insulating film, 15 ... Contact hole, 16 ... Second metal layer, 17 ... Second metal silicide layer

Claims (6)

Forming a first metal silicide layer on a silicon region of the substrate;
Forming an insulating film covering the first metal silicide layer on the substrate;
Forming a contact hole leading to the first metal silicide layer in the insulating film;
Forming a metal layer to be silicided on the inner surface of the contact hole and the insulating film;
A method of forming a second metal silicide layer on the first metal silicide layer by reacting the metal layer with silicon at the bottom of the contact hole. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal silicide layer and the second metal silicide layer are made of cobalt silicide or nickel silicide. Removing the unreacted portion of the metal layer after forming the second metal silicide layer;
Forming a conductive film through the titanium film inside the contact hole;
The method for manufacturing a semiconductor device according to claim 1, further comprising an oxidation-reduction reaction between the first metal silicide layer and the second metal silicide layer and the titanium film by heat treatment. Forming a pixel portion having a photoelectric conversion portion on a silicon substrate, and a logic portion for processing a signal charge output from the pixel portion;
Forming a first metal silicide layer on the silicon region of the logic portion;
Forming an insulating film covering the first metal silicide layer on the silicon substrate;
Forming a first contact hole communicating with the first metal silicide layer and a second contact hole communicating with a contact region of the pixel portion in the insulating film;
Forming a metal layer to be silicided on the inner surface of the first contact hole, the inner surface of the second contact hole, and the insulating film;
The metal layer is reacted with silicon at the bottom of the first contact hole and silicon at the bottom of the second contact hole to form a second metal silicide layer on the first metal silicide layer and the second contact And a step of forming a third metal silicide layer at the bottom of the hole. The method for manufacturing a solid-state imaging device according to claim 4, wherein the first metal silicide layer, the second metal silicide layer, and the third metal silicide layer are made of cobalt silicide or nickel silicide. Removing the unreacted portion of the metal layer after forming the second metal silicide layer and the third metal silicide layer;
Forming a conductive film through the titanium film inside each of the first contact hole and the second contact hole;
By heat treatment, the first metal silicide layer, the second metal silicide layer, and the titanium film are oxidized and reduced at the bottom of the first contact hole, and the third metal silicide layer is formed at the bottom of the second contact hole. The method for manufacturing a solid-state imaging device according to claim 4, further comprising an oxidation-reduction reaction between the titanium film and the titanium film.

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