JP2010278080A - Solid-state image pickup device, method for manufacturing the same and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device for suppressing the generation of a dark current and a defect such as a white spot or the like without deteriorating transfer efficiency. <P>SOLUTION: The solid-state image pickup device has a transfer gate electrode 18 having a tapered side surface facing a light receiving portion PD. The light receiving portion PD includes a dark current suppressing region 25 composed of a first conductivity type high concentration impurity region formed on the uppermost layer of a substrate 12 and a charge accumulating region 24 composed of a second conductivity type impurity region formed below the dark current suppressing region 25. The light receiving portion PD generates signal charges corresponding to a light receiving amount. The transfer gate electrode 18 is formed in a region adjacent to the light receiving portion PD above the substrate 12 via the gate insulating film 13, and have sidewalls SW on side surfaces. The side surfaces of the transfer gate electrode 18 are made to be tapered, thereby controlling the thickness of the sidewalls SW formed on the side surfaces. Ion implantation is executed over the sidewalls SW, thereby forming the dark current suppressing region 25 controlled in the forming region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof. The present invention also relates to an electronic device using the solid-state imaging device.

  Solid-state imaging devices are roughly classified into CCD (Charge Coupled Device) type solid-state imaging devices and CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging devices.

  In CCD solid-state imaging devices and CMOS solid-state imaging devices, a dark current suppression area is provided on the photodiode surface side as a countermeasure against pixel defects such as white spots caused by dark current generated by the influence of interface states near the wafer surface. The technique to form is taken. For example, in a photodiode that handles electrons as signal charges, a dark current suppression region is formed by ion implantation of a dense p-type impurity on the surface side of the photodiode. In the dark current suppression region consisting of a p-type high concentration impurity region, dark current is suppressed by recombining electrons that become dark current generated on the photodiode surface with holes of majority carriers, and pixel defects such as white spots Is suppressed.

  However, the formation of a high-concentration impurity region on the surface of the photodiode causes a problem of deterioration in signal charge transfer efficiency. Therefore, a technique for optimally controlling the distance between the transfer gate electrode and the dark current suppression region formed on the surface of the photodiode is necessary as a method for achieving both improvement in transfer efficiency and suppression of defects such as white spots.

  For example, in Patent Document 1 below, in a CMOS type solid-state imaging device, in order to optimize the distance between the transfer gate portion and the dark current suppression region, ions are implanted through the sidewall of the transfer gate electrode, thereby suppressing dark current. It is described that the region is formed by self-alignment.

  13 and 14 show a manufacturing process of a dark current suppression region used in a conventional CMOS solid-state imaging device. 13 and 14 show a manufacturing process in a cross section of a predetermined region including the light receiving portion PD and the transfer transistor.

  As shown in FIG. 13A, a gate insulating film 113 made of, for example, a silicon oxide film is formed on a semiconductor substrate 112 made of silicon, and a desired gate electrode made of, for example, polysilicon is formed on the gate insulating film 113. In FIG. 13A, a transfer gate electrode 118 constituting a transfer transistor, a non-transfer gate electrode of a transistor other than the transfer transistor configured in the pixel region, and a desired transistor (hereinafter referred to as a non-transfer transistor) configured in a peripheral logic circuit. 116. The transfer gate electrode 118 and the non-transfer gate electrode 116 are formed by patterning a polysilicon film into a desired shape by etching. Further, the side surfaces of the transfer gate electrode 118 and the non-transfer gate electrode 116 are etched so as to be substantially perpendicular to the horizontal plane of the semiconductor substrate 112. Then, after the transfer gate electrode 118 and the non-transfer gate electrode 116 are formed, the charge storage region 124 is formed by ion implantation of n-type impurities using a resist mask having an opening only in the light receiving portion PD. At this time, self-aligned ion implantation using the transfer gate electrode 118 as a mask is performed in a region beside the transfer gate electrode 118.

  Thereafter, as shown in FIG. 13B, a silicon nitride film 114 and a silicon oxide film 115 are sequentially formed on the entire surface including the transfer gate electrode 118 and the non-transfer gate electrode 116 by using, for example, a CVD method.

  Thereafter, the entire surface is etched back by, for example, RIE (Reactive Ion Etching). As a result, as shown in FIG. 13C, sidewalls SW made of the silicon nitride film 114 and the silicon oxide film 115 are formed on the side surfaces of the transfer gate electrode 118 and the non-transfer gate electrode 116.

Next, as shown in FIG. 14D, a resist mask 117 is formed so as to cover a region other than the region where the light receiving portion PD is formed, and a p-type impurity is formed on the charge accumulation region 124 constituting the light receiving portion PD. The dark current suppression region 125 is formed by ion implantation at a high concentration. In this case, since the dark current suppression region 125 is formed so as to enter the lower portion of the sidewall SW so that the distance between the dark current suppression region 125 and the transfer gate electrode 118 is optimal, as shown in FIG. ion implantation obliquely as shown by I ₁ is made. In this way, the oblique ion implantation adjusts the distance W between the dark current suppression region 125 and the transfer gate electrode 118, so that dark current can be generated without deteriorating the signal charge transfer efficiency. Effectively suppressed.

Next, as shown in FIG. 14E, a resist mask 119 is formed so as to cover the region where the light-receiving portion PD is formed, and n-type impurities are ion-implanted at a high concentration through the sidewall SW by self-alignment. Then, source / drain regions 120 are formed. These source and drain regions 120, because it is formed by self-alignment of the side walls SW over the injection angle with respect to the horizontal plane of the semiconductor substrate 112 as indicated by arrow I ₂ may be formed by ion implantation of 90 ° .
In this manner, a conventional solid-state imaging device is formed.

JP 2004-128296 A

  As described above, in the conventional method for manufacturing a solid-state imaging device, the dark current suppression region 125 is formed so that the distance between the dark current suppression region 125 formed on the surface side of the light receiving portion PD and the transfer gate electrode 118 is optimal. A method is adopted in which the p-type impurities to be formed are ion-implanted obliquely. Then, by implanting ions obliquely, the dark current suppression region 125 can be implanted down to the side wall SW, and the distance W between the dark current suppression region 125 and the end of the transfer gate electrode 118 is adjusted. As a result, the transfer gate portion formed on the semiconductor substrate 112 below the transfer gate electrode 118 is formed at a position away from the dark current suppression region 125 by an appropriate distance, so that the signal charge transfer efficiency is not deteriorated. Generation of dark current is effectively suppressed.

  However, when the dark current suppression region 125 is formed under the sidewall SW by obliquely implanting impurities as described above, the implantation angle depends on the shape of the transfer gate electrode 118 and the shape of the sidewall SW each time. It is necessary to change the ion implantation conditions.

In recent years, as the number of pixels has increased, a configuration is adopted in which a floating diffusion portion FD from which signal charges are read is shared by a plurality of adjacent pixels. FIG. 15 shows an example in which one floating diffusion portion FD is shared by, for example, two pixels (light receiving portions PD). Thus, if you share a floating diffusion part FD by two pixels, when forming a dark current suppression region 125 at an oblique ion implantation, as shown in FIG. 15, the ion implantation I ₁ direction, I ₃ direction ion implantation is required. In addition, the increase in the number of shared pixels necessitates oblique ion implantation in a different direction, and as a result, the number of ion implantations needs to be increased. With such an increase in the number of processes, there is a concern about a low yield due to a TAT (Turn Around Time) deterioration and a foreign matter adhesion probability increase.

  In view of the above, the present invention provides a solid-state imaging device in which defects such as white spots are suppressed by suppressing generation of dark current without reducing transfer efficiency. Also provided is a method for manufacturing a solid-state imaging device in which the number of steps is reduced and the yield is improved. Furthermore, an electronic device using the solid-state imaging device is provided.

  In order to solve the above problems and achieve the object of the present invention, the solid-state imaging device of the present invention has a transfer gate electrode having a tapered side surface facing the light receiving portion. The light receiving portion is a charge storage composed of a dark current suppression region formed of a first conductivity type high-concentration impurity region formed on the outermost surface of the substrate and a second conductivity type impurity region formed below the dark current suppression region. A signal charge corresponding to the amount of received light is generated. The transfer gate electrode is formed in a region adjacent to the light receiving portion on the upper part of the substrate via a gate insulating film, and has a side wall on the side surface.

  In the solid-state imaging device of the present invention, the side surface of the transfer gate electrode facing the light receiving portion is formed in a tapered shape. For this reason, the sidewall formed on the side surface of the transfer gate electrode facing the light receiving portion is formed to have a small width, and the distance between the dark current suppression region and the end portion of the transfer gate electrode is thereby reduced. Adjusted.

  In the method for manufacturing a solid-state imaging device of the present invention, first, a gate insulating film is formed on a substrate, and an electrode layer is formed thereon. Next, the electrode layer is etched to form a transfer gate electrode having a tapered side surface facing a region where the light receiving portion of the substrate is formed and a non-transfer gate electrode having a vertical side surface. . Next, a step of forming a sidewall on the transfer gate electrode and the non-transfer gate electrode is included. By implanting a desired impurity ion through a sidewall formed on the tapered side surface of the transfer gate electrode, a dark current suppression region is formed by self-alignment on the outermost surface of the region where the light receiving portion of the substrate is formed.

  In the method for manufacturing a solid-state imaging device according to the present invention, the side surface of the transfer gate electrode facing the light receiving portion is formed in a tapered shape. For this reason, the sidewall formed on the side surface facing the light receiving portion of the transfer gate electrode is formed so as to have a small width. Then, by implanting impurities through the sidewall, a dark current suppression region is formed by self-alignment, and the dark current suppression region is formed in a region separated from the end of the transfer gate electrode by the width of the sidewall.

  The electronic apparatus of the present invention includes an optical lens, the above-described solid-state imaging device, and a signal processing circuit.

  According to the present invention, it is possible to accurately control the formation region of the dark current suppression region, and solid-state imaging in which defects such as white spots are suppressed by suppressing generation of dark current without reducing transfer efficiency. A device is obtained. In addition, this solid-state imaging device can provide an electronic device with improved image quality.

1 is a schematic configuration diagram illustrating an entire solid-state imaging device according to a first embodiment of the present invention. It is a cross-sectional block diagram of the predetermined area | region containing light-receiving part PD of the solid-state imaging device which concerns on 1st Embodiment. A to C are manufacturing process diagrams (part 1 to part 3) of the solid-state imaging device according to the first embodiment. D to E are manufacturing process diagrams (part 4 to part 6) of the solid-state imaging device according to the first embodiment. G is a manufacturing process diagram (No. 7) of the solid-state imaging device according to the first embodiment; FIG. 2A and 2B are a plan layout diagram in the case where one floating diffusion portion is shared by two pixels (light receiving portions), and a cross-sectional view along the line A-A ′. A and B are manufacturing process diagrams of a solid-state imaging device according to Comparative Example 1. FIG. A and B are manufacturing process diagrams of a solid-state imaging device according to Comparative Example 2. FIG. A and B are manufacturing process diagrams of a solid-state imaging device according to Comparative Example 4. FIG. AC is a manufacturing process diagram (No. 1 to No. 3) of the solid-state imaging device according to the second embodiment. FIG. 4D is a manufacturing process diagram (part 4) of the solid-state imaging device according to the second embodiment; It is a schematic block diagram of the electronic device which concerns on the 3rd Embodiment of this invention. AC is a manufacturing process diagram (part 1 to part 3) of the solid-state imaging device of the conventional example. D and E are manufacturing process diagrams (parts 4 and 5) of the solid-state imaging device of the conventional example. In the solid-state imaging device of a prior art example, it is a plane layout figure at the time of sharing one floating diffusion part by two pixels (light-receiving part).

Hereinafter, an example of a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus according to an embodiment of the present invention will be described with reference to FIGS. Embodiments of the present invention will be described in the following order. In addition, this invention is not limited to the following examples.
1. First embodiment: Solid-state imaging device
1-1 Overall Configuration of Solid-State Imaging Device 1-2 Configuration of Main Part 1-3 Manufacturing Method Second Embodiment: Manufacturing Method of Solid-State Imaging Device 3. Third Embodiment: Electronic Device

<1. First Embodiment: Solid-State Imaging Device>
[1-1 Overall Configuration of Solid-State Imaging Device]
FIG. 1 is a schematic configuration diagram showing the entire solid-state imaging device according to the first embodiment of the present invention.
A solid-state imaging device 1 according to the present embodiment includes a pixel unit 3 including a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical drive circuit 4, a column signal processing circuit 5, and a horizontal drive circuit. 6, an output circuit 7, a control circuit 8, and the like.

  The pixels 2 are composed of a light receiving portion made of a photodiode and a plurality of pixel transistors, and a plurality of pixels 2 are regularly arranged in a two-dimensional array on the substrate 11. The pixel transistor constituting the pixel 2 may be four MOS transistors constituted by a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or may be three transistors excluding the selection transistor.

  The pixel unit 3 is composed of pixels 2 regularly arranged in a two-dimensional array. The pixel unit 3 amplifies a signal charge actually received by light and amplifies a signal charge generated by photoelectric conversion and reads it to the column signal processing circuit 5 and a black for outputting an optical black serving as a black level reference. And a reference pixel region (not shown). The black reference pixel region is normally formed on the outer periphery of the effective pixel region.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. The clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows. Then, the pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.

[1-2 Configuration of main parts]
Next, a schematic configuration of a main part of the solid-state imaging device 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional configuration diagram of a predetermined region including the light receiving portion PD. In FIG. 2, a light receiving unit PD, a transfer transistor Tra, a pixel transistor other than the transfer transistor Tra formed in the pixel unit 3 and a transistor formed in the peripheral logic circuit (hereinafter, non-transfer transistor Trb) are illustrated. Yes.
In the solid-state imaging device 1 according to the present embodiment, an example is shown in which electrons are used as signal charges, and each transistor is an example of an n-channel MOS transistor. In this embodiment, the first conductivity type in the present invention is assumed to be p-type, and the second conductivity type is assumed to be n-type.

  The light receiving portion PD includes a charge storage region 24 formed of an n-type impurity region formed on the surface side of the p-type semiconductor substrate 12 and a p-type high-concentration impurity formed on the outermost surface of the semiconductor substrate 12 on the charge storage region 24. It is comprised from the dark current suppression area | region 25 which consists of an area | region. In the light receiving part PD, a main photodiode is constituted by a pn junction between the dark current suppression region 25 and the charge storage region 24, and signal charges generated according to the amount of light incident on the light receiving part PD are stored in the charge. Accumulated in area 24. Further, in the dark current suppression region 25, generation of dark current is suppressed by recombining electrons that cause dark current generated on the surface of the semiconductor substrate 12 by holes that are majority carriers.

  In a desired region on the surface side of the semiconductor substrate 12, source / drain regions 17 constituting each transistor are formed of n-type high concentration impurity regions.

  The transfer transistor Tra includes a transfer gate electrode 18 formed on the semiconductor substrate 12 in a region adjacent to the light receiving portion PD via a gate insulating film 13. The side surface of the transfer gate electrode 18 facing the light receiving portion PD is formed in a shape (tapered shape) that extends obliquely from the top to the bottom of the transfer gate electrode 18. Further, the side surface of the transfer gate electrode 18 facing the source / drain region 17 (in this case, the floating diffusion portion) opposite to the light receiving portion PD is substantially perpendicular to the horizontal plane of the semiconductor substrate 12. Is formed. The semiconductor region corresponding to the lower portion of the transfer gate electrode 18 of the semiconductor substrate 12 is used as the transfer gate of the transfer transistor Tra. In such a transfer transistor Tra, by supplying a desired voltage to the transfer gate electrode 18, the signal charge generated and accumulated in the light receiving portion PD becomes a source / drain region 17 that becomes a floating diffusion portion via the transfer gate. Forwarded to

  A non-transfer gate electrode 16 constituting a non-transfer transistor Trb is formed on the semiconductor substrate 12 between adjacent desired source / drain regions 17 with a gate insulating film 13 interposed therebetween. The side surfaces of the non-transfer gate electrodes 16 constituting these non-transfer transistors Trb facing the source / drain regions 17 are substantially perpendicular to the horizontal plane of the semiconductor substrate 12. The semiconductor region corresponding to the lower portion of the non-transfer gate electrode 16 of the semiconductor substrate 12 is used as the gate of the non-transfer transistor Trb.

  Sidewalls SW made of an insulating film are formed on the side surfaces of the transfer gate electrode 18 and the non-transfer gate electrode 16, respectively. The sidewall SW in this embodiment is formed of the silicon nitride film 14 and the silicon oxide film 15. It is composed of two insulating films.

[1-3 Manufacturing method]
3 to 5 are manufacturing process diagrams of the solid-state imaging device 1 of the present embodiment. A method for manufacturing the solid-state imaging device 1 according to this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3A, a gate insulating film 13 made of, for example, a silicon oxide film is formed on the p-type semiconductor substrate 12, and a desired gate electrode made of, for example, polysilicon is formed on the gate insulating film 13. FIG. 3A illustrates the transfer gate electrode 18 constituting the transfer transistor Tra and the non-transfer gate electrode 16 of the non-transfer transistor Trb. The transfer gate electrode 18 and the non-transfer gate electrode 16 are formed, for example, by patterning an electrode layer made of polysilicon into a desired shape by dry etching. Then, the side surfaces of the transfer gate electrode 18 and the non-transfer gate electrode 16 are etched so as to have a substantially vertical shape (87 ° or more and 90 ° or less) with respect to the horizontal plane of the semiconductor substrate 12.
In the present embodiment, the transfer gate electrode 18 and the non-transfer gate electrode 16 are formed of polysilicon, but other examples may be formed of PDAS (phosphorus doped amorphous silicon).

  Next, as shown in FIG. 3B, a resist mask 19 having an opening on the side facing the region where the light receiving portion PD is formed is formed. At this time, the shoulder portion of the transfer gate electrode 18 facing the light receiving portion PD is exposed in a desired range, and the non-transfer gate electrode 16 is entirely covered with the resist mask 19.

In this state, the shoulder exposed from the resist mask 19 is etched to obtain the transfer gate electrode 18 whose forward taper is applied to the side surface facing the light receiving portion PD as shown in FIG. 3C. In this case, for example, in dry etching by RIE (Reactive Ion Etching) method, etching is performed under high pressure using HBr / O ₂ gas. As a result, the transfer gate electrode 18 is etched at a high selectivity with respect to the silicon oxide film constituting the gate insulating film 13, and the transfer gate electrode 18 having a desired tapered shape on the side surface can be obtained. The angle of the taper shape can be changed by changing the etching conditions.
In addition to RIE, ICP (Inductive Coupled Plasma) -RIE, CCP (Capacitive Coupled Plasma) -RIE, and ECR (Electron Cyclotron Resonance) -RIE can be used.

  The taper-shaped angle formed in FIG. 3C is formed at an angle smaller than 90 ° with respect to the horizontal plane of the semiconductor substrate 12, and the preferred angle is formed by the height of the transfer gate electrode 18 or in a later step. Varies depending on the thickness of the sidewall. In this embodiment, for example, the etching conditions are selected so that the taper shape is 70 ° with respect to the horizontal plane of the semiconductor substrate 12. In this manner, the side surface of the transfer gate electrode 18 facing the light receiving portion PD is tapered so as to spread from the upper part of the transfer gate electrode 18 to the skirt.

  Next, as shown in FIG. 4D, a charge storage region 24 composed of an n-type impurity region is formed in the region where the light receiving portion PD is formed. Thereafter, a silicon nitride film 14 and a silicon oxide film 15 which are insulating films are sequentially formed on the gate insulating film 13 including the transfer gate electrode 18 and the non-transfer gate electrode 16. The charge accumulation region 24 is formed by ion implantation of n-type impurities using a resist mask having an opening only in the region where the light receiving portion PD is formed after the transfer gate electrode 18 and the non-transfer gate electrode 16 are formed. . At this time, self-aligned ion implantation using the transfer gate electrode 18 as a mask is performed in a region beside the transfer gate electrode 18. The silicon nitride film 14a and the silicon oxide film 15a are formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Next, by etching back the entire surface, as shown in FIG. 4E, the side surfaces of the transfer gate electrode 18 and the non-transfer gate electrode 16 are made of the silicon nitride film 14 and the silicon oxide film 15 (two-layer insulating film). Sidewall SW is formed. At this time, since the side surface of the transfer gate electrode 18 facing the light receiving portion PD is tapered, the vertical thickness of the two-layer insulating film formed on the tapered side surface is vertical. It is thinner than the thickness in the vertical direction of the two-layer insulating film formed on the side surface. When the entire surface is etched back, the insulating film is etched by the same thickness on the entire surface. For these reasons, the thickness (width Wa) of the sidewall SW formed on the side surface of the transfer gate electrode 18 having a tapered shape is formed on the side surface of the transfer gate electrode 18 or the non-transfer gate electrode 16 having a vertical shape. It becomes smaller than the thickness (width Wb) of the sidewall SW.

  Next, as shown in FIG. 4F, a resist mask 20 having an opening is formed only in the region where the light-receiving portion PD is formed, and p-type impurities are ionized at a high concentration on the surface of the semiconductor substrate 12 above the charge storage region 24. The dark current suppression region 25 is formed by implantation. The implantation angle of this ion implantation is about 90 ° with respect to the horizontal plane of the semiconductor substrate 23 as shown by an arrow Ia in FIG. 4F. In this embodiment, the dark current suppression region 25 is formed in the light receiving portion PD region beside the transfer gate electrode 18 by ion implantation through the sidewall SW by self-alignment. For this reason, the distance between the transfer gate end and the dark current suppression region 25 is the thickness (width Wa) of the sidewall SW formed on the side surface of the tapered transfer gate electrode 18.

  Thereafter, as shown in FIG. 5G, a resist mask 21 is formed so as to cover the region where the light receiving portion PD is formed, and n-type is formed on the desired semiconductor substrate 12 region beside the transfer gate electrode 18 or the non-transfer gate electrode 16. Ions are implanted at a high concentration. Thereby, a desired source / drain region 17 is formed. Also in this case, the ion implantation is performed by self-alignment through the sidewall SW, and the implantation angle is about 90 ° as shown by the arrow Ib in FIG. 5G.

  In the present embodiment, the light receiving portion PD, the transfer transistor Tra, the non-transfer transistor Trb, and the like are formed as described above.

  In the present embodiment, the side surface of the transfer gate electrode 18 facing the light receiving portion PD is tapered so that the thickness (width Wa) of the sidewall SW formed on the side surface can be adjusted. This makes it possible to adjust the distance between the dark current suppression region 25 and the end portion of the transfer gate electrode with the thickness (width Wa) of the side wall, so that the dark current suppression region 25 is self-aligned by vertical ion implantation. Can be formed. Therefore, there is no need for oblique ion implantation or the like, and the formation region of the dark current suppression region 25 can be accurately adjusted by adjusting the thickness (width Wa) of the sidewall. In addition, the distance between the transfer gate end and the dark current suppression region 25 formed on the surface of the light receiving portion PD is appropriately shortened without affecting the formation of the source / drain regions 17 of other pixel transistors and peripheral logic circuit transistors. Can do. As a result, defects such as white spots can be suppressed by suppressing generation of dark current without reducing transfer efficiency.

  In the solid-state imaging device 1 according to the present embodiment, only the side surface of the transfer gate electrode 18 facing the light-receiving portion PD needs to have a tapered shape. The configuration of the apparatus and the manufacturing process can be used. For this reason, it is not necessary to make a big change from the manufacturing process of the conventional solid-state imaging device, and the solid-state imaging device of this embodiment can be realized.

FIG. 6A is a plan layout diagram in the case where one floating diffusion portion FD is shared by two pixels (light receiving portions PD). Between the light receiving part PD and the floating diffusion part FD, a transfer gate electrode 18 constituting the transfer transistor Tra is formed.
6B is a cross-sectional configuration diagram taken along the line AA ′ in FIG. 6A. The solid-state imaging device shown in FIGS. 6A and 6B is formed by the steps of FIGS. 3 to 5 as in the present embodiment.

  When manufacturing the solid-state imaging device as shown in FIG. 6A using the manufacturing method of this embodiment, the side surface of each transfer gate electrode 18 facing the light receiving portion PD is tapered as shown in FIG. 6B. To form. Thereby, the dark current suppression region 25 formed by self-alignment over the sidewall SW by ion implantation with an implantation angle of 90 ° with respect to the horizontal plane of the semiconductor substrate 12 is only the width Wa of the sidewall SW from the end of the transfer gate. It can be formed in a remote area. Since the ion implantation angle can be set to 90 °, the dark current suppression region 25 can be simultaneously formed by the two light receiving portions PD sharing the floating diffusion portion FD. For this reason, the dark current suppression region 25 of all the pixels can be formed by one ion implantation.

  As described above, when the present embodiment is applied to the solid-state imaging device sharing one floating diffusion portion FD with two pixels, the conventional manufacturing shown in FIG. There is no need for oblique ion implantation with different implantation angles as in the method. For this reason, the number of processes can be reduced. Thereby, TAT deterioration accompanying an increase in the number of steps can be suppressed and the foreign matter adhesion rate can be reduced, so that the yield can be improved.

  Further, even when the number of pixels (light receiving parts PD) sharing one floating diffusion part FD is increased from two, the dark current suppression region can be obtained by one ion implantation by using the manufacturing method of the present embodiment. 25 can be formed.

  7 to 9 show Comparative Examples 1 to 3 in which the shape of the side surface of the transfer gate electrode 18 facing the light receiving portion PD is changed to a shape other than the present embodiment.

First, Comparative Example 1 will be described with reference to FIGS. 7A and 7B.
7A and 7B show a case where the taper-shaped angle of the side surface of the transfer gate electrode 18 facing the light receiving portion PD is set smaller than the specified range of the present embodiment with respect to the horizontal plane of the semiconductor substrate 12. FIG. That is, the taper shape is an example that is made gentler than the taper shape of the present embodiment.

  When the taper shape is formed gently (for example, 45 ° taper angle) as shown in FIG. 7A, the silicon nitride film 14 and the silicon oxide film 15 formed on the transfer gate electrode 18 are formed by the same method as in this embodiment. Etch back. Then, since the distance from the surface of the silicon oxide film 15 to the transfer gate electrode 18 is small on the side surface of the transfer gate electrode 18 having a tapered shape, the silicon oxide film 15 formed on the tapered side surface is necessary. Etching is removed as described above. As a result, no side wall is formed on the side surface of the transfer gate electrode 18 formed in a tapered shape, and the distance between the transfer gate electrode 18 and the dark current suppression region 25 cannot be controlled by the thickness of the side wall. .

Next, Comparative Example 2 will be described with reference to FIGS. 8A and 8B.
8A and 8B, the side surface of the transfer gate electrode 18 facing the light receiving portion PD has a tapered shape in which the upper portion of the transfer gate electrode 18 extends to the skirt, and the side surface has a concave round shape. It is a manufacturing-process figure in the case of being formed in.

  When the side surface of the transfer gate electrode 18 has a round shape as shown in FIG. 8A, the silicon nitride film 14 and the silicon oxide film 15 formed on the transfer gate electrode 18 are etched back by the same method as in this embodiment. . 8B, only the silicon oxide film 15 formed on the side surface of the round transfer gate electrode 18 remains on the side surface of the round transfer gate electrode 18 as shown in FIG. The side silicon oxide film 15 is removed by etching. Therefore, in the example of FIG. 8 as well, a side wall is not formed at the bottom of the side surface of the transfer gate electrode 18 formed in a round shape, and the distance between the transfer gate electrode 18 and the dark current suppression region 25 is determined as the thickness of the side wall. Can not be controlled by.

Next, Comparative Example 3 will be described with reference to FIGS. 9A and 9B.
FIGS. 9A and 9B are manufacturing process diagrams in the case where the side surface of the transfer gate electrode 18 facing the light receiving portion PD is formed in an inversely tapered shape so as to enter the inside from the top to the bottom of the transfer gate electrode 18. It is.

  When the side surface of the transfer gate electrode 18 has a reverse taper diameter as shown in FIG. 9A, a silicon nitride film 14 and a silicon oxide film 15 are formed on the transfer gate electrode 18, and the same method as in this embodiment is used. Etch back. In this case, the silicon nitride film 14 and the silicon oxide film 15 are formed so as to be buried between the side surface having an inversely tapered shape and the semiconductor substrate 12. When the silicon nitride film 14 and the silicon oxide film 15 are etched back, the insulating film made of the silicon nitride film 14 and the silicon oxide film 15 that has entered between the side surface having the inversely tapered shape and the semiconductor substrate 12 is: As shown in FIG. 9B, it remains unetched. Then, the distance between the side surface of the transfer gate electrode 18 formed in the reverse taper shape and the side wall end portion formed on the side surface is formed on the side surface of the transfer gate electrode 18 formed vertically and the side surface thereof. It becomes larger than the distance from the side wall end. In this case, the distance between the side surface facing the light receiving part PD and the dark current suppression region 25 is increased.

  From the above Comparative Examples 1 to 3, in the solid-state imaging device 1 of the present embodiment, the transfer gate electrode 18 is formed by forming the tapered shape of the side surface facing the light receiving part PD of the transfer gate electrode 18 at a suitable angle. It turns out that the distance of 18 edge part and the dark current suppression area | region 25 can be adjusted suitably.

<2. Second Embodiment: Method for Manufacturing Solid-State Imaging Device>
Next, a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention will be described. In this embodiment, the manufacturing method is different from the manufacturing method of the solid-state imaging device according to the first embodiment. The overall configuration of the solid-state imaging device according to this embodiment is the same as that shown in FIG. 1, and the cross-sectional configuration of the main part of the solid-state imaging device manufactured according to this embodiment is the same as that shown in FIG. Omitted.

10 to 12 are manufacturing process diagrams of the solid-state imaging device according to this embodiment.
In this embodiment, first, as shown in FIG. 10A, an electrode layer 18b made of, for example, polysilicon is formed on a p-type semiconductor substrate 12 via a gate insulating film 13, and a resist mask is formed on the electrode layer 18b. 22 is formed and the electrode layer 18a is etched. Thereby, the non-transfer gate electrode 16 is formed.

  Next, as shown in FIG. 10B, a resist mask 28 having an opening in a region where the light receiving portion PD is formed is formed from the position of the transfer gate electrode 18 on the side facing the light receiving portion PD.

Next, for example, using an ECR plasma etching apparatus, the electrode layer 18b exposed from the opening of the resist mask 28 is removed by etching using a mixed gas of hydrogen bromide, chlorine, and oxygen as an etching gas. Under this etching condition, the electrode layer 18b can be etched with a high selectivity with respect to the silicon oxide film constituting the gate insulating film 13. Therefore, a transfer gate electrode 18 having a desired taper shape can be obtained as shown in FIG. 10C. The taper-shaped angle is formed at an angle smaller than 90 ° with respect to the horizontal plane of the semiconductor substrate 12, and the preferred angle is the height of the transfer gate electrode 18 and the thickness of the sidewall formed in a later step. It depends on. In this embodiment, for example, the etching conditions are selected so that the taper shape is 70 ° with respect to the horizontal plane of the semiconductor substrate 12.
In the present embodiment example, the ECR plasma etching apparatus is used as an example, but other processing conditions similar to those in the first embodiment are possible, and the taper can be obtained by using RIE, ICP-RIE, and CCP-RIE. A transfer gate electrode 18 having a shape can be formed.

Next, although not shown, after forming a resist mask having an opening in the light receiving portion PD, the charge storage region 24 is formed by ion-implanting n-type impurities in the region where the light receiving portion PD is formed. . In this case, in the region beside the transfer gate electrode 18, the charge accumulation region 24 is formed by self-alignment using the end portion of the transfer gate electrode 18 as a mask.
Thereafter, as shown in FIG. 11D, two insulating layers of a silicon nitride film 14 and a silicon oxide film 15 are sequentially formed on the gate insulating film 13 including the transfer gate electrode 18 and the non-transfer gate electrode 16. These silicon nitride film 14 and silicon oxide film 15 can be formed by the CVD method as in the first embodiment.

  Then, the solid-state imaging device shown in FIG. 2 can be obtained through the manufacturing steps of FIGS. 4E to 5G in the first embodiment.

  Also in the manufacturing method of the solid-state imaging device of the present embodiment example, a solid-state imaging device having the same configuration as the solid-state imaging device of the first embodiment can be obtained, and the solid-state imaging device obtained in the first embodiment can be obtained. Effects similar to those of the manufacturing method can be obtained.

  In the first and second embodiments described above, the configuration using mainly n-channel MOS transistors has been described, but a p-channel MOS transistor configuration may also be used. In this case, the conductivity type is reversed in each figure.

  In the first and second embodiments described above, a case where the present invention is applied to a CMOS solid-state imaging device in which unit pixels that detect signal charges corresponding to the amount of incident light as physical quantities are arranged in a matrix is taken as an example. explained. However, the present invention is not limited to application to a CMOS type solid-state imaging device. Further, the present invention is not limited to a column type solid-state imaging device in which column circuits are arranged for each pixel column of a pixel portion in which pixels are formed in a two-dimensional matrix.

  In addition, the present invention is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures an image as an image. The present invention can also be applied to an imaging device. In a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.

Furthermore, the present invention is not limited to the solid-state imaging device that sequentially scans each unit pixel of the pixel unit in units of rows and reads a pixel signal from each unit pixel. The present invention is also applicable to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads out signals from the selected pixels in pixel units.
Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which a pixel portion and a signal processing portion or an optical system are packaged together. Good.

  In addition, the present invention is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device. The electronic device of the present invention will be described below.

<3. Third Embodiment: Electronic Device>
FIG. 12 is a schematic configuration diagram of an electronic device 200 according to the third embodiment of the present invention.
An electronic apparatus 200 according to the present embodiment shows an embodiment when the solid-state imaging device 1 according to the first embodiment of the present invention described above is used in an electronic apparatus (camera).

  The electronic apparatus 200 according to the present embodiment includes the solid-state imaging device 1, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213.

The optical lens 210 collects image light (incident light) from the subject and forms an image on the imaging surface of the solid-state imaging device 1. As a result, the signal charge is accumulated in the solid-state imaging device 1 for a certain period.
The shutter device 211 controls a light irradiation period and a light shielding period for the solid-state imaging device 1.
The drive circuit 212 supplies drive signals that control the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 211. Signal transfer of the solid-state imaging device 1 is performed by a drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the electronic apparatus 200 according to the present embodiment, in the solid-state imaging device 1, the formation region of the dark current suppression region can be accurately controlled, and white by suppressing generation of dark current without reducing transfer efficiency. Since defects such as dots can be suppressed, deterioration of image quality is suppressed.

  Thus, the electronic device 200 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can be applied to an imaging device such as a digital still camera and a camera module for mobile devices such as a mobile phone.

  In the present embodiment example, the solid-state imaging device 1 is configured to be used for an electronic device, but the solid-state imaging device formed according to the second embodiment described above can also be used.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel 3 Pixel part 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Horizontal signal line 11 Substrate 12 Semiconductor substrate 13 Gate insulating film 14 Silicon nitride film 14a Silicon nitride film 15 Silicon oxide film 15a Silicon oxide film 16 Non-transfer gate electrode 17 Source / drain region 18 Transfer gate electrode 18a Electrode layer 18b Electrode layer 19 Resist mask 20 Resist mask 21 Resist mask 22 Resist mask 23 Semiconductor substrate 24 Charge storage region 25 Dark current suppression Area 28 Resist mask PD Light receiving part FD Floating diffusion part

Claims (8)

A dark current suppression region formed of a first conductivity type high-concentration impurity region formed on the outermost surface of the substrate; and a charge storage region formed of a second conductivity type impurity region formed below the dark current suppression region; A light receiving unit configured to generate a signal charge according to the amount of received light;
A transfer gate electrode formed through a gate insulating film in a region adjacent to the light receiving unit on the substrate, wherein a side surface facing the light receiving unit is tapered, and a transfer having a side wall on the side surface A gate electrode;
A solid-state imaging device. The desired region on the substrate has a non-transfer gate electrode formed through a gate insulating film,
Side surfaces other than the tapered side surface of the transfer gate electrode and side surfaces of the non-transfer gate electrode are formed so as to be substantially perpendicular to a horizontal plane of the substrate,
The thickness of the side wall formed on the tapered side surface of the transfer gate electrode is on the side surface of the transfer gate electrode and the non-transfer gate electrode formed so as to be substantially perpendicular to the horizontal plane of the substrate. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed smaller than a thickness of the formed sidewall. The solid-state imaging device according to claim 2, wherein the dark current suppression region is formed in a region separated from an end portion of the transfer gate electrode by a thickness of a side wall formed on the tapered side surface. Forming a gate insulating film on the substrate and forming an electrode layer thereon;
Etching the electrode layer to form a transfer gate electrode having a tapered side surface facing a region where the light receiving portion of the substrate is formed, and a non-transfer gate electrode having a vertical side surface ,
Forming sidewalls on side surfaces of the transfer gate electrode and the non-transfer gate electrode;
By ion-implanting a desired impurity through a sidewall formed on the tapered side surface of the transfer gate electrode, a dark current suppression region is self-aligned on the outermost surface of the region where the light receiving portion of the substrate is formed. Forming step,
A method for manufacturing a solid-state imaging device including: The method for manufacturing a solid-state imaging device according to claim 4, wherein ion implantation used in the step of forming the dark current suppression region is performed at an implantation angle perpendicular to a horizontal plane of the substrate. The step of forming the transfer gate electrode and the non-transfer gate electrode includes:
Etching the electrode layer to form a transfer gate electrode and a non-transfer gate electrode whose side surfaces are vertically processed, and etching the side surface of the transfer gate electrode facing the region where the light-receiving portion is formed. The method for manufacturing a solid-state imaging device according to claim 5, comprising a processing step. Forming the transfer gate electrode and the non-transfer gate electrode,
Etching the electrode layer and etching the electrode layer before or after the step of forming the non-transfer gate electrode whose side surfaces are vertically processed, the step of forming the non-transfer gate electrode, and the light receiving portion of the substrate The solid-state imaging device according to claim 5, further comprising a step of forming a transfer gate electrode having a tapered side surface facing a region where the film is formed. An optical lens,
A solid-state imaging device to which light condensed by the optical lens is irradiated, comprising: a dark current suppression region formed of a high-concentration impurity region of a first conductivity type formed on an outermost surface of a substrate; and the dark current suppression region A light-receiving portion that forms a signal charge corresponding to the amount of light received, and a gate in a region adjacent to the light-receiving portion above the semiconductor substrate. A solid-state imaging device having a transfer gate electrode formed through an insulating film, the side surface facing the light-receiving portion being tapered and a transfer gate electrode having a side wall on the side surface;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
Including electronic equipment.

Images