JP2011041349A - Controller of load circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller of a load circuit facilitating adjustment of a clamp voltage. <P>SOLUTION: The controller of the load circuit is provided with a drive circuit 13 having a superimposed power supply VP connected in series to a DC power supply VB, supplying a current to a gate of a MOSFET (M1) used as an electronic switch from the superimposed power supply VP to raise a gate voltage and turn on the MOSFET (M1), and a clamping circuit 14 which is changed in conjunction with a source voltage VS of the MOSFET (M1), generates a fluctuation voltage V2 which is set to be higher than the source voltage VS by a prescribed voltage, and extracts a part of the current output from the superimposed power supply VP and clamps a gate voltage VG to the prescribed voltage when the gate voltage VG of the MOSFET (M1) exceeds the fluctuation voltage (V2). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a control device that controls driving of a load circuit, and more particularly to a technique for protecting the entire load circuit when an overcurrent occurs.

  For example, a load circuit for driving loads such as various lamps and motors mounted on a vehicle includes a MOSFET (field effect transistor) provided between a battery (DC power supply) mounted on the vehicle and the load. Thus, the driving and stopping of the load are controlled by switching the MOSFET on and off.

  In such a load circuit, overcurrent may flow due to circuit failure, malfunction, short circuit accident, etc., and in order to protect the load circuit from overcurrent, an overcurrent protection circuit is provided. For example, what was described in Unexamined-Japanese-Patent No. 2005-323489 (patent document 1) is known.

  In Patent Document 1, a Zener diode is provided between the gate and source of a MOSFET, and when the source voltage drops due to the occurrence of an overcurrent and falls below a predetermined value, the Zener diode is used to form a gate / source. It is described that the current flowing through the MOSFET is limited by clamping the voltage between them to a constant voltage, thereby avoiding heat generation due to overcurrent.

JP 2005-323489 A

  However, the conventional example disclosed in Patent Document 1 described above uses a Zener diode to clamp the gate-source voltage of the MOSFET, and the generally available Zener diode is set to a desired clamp voltage. Difficult to do. That is, the Zener voltage of the Zener diode becomes a predetermined value and cannot be finely adjusted to a desired voltage value. Therefore, there has been an increasing demand for finely adjusting the clamp voltage.

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a load circuit control device capable of easily adjusting a clamp voltage. .

  In order to achieve the above object, an invention according to claim 1 of the present application is a load circuit that controls on / off of a load by switching on and off of a field effect transistor provided between a DC power supply and a load. The control device includes a superimposed power source connected in series to the DC power source, and when a drive signal is supplied, current is supplied from the superimposed power source to the gate of the field effect transistor to increase the gate voltage. Driving means for turning on the field effect transistor, and a variable voltage (V2) set so as to change in conjunction with the source voltage of the field effect transistor and to be higher than the source voltage by a predetermined voltage. When the gate voltage exceeds the fluctuation voltage (V2), a part of the current output from the superimposed power supply is extracted, and the gate voltage is set to a predetermined voltage. Characterized in that and a clamping means for amplifier.

  The invention according to claim 2 generates a reference voltage (V1, V5) set lower than the source voltage when the normal load current is flowing, and when the source voltage exceeds the reference voltage, A clamp operation control means for disabling the clamp function by the clamp means is further provided.

  According to a third aspect of the present invention, the clamp operation control means includes a series connection circuit of a first resistor (R3) and a third current source (CC3) interposed between the DC power supply and the ground. The voltage dropped from the DC power source by the voltage indicated by (CC3 * R3) is used as the reference voltage (V1).

  According to a fourth aspect of the present invention, the clamp operation control means includes a series connection circuit of a second resistor (R3) and a third resistor (R8) interposed between the DC power supply and the ground. A voltage obtained by dividing the voltage output from the DC power source by the first resistor and the second resistor is used as the reference voltage (V5).

  According to a fifth aspect of the present invention, the drive means includes a first current source (CC1) that supplies a constant current when the drive signal is supplied, and two current paths. A current mirror circuit connected to the first current source and having the other current path connected to the gate of the field effect transistor, and when the drive signal is supplied, the first current (CC1) The same current is supplied from the superimposed power source to the gate of the field effect transistor.

  According to a sixth aspect of the present invention, the clamp means includes a second current source (CC2) interposed between either the superimposed power source or the DC power source and the source of the field effect transistor, And a fourth resistor (R2), and a constant current is caused to flow through the fourth resistor (R2) by the second current source, whereby a predetermined voltage becomes higher than the source voltage at one end of the first resistor. And amplifying means (AMP1) for generating a variable voltage (V2) that changes in such a manner and outputting a signal corresponding to the difference between the variable voltage and the gate voltage, and an energization current according to the output signal of the amplifying means And a first switch (M6) for extracting a predetermined amount of current from the current supplied to the gate.

  The invention according to claim 7 further comprises overheat protection means for protecting the load circuit from overheating by shutting off the field effect transistor when the ambient temperature of the field effect transistor reaches a predetermined temperature set in advance. It is characterized by having.

  According to an eighth aspect of the present invention, the overheat protection means includes a diode installed around the field effect transistor, a fourth current source (CC4) for supplying a constant current to the diode, and a voltage generated in the diode. A first comparison means (CMP2) for comparing the voltage (V4), a latch circuit for outputting a latch signal when the voltage generated in the diode falls below the reference voltage V4, and when the latch signal is output, And a second switch (M8) for connecting the output point of the drive signal to the ground.

  The invention according to claim 9 further includes a back electromotive force detection means for detecting a back electromotive force from the field effect transistor toward the DC power source when the field effect transistor is turned on. When the occurrence of back electromotive force is detected, the clamping function by the clamping means is validated regardless of the output signal of the clamping operation control means.

  According to a tenth aspect of the present invention, the back electromotive force detection means sets a predetermined time constant when the connection point between the drain of the field effect transistor and the DC power supply is a point p1, and is normally a point. a time constant circuit for outputting a voltage set slightly lower than the voltage of p1, and a second comparison means (CMP3) for comparing the voltage of the point p1 with the output voltage of the time constant circuit. It is determined that the back electromotive force is generated when the voltage of the voltage falls below the output voltage of the time constant circuit.

  In the first aspect of the present invention, the fluctuation voltage (V2) set to be higher than the source voltage (VS) of the field effect transistor by a predetermined voltage is generated, and the gate voltage (VG) of the field effect transistor is changed to the fluctuation voltage (V2). ), The gate voltage (VG) is clamped to a predetermined voltage. Therefore, the current flowing through the field effect transistor can be suppressed. That is, when an overcurrent flows in the load circuit and the drain-source voltage of the field effect transistor increases and the source voltage (VS) decreases relatively, the fluctuation voltage (V2) decreases accordingly. > V2, and the gate voltage (VG) is clamped to a predetermined voltage. Therefore, even when a short circuit abnormality occurs in the load and an overcurrent flows, the current value can be suppressed and the load circuit can be protected from overheating.

  In addition, the clamp means clamps the gate voltage (VG) by extracting a part of the current supplied to the gate of the field effect transistor, so that the clamp voltage can be easily set by appropriately setting the current value to be extracted. Can be set to a value. For this reason, it is possible to set a fine clamping voltage as compared with the conventional case of clamping using a Zener diode.

  According to a second aspect of the present invention, there is provided clamping operation control means for controlling whether or not the clamping means is operated effectively, and the clamping means when the source voltage (VS) of the field effect transistor exceeds the reference voltage (V1). The clamp operation by is invalidated. In other words, the clamping means is effective only when the source voltage (VS) is lower than the reference voltage (V1), so that it is possible to prevent the clamping means from operating when the overcurrent is not generated.

  In the invention of claim 3, since the reference voltage (V1) is generated by flowing the current of the third current source (CC3) through the first resistor (R3), the current value of the third current source is set to By appropriately adjusting, the reference voltage (V1) can be easily set to a desired value.

  In the invention of claim 4, the voltage output from the DC power source is divided by the second resistor (R3) and the third resistor (R8) to generate the reference voltage (V5), so the output voltage of the DC power source fluctuates. In this case, the magnitude of the reference voltage (V5) can be changed corresponding to this variation, and an appropriate reference voltage (V5) corresponding to the output voltage of the DC power supply can be generated. This is extremely effective when the output voltage fluctuates momentarily, for example, as in a battery mounted on a vehicle.

  In the invention of claim 5, since the current supplied to the gate of the field effect transistor is generated using the first current source (CC1) and the current mirror circuit, the accuracy of the current value can be improved, and the clamp voltage Can be set with high accuracy.

  According to the sixth aspect of the present invention, by causing the current of the second current source (CC2) to flow through the fourth resistor (R2), the fluctuation voltage (V2) higher than the source voltage (VS) of the field effect transistor is generated. Therefore, the variable voltage (V2) can be set to a desired value with high accuracy. Further, when the clamping means is activated, the amplification means (AMP1) is used to output a signal corresponding to the difference between the gate voltage (VG) and the fluctuation voltage (V2), and further the first switch (M6) is turned on. Since the current supplied to the gate of the field effect transistor is extracted, the current value to be extracted can be set with high accuracy, and the accuracy of the clamp voltage can be improved.

  In the invention of claim 7, overheat protection means is provided, and when the ambient temperature of the field effect transistor reaches a predetermined temperature detected by the overheat protection means, the field effect transistor is shut off. Can be protected from overheating. For example, when a short circuit abnormality occurs in the load and the state where the load current is limited by the clamping means is continued for a long time, the ambient temperature of the field effect transistor rises due to the generation of Joule heat. In such a case, the drive of the load is stopped by turning off the field effect transistor, so that the entire circuit can be reliably protected from overheating.

  In the invention of claim 8, when a diode is installed around the field effect transistor and the ambient temperature rises, the rise in ambient temperature is detected by utilizing the decrease in the resistance value of the diode. That is, when the current output from the fourth current source (CC4) is passed through a diode and the voltage generated in the diode falls below a preset reference voltage, the ambient temperature of the field effect transistor has reached a predetermined temperature. Detect. In this case, by appropriately changing the current value of the fourth current source (CC4), the predetermined temperature for determining overheating can be finely set, and high-temperature overheating can be cut off.

  Further, when the ambient temperature reaches a predetermined temperature, a latch signal is output from the latch circuit, and the field effect transistor is turned off by the latch signal, so that driving of the load circuit is stopped until the latch circuit is reset. Therefore, it is possible to prevent troubles caused by inadvertent driving.

  According to the ninth aspect of the present invention, when the back electromotive force directed from the drain of the field effect transistor to the DC power source reaches a certain level, it is determined that the back electromotive force is generated by the back electromotive force detecting means. Then, the clamp circuit is effectively operated. Therefore, when a dead short of the load circuit occurs, the gate voltage of the field effect transistor is clamped and the load current is limited regardless of the output of the clamp operation control means. As a result, even when a dead short occurs, the load circuit can be reliably protected from overheating.

  In the invention of claim 10, the occurrence of the counter electromotive force is detected by using the time constant circuit and the second comparison means (CMP3). That is, when the voltage at the point p1 rapidly decreases due to the occurrence of the back electromotive force, the voltage at the point p1 changes at a fast following speed, and the output voltage of the time constant circuit changes at a slow following speed. The output signal of the comparison means (CMP3) is inverted. Since this inversion is detected and the occurrence of a dead short is detected, the occurrence of a dead short can be detected with high accuracy.

It is a circuit diagram which shows the structure of the load circuit which concerns on 1st Embodiment of this invention, and a control apparatus. It is a timing chart which shows change of each signal used with a control device of a load circuit concerning a 1st embodiment of the present invention. It is explanatory drawing which shows the operating point of MOSFET (M1) of the control apparatus of the load circuit which concerns on 1st Embodiment of this invention, and has shown the change from the normal time to when a short abnormality generate | occur | produces. It is explanatory drawing which shows the operating point of MOSFET (M1) of the control apparatus of the load circuit which concerns on 1st Embodiment of this invention, and has shown the case where the short abnormality has occurred initially. It is a circuit diagram which shows the structure of the load circuit which concerns on 2nd Embodiment of this invention, and a control apparatus. It is a circuit diagram which shows the structure of the load circuit which concerns on 3rd Embodiment of this invention, and a control apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of a load circuit according to a first embodiment of the present invention and a control device connected to the load circuit.

  As shown in FIG. 1, an N-type MOSFET (field effect transistor) M1 used as an electronic switch is provided between the DC power supply VB and the load 11, and the MOSFET (M1) is switched on and off. Thus, for example, the driving and stopping of the load 11 such as a lamp and a motor are controlled.

  In addition, a control device 12 for driving and controlling the MOSFET (M1) is provided, the MOSFET (M1) is switched on and off by the control device 12, and the current IL flowing through the load circuit becomes an overcurrent. In some cases, the MOSFET (M1) is immediately shut off to protect the load circuit.

  In the following description, the symbol VB is used both when indicating the DC power supply itself and when indicating its output voltage. Similarly, VP and V4, which will be described later, are used both when indicating the power supply itself and when indicating its output voltage. In addition, current sources CC1 to CC4, which will be described later, are used both when indicating the current source itself and when indicating the current value.

  The control device 12 shown in FIG. 1 includes a drive circuit (drive means) 13 for switching on and off the MOSFET (M1), a clamp circuit (clamp means) 14 for clamping a gate-source voltage of the MOSFET (M1), When the temperature of the clamp operation control circuit 15 (including the transistor M7 indicated by reference numeral 15 '; the clamp operation control means) for switching whether or not to effectively operate the clamp circuit 14 and the MOSFET (M1) reaches a predetermined value And an overheat protection circuit (overheat protection means) 16 that shuts off the MOSFET (M1) and protects the MOSFET (M1) from overheating.

  The drive circuit 13 includes, for example, transistors M2 (N-type), M3 (P-type), M4 (P-type), M5 (N-type) such as a MOSFET, a superimposed power source VP, a current source CC1 (first current source), , A resistor R1, and an inverter INV.

  The negative pole of the superimposed power supply VP is connected to the point p1 which is the output terminal of the DC power supply VB, the point p2 which is the positive pole of the superimposed power supply VP is branched into three systems, and the first branch line is the transistor M3. The second branch line is connected to one end of the transistor M4, and the third branch line is connected to a later-described current source CC2 (second current source).

  The other end of the transistor M3 is connected to the ground via the resistor R1 and the transistor M2, and is connected to the gate of the MOSFET (M1). The other end of the transistor M4 is connected to the ground via the current source CC1 and the transistor M5. The gates of the transistors M3 and M4 are connected to each other, and this connection point is connected to the other end of the transistor M4. Therefore, the transistors M3 and M4 constitute a current mirror.

  The gate of the transistor M5 is connected to the input end of the drive signal via the resistor R5. Further, the gate of the transistor M2 is connected to the input terminal of the drive signal via the inverter INV and the resistor R5. Accordingly, when the drive signal becomes H level, the transistor M5 is turned on and M2 is turned off. When the drive signal becomes L level, the transistor M5 is turned off and M2 is turned on.

  The clamp circuit 14 includes a current source CC2, a resistor R2, an amplifier AMP1 (amplifying means), and a transistor M6 (N-type; first switch). One end of the current source CC2 is connected to the point p2, and the other end (point p4) is connected to the minus side input terminal (inverting side input terminal) of the amplifier AMP1. Further, this point p4 is connected to the source (point p3) of the MOSFET (M1) via the resistor R2.

  The positive side input terminal (non-inversion side input terminal) of the amplifier AMP1 is connected to the gate of the MOSFET (M1), and the output terminal is connected to the gate of the transistor M6 and one end of a transistor M7 (N-type) described later. . One end of the transistor M6 is connected to the gate of the MOSFET (M1), and the other end is connected to the ground.

  Therefore, as described later, when the voltage V2 (fluctuation voltage) at the point p4 falls below the gate voltage VG of the MOSFET (M1), the clamp circuit 14 turns on the transistor M6 and flows into the gate of the MOSFET (M1). It has a function of drawing the current and clamping the gate voltage VG to the voltage V2.

  The clamp operation control circuits 15 and 15 ′ include a series connection circuit of a resistor R3 (first resistor) and a current source CC3 (third current source) connected to the DC power supply VB, a comparator CMP1, a resistor R4, and a transistor. M7 (N type) is provided.

  The negative input terminal of the comparator CMP1 is connected to a connection point (voltage V1) between the resistor R3 and the current source CC3, and a positive input terminal is connected to the source (point p3) of the MOSFET (M1) via the resistor R4. It is connected. The voltage V1 (reference voltage) is a constant voltage lower than the DC power supply VB by a voltage indicated by “R3 * CC1”.

  When the voltage at the point p3 (source voltage VS) exceeds the voltage V1, the output signal DST of the comparator CMP1 becomes H level, and when the voltage VS falls below the voltage V1, the output signal DST becomes L Become a level. When the output signal DST is at H level, the transistor M7 is turned on, and the output of the amplifier AMP1 and the gate of the transistor M6 are connected to the ground. On the other hand, when the output signal DST is at L level, the transistor M7 is turned off, and the output signal of the amplifier AMP1 is supplied to the gate of the transistor M6. That is, when the output signal DST is at L level, the clamp circuit 14 is validated, and when the output signal DST is at H level, the clamp circuit 14 is invalidated.

  The overheat protection circuit 16 includes a current source CC4 (fourth current source) connected to the DC power supply VB, a reference power supply V4 that outputs a reference voltage, a comparator CMP2, and a D flip-flop (latch circuit) 21. Yes. The output terminal (voltage VF) of the current source CC4 is connected to the negative input terminal of the comparator CMP2, and is connected to the ground via a diode D1 integrated with the MOSFET (M1). The plus side input terminal of the comparator CMP2 is connected to the ground via the reference power source V4.

  The output terminal of the comparator CMP2 is connected to the D flip-flop 21, and the output terminal of the D flip-flop 21 is connected to the gate of the transistor M8 (N type; second switch). One end of the transistor M8 is connected to the resistor R5, and the other end is connected to the ground.

  The overheat protection circuit 16 is normally set so that the voltage VF exceeds the voltage V4 (reference voltage), the ambient temperature of the MOSFET (M1) rises to reach a predetermined upper limit temperature, and the resistance value of the diode D1 is When the voltage drops, the voltage VF is set to be lower than the voltage V4. Therefore, when the ambient temperature of the MOSFET (M1) reaches the upper limit temperature, the voltage VF is lower than the voltage V4, so the output signal THD of the comparator CMP2 changes from L level to H level, and the D flip-flop 21 The output signal is set to H level. Thereby, the transistor M8 is turned on, the drive signal is dropped to the ground, and the MOSFET (M1) can be cut off.

[Description of Operation of First Embodiment]
Next, the operation of the load circuit control device according to the present embodiment will be described with reference to the timing chart shown in FIG.

  First, the normal operation will be described. At time t0 shown in FIG. 2A, since the drive signal is at the L level, the transistor M5 is turned off, M2 is turned on, and the MOSFET (M1) is turned off. That is, no current flows through the load 11 and the load 11 is not driven. At this time, as shown in FIG. 2B, the voltage V2 at the point p4 is about 4V, and the voltage V1 is about 11V.

  After that, when the drive signal is switched to the H level at time t1 shown in FIG. 2A, the transistor M5 is turned on and M2 is turned off. For this reason, the current from the current source CC1 flows through the transistor M4, and the same current CC1 flows through the transistor M3 that forms a current mirror with the transistor M4. This current flows into the gate of the MOSFET (M1), and the gate voltage VG of the MOSFET (M1) gradually increases.

  At this time, since the source voltage VS of the MOSFET (M1) is approximately 0 V, DST, which is an output signal of the comparator CMP1, becomes L level (see FIG. 2C). Therefore, the transistor M7 is off, and the clamping operation by the amplifier AMP1 is valid. However, since VG <V2 at this time, the transistor M6 is turned off, and the clamping operation by the amplifier AMP1 is not performed.

  As time elapses, the voltage VG increases, and when it exceeds the operation threshold voltage Vgsoff of the MOSFET (M1), the source voltage VS starts increasing (time t2). At this time, as shown in FIG. 2D, the load current IL starts to flow. The voltage Vgsoff is about 1 to 2 V, and the voltage VS rises while maintaining the relationship of VS≈VG−Vgsoff. Therefore, the state of VG <V2 is continued, the output of the amplifier AMP1 becomes L level, and the transistor M6 is The off state continues.

  Thereafter, the voltage VG further rises, and accordingly, the voltage VS rises. When the voltage VS becomes V1 <VS at time t3, the output signal DST of the comparator CMP1 is inverted and becomes H level (FIG. 2 ( c)). Thereafter, at time t4, VG = VB + 10, and the MOSFET (M1) is completely turned on. At this time, the current IL flowing through the load 11 becomes a steady current.

  That is, in the normal operation, the steady current flows through the load 11 without the gate of the MOSFET (M1) being clamped by the clamp circuit 14 when the drive signal is on.

  Next, an operation when a short circuit abnormality occurs in the load 11 at time t5 will be described. If a short circuit abnormality occurs at time t5 when a certain time has elapsed after the MOSFET (M1) is turned on, the load current IL increases rapidly as shown in FIG. 2 (d). Along with this, the drain-source voltage Vds of the MOSFET (M1) increases, and the source voltage VS relatively decreases (see FIG. 2B).

  As a result, since VS <V1, the output signal DST of the comparator CMP1 is inverted from H level to L level (see FIG. 2C), and the transistor M7 is turned off. Therefore, the clamp circuit 14 becomes effective. At this time, since the relationship between the voltage VG and the voltage V2 is V2 <VG, a signal having a magnitude proportional to VG-V2 is output from the amplifier AMP1, the transistor M6 is turned on, and flows into the gate of the MOSFET (M1). Pull a portion of the current to ground. As a result, the gate voltage VG is clamped to the voltage V2. In other words, the gate voltage VG is lowered until the gate-source voltage Vgs of the MOSFET (M1) becomes V2 (for example, 4 V).

  Since the voltage Vgs is lowered to 4 V, the MOSFET (M1) operates in the saturation region, and the load current IL is suppressed to a constant value (see FIG. 2C). That is, when a short circuit abnormality occurs in the load 11, the gate-source voltage Vgs is clamped to V2 and the load current IL is suppressed to a constant value. Therefore, as shown in FIG. The overcurrent due to the occurrence of can be suppressed.

  Thereafter, when the short circuit abnormality continues, the ambient temperature of the MOSFET (M1) rises, and the temperature of the diode D1 rises accordingly, so that the resistance value of the diode D1 falls and the voltage VF falls. When the voltage VF falls below the voltage V4, the output signal THD of the comparator CMP2 is inverted from the L level to the H level, and this output signal THD is supplied to the D flip-flop 21. A level signal is output to turn on the transistor M8. As a result, the transistor M5 is turned off and the drive signal is not supplied to the gate of the MOSFET (M1), so that the MOSFET (M1) is turned off. Thereafter, the MOSFET (M1) is kept off until the D flip-flop 21 is reset.

  In the timing chart shown in FIG. 2, as shown in FIG. 2 (e), although the voltage VF decreases as the overcurrent occurs, the overcurrent is avoided without falling below the voltage V4. Yes. Therefore, as shown in FIG. 2F, the output signal THD does not become H level but maintains L level.

  Thereafter, when the short circuit abnormality is avoided at time t6 shown in FIG. 2B and the load current IL returns to the normal current, the voltages VS and VG return to the voltages in the normal state.

  In this way, when a short circuit abnormality occurs in the load 11, a sudden increase in the load current IL can be avoided, and the load circuit can be protected from heat generation due to overcurrent.

  Next, the operating point of the MOSFET (M1) when a short circuit abnormality occurs will be described with reference to the characteristic diagram shown in FIG. 3, S1 is a load line showing the relationship between Vds and Id when the load 11 is normal, S2 is a load line when a short abnormality occurs in the load 11, and S3 is a characteristic line showing Vgs = 10V. , S4 is a characteristic line indicating Vgs = 4V, and S5 is a Vds-Id characteristic curve of the MOSFET (M1).

  During normal operation, the gate-source voltage Vgs of the MOSFET (M1) is Vgs = 10 V, and the load current IL is a normal current. Therefore, the operating point is x1, which is the intersection of S1 and S3. Thereafter, when a short circuit abnormality occurs in the load 11, the load line moves rightward in the figure, and the drain current Id of the MOSFET (M1) increases toward x2 that is the intersection of S2 and S3 (see S5).

  When the drain-source voltage Vds exceeds the voltage V1, the voltage Vgs is clamped at 4V, so the curve S5 moves toward S4 (Vgs = 4V), and toward x3, which is the intersection of S2 and S4. . Since the transition to the intersection point x3 is a positive feedback operation, the MOSFET (M1) is stabilized in a state where the current is suppressed at the operation point of x3. Thereafter, when the ambient temperature of the MOSFET (M1) rises and the output signal of the D flip-flop 21 becomes H level, the drain current Id becomes 0A.

  Next, with reference to FIG. 4, the operation in the case where a short circuit abnormality has already occurred before the MOSFET (M1) is turned on will be described. Since Vds = 12V (12V is a voltage of VB) before the MOSFET (M1) is turned on, the clamp circuit 14 is enabled. When the MOSFET (M1) is turned on, the drain current Id increases along the load line S2 when the short circuit abnormality occurs. However, since it is clamped at Vgs = 4V, the drain current Id is stabilized at the operating point x3 which is the intersection of S2 and S4. Thereafter, when the ambient temperature of the MOSFET (M1) rises and the output signal of the D flip-flop 21 becomes H level, the drain current Id decreases along the same path and becomes 0A.

  As described above, in the load circuit control device according to the first embodiment, when the source voltage VS of the MOSFET (M1) is lowered to a predetermined level, the clamp circuit 14 is activated and the MOSFET (M1) When the gate voltage exceeds the voltage V2, the current is drawn from the gate, and the gate voltage VG is clamped to the voltage V2. Therefore, a short circuit abnormality occurs in the load 11, the drain-source voltage Vds of the MOSFET (M1) increases (in other words, the source voltage VS decreases), and an overcurrent flows in the load circuit. However, since the current value at this time can be suppressed to a certain value or less, damage to the load circuit due to the occurrence of overcurrent can be prevented.

  Further, when the short circuit abnormality continues and the ambient temperature of the MOSFET (M1) is overheated, the transistor M8 can be turned on by the operation of the D flip-flop 21, and the MOSFET (M1) can be shut off. It can be surely protected from overheating.

  Moreover, since an arbitrary clamp voltage can be set by appropriately changing the current value of the current source CC2, the clamp voltage can be set finely as compared with the case where a Zener diode is used as in the prior art.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing the configuration of the load circuit according to the second embodiment of the present invention and the control device 12a connected to the load circuit. In the second embodiment, the major difference compared to the first embodiment described above is that the clamp operation control circuit 15 is provided with a series connection circuit of a resistor R3 (second resistor) and a resistor R8 (third resistor). This is the point. That is, in the second embodiment, a series connection circuit of resistors R3 and R8 is provided between the DC power supply VB and the ground, and the connection point (voltage V5) of each of the resistors R3 and R8 is the negative input of the comparator CMP1. Connected to the terminal. As a result, the voltage V5 (reference voltage) obtained by dividing the voltage VB by the resistors R3 and R8 is supplied to the negative side input terminal of the comparator CMP1.

  In addition, the current source CC2 is connected to the DC power supply VB, the amplifier AMP2 and the transistor M9 (N-type) are provided, and the resistors R6 and R7 for dividing the voltage VS are provided. This is different from the first embodiment described above.

  Next, the operation of the second embodiment will be described. In the circuit shown in FIG. 5, the source voltage VS of the MOSFET (M1) is divided by the resistors R6 and R7, and the same voltage as the voltage obtained by dividing is generated as the voltage V3. That is, the connection point p11 between the resistors R6 and R7 is connected to the negative input terminal of the amplifier AMP2, the output terminal of the amplifier AMP2 is connected to the gate of the transistor M9, and one end of the transistor M9 is connected to the plus of the resistor R2 and the amplifier AMP2. It is connected to the side input terminal (voltage V3) and the other end is connected to the ground. The plus side input terminal of the amplifier AMP2 is connected to the plus side input terminal of the comparator CMP1.

  In the control device 12a according to the second embodiment configured as described above, the same effect as that of the first embodiment described above can be achieved, and the voltage supplied to the negative input terminal of the comparator CMP1 is a power supply. Since the voltage VB is the voltage V5 obtained by dividing the voltage VB with the resistors R3 and R8, the voltage V5 varies as the power supply voltage VB varies. Therefore, even when the output voltage changes greatly depending on the charging state, such as a battery mounted on a vehicle, the voltage V5 corresponding to this change can be generated and supplied to the comparator CMP1. Therefore, the timing for enabling the clamp circuit 14 can be set appropriately.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a load circuit according to the third embodiment of the present invention and a control device 12b connected to the load circuit. In the third embodiment, compared with the first embodiment described above, the back electromotive force detection circuit (back electromotive force detection means) 17 is provided, and the OR circuit OR and the NAND circuit NAND are provided in the clamp operation control circuit 15b. It is different in that is provided. Details will be described below.

  The counter electromotive force detection circuit 17 includes a comparator CMP3 (second comparison means), a capacitor C1, and resistors R9, R10, and R11. C1, R9, and R10 constitute a time constant circuit. The point p1, which is the drain of the MOSFET (M1), is connected to the negative side input terminal of the comparator CMP3 via the resistor R9. Further, the point p1 is connected to the ground via a series connection circuit of resistors R10 and R11, a capacitor C1 is arranged in parallel with the resistor R11, and the connection point of the resistors R10 and R11 is the positive input of the comparator CMP3. Connected to the terminal. Further, in a normal time, the voltage supplied to the minus side input terminal of the comparator CMP3 is set to be slightly higher than the voltage supplied to the plus side input terminal. In other words, when the load 11 is operating normally, the output signal ELV of the comparator CMP3 is at L level.

  The clamp operation control circuit 15b includes a comparator CMP1, a resistor R3, a current source CC3, an OR circuit OR, and a NAND circuit NAND. As in FIG. 1, the voltage at the connection point between the resistor R3 and the current source CC3 is V1. Here, the circuit is different from the circuit shown in FIG. 1 in that the voltage V1 is supplied to the positive input terminal of the comparator CMP1 and the voltage VS is supplied to the negative input terminal.

  The output terminal of the comparator CMP1 is connected to one input terminal of the OR circuit OR, and the other input terminal is connected to the output terminal of CMP3. The output terminal of the OR circuit OR is connected to one input terminal of the NAND circuit NAND, and the other input terminal is connected to a resistor R5 that is a supply point of the drive signal. The output terminal of the NAND circuit NAND is connected to the gate of the transistor M7 (clamp operation control circuit 15b ').

  Further, a resistance RW and an inductance LW exist in the wiring connecting the point p1 which is the drain of the MOSFET (M1) and the DC power supply VB.

  Next, the operation of the control device 12b according to the third embodiment will be described. In the third embodiment, the clamp operation control circuit 15b is provided with two logic circuits (OR, NAND), but the basic operation is the same as that of the first embodiment shown in FIG. That is, when the relationship of VS <V1 is established, the output signal DST of the comparator CMP1 becomes H level (opposite to the case of FIG. 1), the output signal of the OR circuit OR becomes H level, and the NAND circuit Since the two input signals of the NAND are both at the H level, the output signal is at the L level, and the clamp circuit 14 is enabled.

  On the other hand, when the relationship of VS> V1 is established by increasing the voltage VS, the output signal DST of the comparator CMP1 becomes L level, and the output signal of the OR circuit OR becomes L level, so that the output of the NAND circuit NAND The signal becomes H level, and the operation of the clamp circuit 14 is invalidated.

  Here, when a dead short occurs in the load circuit (an excessive short circuit abnormality such that the wiring connected to the load 11 is directly connected to the ground), the resistance RW is connected to the wiring connecting the point p1 and the DC power source VB. The presence of the inductance LW generates a back electromotive force from the point p1 toward the DC power source VB. For this reason, the voltage of the point p1 falls rapidly.

  Along with this, the voltage supplied to the negative side input terminal of the comparator CMP3 rapidly decreases. On the other hand, the voltage supplied to the plus side input terminal cannot be rapidly lowered due to the presence of the time constant due to the resistors R10 and R11 and the capacitor C1. Therefore, the output signal ELV of the comparator CMP3 is inverted from the L level to the H level.

  As a result, since the output signal of the OR circuit OR becomes H level and the output signal of the NAND circuit NAND becomes L level, the transistor M7 is turned off, and the clamp circuit 14 operates effectively. That is, the clamp circuit 14 is validated regardless of the output of the comparator CMP1 of the clamp operation control circuit 15b.

  Therefore, similarly to the above-described operation, the gate-source voltage Vgs of the MOSFET (M1) is clamped to the voltage V2 (V2 = 4 V), and the current IL flowing through the load 11 is limited.

  In this way, the load circuit control device according to the third embodiment can achieve the same effects as those of the first embodiment described above, and in addition, when a dead short occurs in the load circuit. Regardless of whether or not the voltage VS decreases (regardless of the output signal DST of the comparator CMP1), the clamp circuit 14 is effectively operated immediately and the voltage Vgs is clamped. Can be protected from current.

  The load circuit control device according to the present invention has been described above based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part is an arbitrary configuration having the same function. Can be replaced.

  The present invention is extremely useful for suppressing overcurrent when a short circuit abnormality occurs in a load circuit.

DESCRIPTION OF SYMBOLS 11 Load 12 Control apparatus 13 Drive circuit (drive means)
14 Clamp circuit (clamping means)
15 Clamp operation control circuit (Clamp operation control means)
16 Overheat protection circuit (overheat protection means)
17 Back electromotive force detection circuit (back electromotive force detection means)
21 D flip-flop (latch circuit)
INV Inverter M1 Field Effect Transistor (MOSFET)
VB DC power supply VP Superimposed power supply V4 Reference power supply CC1 to CC4 Current source AMP1 Amplifier (amplifying means)
CMP1-CMP3 comparator M2-M9 transistor D1 diode

Claims (10)

In a load circuit control device that controls on / off of a load by switching on and off a field effect transistor provided between a DC power supply and a load,
A superposition power source connected in series to the direct current power source, and when a drive signal is supplied, current is supplied from the superposition power source to the gate of the field effect transistor to increase a gate voltage; Driving means for turning on the transistor;
A fluctuation voltage (V2) set to be changed in conjunction with the source voltage of the field effect transistor and set to be a predetermined voltage higher than the source voltage is generated, and the gate voltage exceeds the fluctuation voltage (V2). A clamping means for extracting a part of the current output from the superimposed power source and clamping the gate voltage to a predetermined voltage;
A control apparatus for a load circuit, comprising:   A reference voltage (V1, V5) set lower than the source voltage when a normal load current is flowing is generated, and when the source voltage exceeds the reference voltage, the clamping function by the clamping means is disabled. 2. The load circuit control device according to claim 1, further comprising clamping operation control means for performing the operation.   The clamp operation control means includes a series connection circuit of a first resistor (R3) and a third current source (CC3) interposed between the DC power supply and the ground, from the DC power supply (CC3 * R3 3. The load circuit control device according to claim 2, wherein the reference voltage (V <b> 1) is a voltage dropped by a voltage indicated by).   The clamp operation control means includes a series connection circuit of a second resistor (R3) and a third resistor (R8) interposed between the DC power supply and the ground, and outputs a voltage output from the DC power supply. The load circuit control device according to claim 2, wherein a voltage divided by the first resistor and the second resistor is used as the reference voltage (V5). The driving means includes
A first current source (CC1) for supplying a constant current when the drive signal is supplied;
A current mirror circuit having two current paths, one of which is connected to the first current source and the other of which is connected to the gate of the field effect transistor;
The current of the first current (CC1) is supplied from the superimposed power source to the gate of the field effect transistor when the driving signal is supplied. The load circuit control device according to claim 1. The clamping means includes
A second current source (CC2) and a fourth resistor (R2) interposed between either the superimposed power source or the DC power source and the source of the field effect transistor;
By supplying a constant current to the fourth resistor (R2) by the second current source, the variable voltage (V2) that changes so as to be higher than the source voltage by a predetermined voltage at one end of the first resistor. Generate
And amplifying means (AMP1) for outputting a signal corresponding to the difference between the fluctuation voltage and the gate voltage;
A first switch (M6) for controlling an energization current in accordance with an output signal of the amplifying means and extracting a predetermined amount of current from a current supplied to the gate;
The load circuit control device according to any one of claims 1 to 5, further comprising:   2. The apparatus according to claim 1, further comprising overheat protection means for shutting off the field effect transistor and protecting the load circuit from overheating when the ambient temperature of the field effect transistor reaches a predetermined temperature. The load circuit control device according to any one of claims 1 to 6. The overheat protection means includes:
A diode installed around the field effect transistor;
A fourth current source (CC4) for supplying a constant current to the diode;
First comparison means (CMP2) for comparing a voltage generated in the diode with a reference voltage (V4);
A latch circuit that outputs a latch signal when a voltage generated in the diode falls below the reference voltage V4;
A second switch (M8) for connecting the output point of the drive signal to the ground when the latch signal is output;
The load circuit control device according to claim 7, further comprising: Further comprising back electromotive force detection means for detecting back electromotive force from the field effect transistor toward the DC power source when the field effect transistor is turned on;
When the back electromotive force detection means detects the occurrence of a back electromotive force, the clamp function by the clamp means is validated regardless of the output signal of the clamp operation control means. The load circuit control device according to any one of claims 1 to 8. The back electromotive force detection means has a connection point between the drain of the field effect transistor and the DC power supply as a point p1,
A time constant circuit that outputs a voltage that is set to a predetermined time constant and is set to be slightly lower than the voltage at the point p1 in a normal state;
Second comparing means (CMP3) for comparing the voltage at the point p1 with the output voltage of the time constant circuit;
10. The load circuit control device according to claim 9, wherein when the voltage at the point p <b> 1 falls below the output voltage of the time constant circuit, it is determined that a back electromotive force has occurred.

Images