JP2011040594A - Method for manufacturing thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that when the heat applied to an α-Si layer by an excimer laser is transmitted to a metal light blocking layer via an insulating layer and the α-Si layer is recrystallized by being cooled, the characteristics of a polycrystal silicon layer vary widely depending on the influence of the pattern shape of the metal layer because the cooling rate of the α-Si layer is influenced by the pattern shape of the metal layer. <P>SOLUTION: The rectangular metal light blocking layer 105, which is uniformly shaped and distanced, is scanned by the excimer laser in the longitudinal direction to reform the α-Si layer to the polycrystal silicon layer 115. Since the excimer laser scans to the longitudinal direction, the metal light blocking layer 105 is laser annealed in the continuous state. Thereby, the polycrystal silicon layer 115 on the metal light blocking layer 105 becomes highly homogeneous. Thereby, the electric characteristics of TFT 101 formed on the metal light blocking layer 105 becomes homogeneous, and the display uniformity of a liquid crystal device 100 can be increased. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor.

  Thin film transistors (hereinafter also referred to as TFTs) are suitably used for liquid crystal devices, organic electroluminescence devices (hereinafter also referred to as organic EL devices), and the like. In recent years when high-speed operation is required, a polycrystalline silicon layer having a higher mobility than an amorphous silicon layer (hereinafter also referred to as an α-Si layer) is preferably used as a semiconductor layer constituting a TFT. Yes.

  As the polycrystalline silicon layer constituting the TFT, a polycrystalline silicon layer having a low grain boundary density, that is, a large grain size, which has a uniform orientation direction so as to enable high-speed operation and lowers the mobility of the TFT is used. It is preferable. A method for forming such a polycrystalline silicon layer is described in Patent Document 1. As a typical method for forming a polycrystalline silicon layer, first, an α-Si layer is deposited using a CVD (chemical vapor deposition) method, and then the α-Si layer is melted / regenerated using an excimer laser beam or the like as a heat source. A method of forming a polycrystalline silicon layer by crystallization is known.

  At this time, the excimer laser light is oscillated in pulses so that the emission time is about several tens of nanometers, and is irradiated to the α-Si layer. In this way, the energy of the excimer laser light is converted into heat on the surface of the α-Si layer, and this heat is transferred to the inside of the α-Si layer, so that only the α-Si layer is melted, and the temperature in other regions. The rise can be suppressed. Therefore, it is possible to use a substrate having a lower heat resistance than quartz glass, such as non-alkali glass, which is advantageous in terms of cost. In addition, since a material having low heat resistance, that is, a softening point can be used, it is possible to cope with an increase in the size of a substrate, which is difficult with quartz glass.

  Here, in the case where a TFT is used for pixel driving of a liquid crystal device or an organic EL device, it is preferable to provide a light shielding layer that shields light entering the TFT in order to prevent leakage current from being generated by light carriers. As a material of the light shielding layer, it is preferable to use a material that can withstand the manufacturing process temperature of the TFT. For example, a metal such as molybdenum is used. That is, the TFT is formed in a region that covers the metal layer via the insulating layer.

JP 2002-176180 A

  When the α-Si layer is melted / recrystallized using an excimer laser or the like as an energy source, the heat applied to the α-Si layer is transferred to the metal layer through the insulating layer. The α-Si layer is melted and then recrystallized by being cooled by the metal layer. In this case, the cooling rate of the α-Si layer is affected by the pattern shape of the metal layer. Therefore, the characteristics of the polycrystalline silicon layer vary due to the influence of the pattern shape of the metal layer. Therefore, the electrical characteristics of TFTs using this polycrystalline silicon layer as a semiconductor layer also vary greatly, and there is a problem that display image quality is lowered when used for pixel driving of a liquid crystal device or an organic EL device.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. Here, “up” is defined as the direction from the inside of the substrate toward the first surface. In addition, when “above XX” is described, the case where it is not in direct contact with XX is also included.

  [Application Example 1] In the thin film transistor manufacturing method according to this application example, a metal layer having a rectangular shape, a chamfered rectangular shape, or a planar shape including a longitudinal direction and a lateral direction is formed on a first surface of a substrate. A step of forming a silicon nitride layer overlying the first surface, a step of forming a silicon oxide layer overlying the first surface, and a layer of silicon overlying the first surface Forming a layer, irradiating the silicon layer with a pulsed excimer laser beam while scanning in the longitudinal direction of the metal layer, modifying the silicon layer into a polycrystalline silicon layer, and the metal Forming a plurality of thin film transistors using the polycrystalline silicon layer overlapping with the layer in a planar manner as a channel.

  According to this, a polycrystalline silicon layer modified under the same conditions is used for the channel of the thin film transistor by irradiating pulsed excimer laser light. Therefore, a plurality of thin film transistors with uniform electrical characteristics can be obtained.

  Application Example 2 In the method of manufacturing a thin film transistor according to the application example, a plurality of the metal layers are provided on the first surface of the substrate with a shape and an interval between the metal layers being aligned. Features.

  According to the application example described above, a polycrystalline silicon layer modified under the same conditions is obtained on the first surface side of the substrate. Therefore, it is possible to obtain a plurality of thin film transistors having the same electrical characteristics on the first surface side.

  [Application Example 3] A method of manufacturing a thin film transistor according to the above application example, wherein the metal layer has a light shielding property, and a plurality of the thin film transistors are aligned in a longitudinal direction of the metal layer, and at least the channel Is overlapped with the metal layer in a planar manner.

  According to the application example described above, when applied to a light control using a thin film transistor, it is possible to prevent at least light penetration into the channel of the thin film transistor, and the thin film transistor due to carrier generation due to light penetration. It is possible to prevent the influence on the operation.

  Application Example 4 A method of manufacturing a thin film transistor according to the application example, wherein the thin film transistor has a channel, a source, and a drain aligned in a longitudinal direction of the metal layer.

  According to the application example described above, the width of the thin film transistor can be reduced. By reducing the width of the thin film transistor, the width of the metal layer for preventing light intrusion can be reduced. Therefore, it is possible to take a wide area for light control and increase the aperture ratio.

  Application Example 5 In the method of manufacturing a thin film transistor according to the application example, the pulsed excimer laser light is irradiated to the same portion of the silicon layer 40 times or more and 150 times or less. .

  According to the application example described above, by irradiating the pulsed excimer laser light 40 times or more, the grain size of the polycrystalline silicon layer can be increased and the alignment direction can be made uniform. Therefore, it is possible to form a thin film transistor having a large mutual conductance. Moreover, the damage which a polycrystalline-silicon layer receives can be suppressed by suppressing to the frequency | count of 150 times or less. In addition, by limiting the number of times to 150 times or less, the time required for the manufacturing process can be suppressed, and the throughput can be increased.

  Application Example 6 A method for manufacturing a thin film transistor according to the application example described above, wherein the thickness of the silicon oxide layer is 200 nm or more and 500 nm or less.

  According to the application example described above, by providing the thickness of 200 nm or more, the orientation direction of the polycrystalline silicon layer can be aligned with the (111) direction. In addition, by providing the thickness of 500 nm or less, it is possible to suppress the generation of cracks due to stress generated when the silicon oxide layer is deposited.

  Application Example 7 A manufacturing method of a thin film transistor according to the application example, wherein the metal layer has a thickness of 50 nm to 500 nm.

  According to the application example described above, by setting the thickness of the metal layer to 50 nm or more, it becomes possible to suppress light penetration into the thin film transistor as the light shielding layer. Moreover, generation | occurrence | production of the crack of the metal material by the stress which generate | occur | produces when depositing a metal material can be suppressed by restraining to 500 nm or less.

  Application Example 8 In the method for manufacturing a thin film transistor according to the application example, the silicon nitride layer has a thickness of 50 nm to 500 nm.

  According to the application example described above, the intrusion of impurities from the metal layer or the substrate can be prevented by setting the thickness of the silicon nitride layer to 50 nm or more. Further, by setting the thickness to 500 nm or less, it is possible to suppress the generation of cracks due to stress generated when the silicon nitride layer is deposited. Further, by suppressing the thickness to 500 nm or less, the thermal coupling between the metal layer and the silicon layer can be made dense.

  Application Example 9 A method for manufacturing a thin film transistor according to the application example described above, wherein the silicon layer has a thickness of 30 nm to 100 nm.

  According to the application example described above, since the thickness of the silicon layer is 30 nm or more, it is possible to prevent the silicon layer from being broken when the pulsed excimer laser light is irradiated. Further, by suppressing the thickness to 100 nm or less, it is possible to dissolve / recrystallize to the deep part of the silicon layer.

FIG. 6 is a layout diagram when a TFT is applied to a liquid crystal device. Sectional drawing in the A-A 'line | wire of FIG. (A)-(c) is process sectional drawing which shows the manufacturing process of TFT concerning 3rd Embodiment. (A)-(c) is process sectional drawing which shows the manufacturing process of TFT concerning 3rd Embodiment. (A) is a reverse pole figure when the thickness of a silicon oxide layer is 50 nm, (b) is a reverse pole figure when the thickness of a silicon oxide layer is 200 nm.

Hereinafter, embodiments embodying the present invention will be described with reference to the drawings.
First Embodiment: Planar Configuration of Pixel
Hereinafter, the planar configuration of the TFT according to the present embodiment will be described with reference to the drawings. FIG. 1 is a layout diagram when the TFT according to this embodiment is applied to a liquid crystal device, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 2, the portion constituting the TFT 101 is shown in the drawing, and the description of the liquid crystal layer and the like is omitted.

  A liquid crystal device 100 shown in FIG. 1 has a TFT 101, a source line 102, a pixel electrode 103, a gate line 104, a metal light shielding layer 105 as a metal layer, and a gate electrode 106 (overlap with a channel 114) on the surface as a first surface. , Source 107 and drain 108. In order to extend the potential holding time of the liquid crystal device 100, it is preferable to adopt a configuration including a storage capacitor (not shown).

  The source line 102 has a function of applying a potential to the source 107 of the TFT 101. The pixel electrode 103 applies a potential applied via the source line 102 to a liquid crystal layer (not shown), and controls the light transmittance of the liquid crystal layer. The gate line 104 has a function of applying a potential to the gate electrode 106 and rewriting / holding the potential applied from the source line 102. The metal light-shielding layer 105 as a metal layer has a function of preventing light from entering the TFT 101 and preventing leakage current from being generated by optical carriers.

  The gate electrode 106, the channel 114, the source 107, and the drain 108 constitute the TFT 101. The TFT 101 controls the potential applied to the pixel electrode 103 by applying or holding the potential applied to the source 107 to the drain 108 based on the potential applied to the gate electrode 106.

  Further, as shown in FIG. 1, a plurality of metal light shielding layers 105 are arranged with the same width (shape) and the same spacing in accordance with the pixel pitch. Therefore, when the thin film transistor manufacturing method described later is used, the electrical characteristics of the TFTs 101 can be made uniform. The metal light-shielding layers 105 are preferably arranged with the same width and the same spacing so as to match the pixel pitch, but this is not an essential configuration.

  In the TFT 101, a plurality of metal light shielding layers 105, channels 114, sources 107, and drains 108 are aligned in the longitudinal direction so as to overlap in a plane. Therefore, light intrusion into the TFT 101 can be prevented, and generation of leakage current due to optical carriers is suppressed. In addition, although the above-mentioned effect is acquired by arranging two or more with respect to a longitudinal direction, this is not an essential structure. Further, only the channel 114 may overlap the metal light shielding layer 105 in a planar manner.

  Further, the TFT 101 has a channel 114, a source 107, and a drain 108 arranged in alignment with the longitudinal direction of the metal light shielding layer 105. For this reason, the width (short side) of the metal light shielding layer 105 can be reduced. Even in this case, it is not essential to have an arrangement aligned in the longitudinal direction. In particular, when the channel width of the TFT 101 is larger than the channel length, it is also preferable to arrange the source 107 and the drain 108 so as to be bent.

Second Embodiment: Cross-sectional Configuration of TFT
Hereinafter, a cross-sectional configuration of the TFT according to the present embodiment will be described with reference to the drawings. FIG. 2 is a cross-sectional view of the main part of the TFT taken along the line AA ′ in FIG. 1, and descriptions of contacts, liquid crystal layers and the like are omitted. The TFT 101 includes a gate electrode 106, a source 107, a drain 108, a channel 114, a substrate 109, a base protective layer 110, a metal light shielding layer 105 as a metal layer, a silicon nitride layer 111, a silicon oxide layer 112, a gate insulating layer 113, a polycrystal. A silicon layer 115, a source electrode 116, a drain electrode 117, and an interlayer insulating layer 118 are provided.

  The substrate 109 supports the TFT 101 and the like, and for example, alkali-free glass can be used. The base protective layer 110 is formed to prevent the intrusion of contaminants from the substrate 109, suppress the influence of the surface state (such as the polishing state of the substrate 109), and stabilize the quality of the TFT 101 and the like. The metal light-shielding layer 105 mainly suppresses light penetration into the channel 114 and prevents the occurrence of leakage current due to optical carriers. As the metal constituting the metal light shielding layer 105, for example, Mo, Cr, Ni, Cu, Ta, W, AlNd (aluminum added with neodymium), or Al is preferably used. In this embodiment, Mo is used. The metal light shielding layer 105 desirably has a thickness of 50 nm or more in order to ensure light shielding properties. Moreover, in order to suppress the occurrence of cracks and the like due to internal stress, the layer thickness is desirably 500 nm or less. In this embodiment, Mo is formed to have a layer thickness of 200 nm.

  The silicon nitride layer 111 is formed to prevent impurities from entering the channel 114 from the metal light shielding layer 105 or the substrate 109. The thickness of the silicon nitride layer 111 is preferably 50 nm or more, so that impurities can be prevented from entering from the metal light shielding layer 105 and the substrate 109. Further, by setting the thickness to 500 nm or less, generation of cracks due to stress generated when the silicon nitride layer 111 is deposited can be suppressed. Further, by suppressing the thickness to 500 nm or less, the thermal coupling between the metal light shielding layer 105 and the polycrystalline silicon layer 115 can be made dense.

  The silicon oxide layer 112 has a function of controlling the orientation of the polycrystalline silicon layer 115. When the metal light-shielding layer 105 is provided, when the α-Si layer is modified to the polycrystalline silicon layer 115 by laser annealing, the orientation thereof varies, and as a result, the electrical characteristics of the TFT 101 deteriorate. In order to prevent this phenomenon, the thickness of the silicon oxide layer 112 is preferably 200 nm or more. By setting the thickness to 200 nm or more, the orientation direction of the polycrystalline silicon layer 115 can be aligned with the (111) direction. The reason why this phenomenon occurs is not yet clear, but it is considered that the orientation is controlled in the (111) direction by changing the temperature profile of the cooling process after laser irradiation and decreasing the cooling rate. The thickness of the silicon oxide layer 112 is preferably 500 nm or less, and generation of cracks due to internal stress generated when the silicon oxide layer 112 is deposited can be suppressed.

  As will be described later, the polycrystalline silicon layer 115 is formed by modifying the α-Si layer into the polycrystalline silicon layer 115 by laser annealing. Here, the state before laser annealing is not limited to α-Si, but may be in a state of, for example, microcrystalline silicon. In laser annealing, laser light is absorbed on the outermost surface of the α-Si layer, and the energy of the laser light is converted into thermal energy. Then, melting / recrystallization is performed by the thermal energy at the outermost surface diffusing into the deep part of the α-Si layer. Therefore, the thickness of the polycrystalline silicon layer 115 is preferably 100 nm or less. If it is 100 nm or less, dissolution / recrystallization can be performed. It is preferable to provide a thickness of 30 nm or more. In this case, the polycrystalline silicon layer 115 can be prevented from being cut.

  The gate insulating layer 113 has a function of applying an electric field to the channel 114 in cooperation with the gate electrode 106 and inducing carriers in the channel 114. As the gate insulating layer 113, for example, a silicon oxide layer using a chemical vapor deposition (CVD) method can be used. In place of silicon oxide, an insulating material such as silicon nitride, hafnium oxide, or aluminum oxide may be used. Although the thickness of the gate insulating layer 113 varies depending on the voltage handled by the TFT 101 (thickness increases when a high voltage is used), a value of about 100 nm can be exemplified. The gate electrode 106 has a function of applying an electric field to the channel 114 as described above. The gate electrode 106 can be made of a metal material such as Al, Ti, Ta, or Mo. Here, Al is used. Alternatively, a metal obtained by adding Nd, Cu, Si, or the like to Al may be used.

The interlayer insulating layer 118 is formed to electrically isolate the source electrode 116, the drain electrode 117, and the like. The source 107 and the drain 108 are formed so that a current corresponding to carriers induced in the channel 114 flows. The source 107 and the drain 108 have a high impurity concentration (for example, about 5 × 10 ²⁰ cm ⁻³ ), and can form an ohmic junction with the metal. The source 107 and the source electrode 116, It also functions as a region for electrically connecting the drain 108 and the drain electrode 117.

(Third embodiment: TFT manufacturing process)
Hereinafter, the manufacturing process of the TFT according to the present embodiment will be described with reference to the drawings. 3A to 3C and 4A to 4C are process cross-sectional views illustrating the manufacturing process of the TFT according to this embodiment. Here, the manufacturing process of the TFT 101 is described with respect to a cross section taken along the line AA ′ of FIG. In the manufacturing process, the manufacturing part of the TFT 101 is selected and described. For example, a photolithography process required for manufacturing peripheral circuits is omitted.

  First, as step 1, the substrate 109 is cleaned. As a material constituting the substrate 109, glass or resin is typically used. In this embodiment, alkali-free glass is used for the substrate 109. Here, the base protective layer 110 may be formed over the substrate 109, or a glass-based layer such as a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer may be formed. An organic layer such as polyimide or acrylic may be formed. In particular, when a resin-based substance is used as the substrate 109, the stratification temperature can be lowered by using the organic base protective layer 110.

  Then, a metal layer is deposited using a sputtering method or the like, a resist mask or the like is formed in a desired portion, and etching is performed to form a metal light shielding layer 105. As the metal constituting the metal light shielding layer 105, for example, Mo, Cr, Ni, Cu, Ta, W, AlNd (aluminum with neodymium added), or Al may be used. In this embodiment, Mo is used. The metal light shielding layer 105 desirably has a thickness of 50 nm or more in order to ensure light shielding properties. Moreover, in order to suppress the occurrence of cracks and the like due to internal stress, the layer thickness is desirably 500 nm or less. In this embodiment, Mo is formed to have a layer thickness of 200 nm. FIG. 3A shows a cross-sectional view after the steps so far are completed. Here, as a manufacturing method of the metal light-shielding layer 105, the metal light-shielding layer 105 is formed by forming a metal layer once on the entire surface and then performing a photolithography process and an etching process. This is performed using a physical vapor deposition method. Alternatively, a metal mask or a silicon mask may be used as a vapor deposition mask without forming an etching process. Examples of physical vapor deposition include vacuum vapor deposition, ion plating, ion beam vapor deposition, conventional sputtering, magnetron sputtering, ion beam sputtering, ECR sputtering, and the like. Here, as shown in FIG. 1, the metal light-shielding layer 105 is arranged with the same width (shape) and the same interval so as to match the pixel pitch, and has a rectangular shape having a longitudinal direction and a short direction. It has a shape. In the example of FIG. 1, the direction along the gate line 104 is the longitudinal direction, and the direction along the source line 102 is the short direction. Here, the shape of the metal light shielding layer 105 is not limited to a rectangle, and a corner R (rounded corner) or a C-face (chamfered) shape may be used. Further, a shape different from a rectangle, such as an ellipse, may be used, and any shape having a longitudinal direction and a transverse direction can be used.

  Next, as step 2, a silicon nitride layer 111 is formed. The silicon nitride layer 111 is formed using, for example, a CVD method using a silane-ammonia gas or a sputtering method. The thickness of the silicon nitride layer 111 is desirably 50 nm or more in order to prevent metal contamination from the metal light shielding layer 105. Moreover, since there exists a possibility that a crack may generate | occur | produce in a silicon nitride layer by the stress at the time of layer formation, it is preferable that it is 500 nm or less in thickness. In this embodiment, it is formed to have a thickness of 100 nm. FIG. 3B shows a cross-sectional view after the steps so far are completed.

  Next, as step 3, a silicon oxide layer 112 is formed. The silicon oxide layer 112 has a function of controlling the orientation of the polycrystalline silicon layer 115 shown in FIG. When the metal light shielding layer 105 is provided, when an α-Si layer 115a as a silicon layer, which will be described later, is modified to a polycrystalline silicon layer 115 by laser annealing, the orientation varies, and as a result, the electrical characteristics of the TFT 101 are changed. descend. In order to prevent this phenomenon, the thickness of the silicon oxide layer 112 is preferably 200 nm or more. By setting the thickness to 200 nm or more, the orientation direction of the polycrystalline silicon layer 115 can be aligned with the (111) direction. The reason why this phenomenon occurs is not yet clear, but it is considered that the orientation is controlled in the (111) direction by changing the temperature profile of the cooling process after laser irradiation and decreasing the cooling rate. The thickness of the silicon oxide layer 112 is preferably 500 nm or less, and generation of cracks due to internal stress generated when the silicon oxide layer 112 is deposited can be suppressed. In this embodiment, it is formed to have a thickness of 300 nm. FIG. 3C shows a cross-sectional view after the steps so far are completed.

Next, as step 4, an α-Si layer 115a as a silicon layer is formed using a plasma CVD (PECVD) method or the like. The α-Si layer 115a has a layer thickness of 30 nm or more in order to suppress the phenomenon of agglomeration when the α-Si is irradiated with pulsed excimer laser light (described later) and the dissolution / recrystallization process is performed. It is preferable to have. In laser annealing described later, laser light is absorbed by the outermost surface of the α-Si layer 115a, and the energy of the laser light is converted into thermal energy. Then, the thermal energy at the outermost surface diffuses into the deep part of the α-Si layer 115a to perform dissolution / recrystallization. The α-Si layer 115a preferably has a layer thickness of 100 nm or less in order to be dissolved to a deep portion by pulsed excimer laser light. In this embodiment, the layer thickness is 50 nm. FIG. 4A shows a cross-sectional view after the steps so far are completed. Note that after forming the α-Si layer 115a, it is also preferable to insert an annealing step for desorbing hydrogen in the α-Si layer 115a. By desorbing hydrogen, it becomes possible to suppress ablation (a phenomenon in which the silicon layer is peeled off) due to rapid hydrogen desorption accompanying laser irradiation.
Note that the silicon layer is not limited to the α-Si layer 115a, and a microcrystalline silicon layer, a partially crystallized silicon layer, or the like may be used.

Next, as step 5, the α-Si layer 115a is irradiated with pulsed excimer laser light to crystallize the α-Si layer 115a, thereby forming a polycrystalline silicon layer 115. Intensity of pulsed excimer laser beam, the optimum value differs in a layer thickness of alpha-Si layer 115a and the like, it is preferable to irradiate with ² about energy density of 1 shot per 350mJ / cm ² ~450mJ / cm. Here, a XeCl excimer laser (wavelength 308 nm) is used as a pulsed excimer laser beam. For this, an excimer laser using a gas such as ArF (wavelength 193 nm), KrF (wavelength 248 nm), XeF (wavelength 353 nm) may be used instead of XeCl.

  Crystallization is performed by irradiating the α-Si layer 115a with multiple shots of pulsed excimer laser light. The number of shots is preferably 40 times or more. By irradiating 40 times or more, it becomes possible to obtain the polycrystalline silicon layer 115 in which the orientation direction is aligned in the (111) direction.

  Further, by suppressing the number of shots to 150 times or less, damage to the α-Si layer 115a can be suppressed and the polycrystalline silicon layer 115 can be obtained. In addition, by limiting the number of times to 150 or less, the time required for the step of obtaining the polycrystalline silicon layer 115 can be suppressed, and the throughput can be increased. In this embodiment, the XeCl excimer laser having a rectangular light shape and a short side of 0.4 mm is used to send at a pitch of 6 μm so that the number of shots per spot is approximately 67 times. Yes.

  Further, the XeCl excimer laser feed direction (scanning direction) is directed to the longitudinal direction of the metal light shielding layer 105. In the example of FIG. 1, the direction along the gate line 104 is the longitudinal direction, and the direction along the source line 102 is the short direction. The electrical characteristics of the polycrystalline silicon layer 115 in a region overlapping the metal light-shielding layer 105 in a planar manner by engraving the scanning direction of the XeCl excimer laser in the laser scanning direction (longitudinal direction of the metal light-shielding layer 105) shown in FIG. As compared with the case where the metal light shielding layer 105 is interrupted, it is possible to have high uniformity. Then, a plurality of TFTs 101 are formed using the polycrystalline silicon layer 115 in a region overlapping with the metal light shielding layer 105 as a channel 114. Since the polycrystalline silicon layer 115 has high uniformity in electrical characteristics, the electrical characteristics of the TFTs 101 can be made uniform. For example, when the TFT 101 is used for driving the pixel electrode 103 of the liquid crystal device 100 as shown in FIG. 1, the liquid crystal device 100 has a uniform luminance distribution, and the display image quality can be improved.

  5A and 5B show reverse pole figures of the polycrystalline silicon layer 115 formed under this laser irradiation condition. FIG. 5A is a reverse pole figure when the thickness of the silicon oxide layer is 50 nm, and FIG. 5B is a reverse pole figure when the thickness of the silicon oxide layer is 200 nm. In addition, an inverted pole figure is a figure which shows distribution of the direction where each crystal which comprises a polycrystal body is orientating.

  As shown in FIG. 5A, when the thickness of the silicon oxide layer 112 is 50 nm, the orientation direction of the polycrystalline silicon layer 115 is distributed almost uniformly. As shown in FIG. 5B, when the thickness of the silicon oxide layer 112 is 200 nm, the orientation direction of the polycrystalline silicon layer 115 is substantially aligned with the (111) direction. A cross-sectional view in the middle of crystallization with a XeCl excimer laser is shown in FIG.

Next, as step 6, the polycrystalline silicon layer 115 is etched using a resist mask to perform element isolation. At this time, it is preferable to align a plurality of sources 107, drains 108, and channels 114 in the longitudinal direction of the metal light shielding layer 105 as shown in FIG. In this case, the width of the TFT 101 can be reduced. By narrowing the width of the TFT 101, the width of the metal light shielding layer 105 for preventing light intrusion can be narrowed. Therefore, it is possible to take a wide area for light control and increase the aperture ratio.
Then, the gate insulating layer 113 is formed using a PECVD method or the like. The layer thickness of the gate insulating layer 113 depends on the breakdown voltage design of the TFT 101 shown in FIG. 2, but a silicon oxide layer having a layer thickness of about 100 nm can be exemplified as an example.

  Then, a metal material such as aluminum (Al), titanium (Ti), tantalum (Ta), or molybdenum (Mo) is deposited by a sputtering method or the like. Next, etching is performed using a resist mask to form the gate electrode 106. Next, ion implantation is performed using the gate electrode 106 as a mask to form the source 107, the drain 108, and the channel 114. The channel 114 is not ion-implanted, and the polycrystalline silicon layer 115 remains as it is. Then, after the ion implantation, a heat treatment at about 400 ° C. is performed to activate the impurities in the ion implanted region. FIG. 4C shows a cross-sectional view after the steps so far are completed.

  Next, an interlayer insulating layer 118 is deposited. Then, etching is performed using a resist mask to form a contact hole. Next, a metal material such as aluminum (Al), titanium (Ti), tantalum (Ta), or molybdenum (Mo) is deposited by a sputtering method or the like, and etched using a resist mask, whereby the source electrode 116 and the drain electrode 117 are formed. The TFT 101 shown in FIG. 2 is formed.

  DESCRIPTION OF SYMBOLS 100 ... Liquid crystal device, 101 ... TFT, 102 ... Source line, 103 ... Pixel electrode, 104 ... Gate line, 105 ... Metal light shielding layer, 106 ... Gate electrode, 107 ... Source, 108 ... Drain, 109 ... Substrate, 110 ... Base Protective layer, 111 ... silicon nitride layer, 112 ... silicon oxide layer, 113 ... gate insulating layer, 114 ... channel, 115 ... polycrystalline silicon layer, 115a ... α-Si layer, 116 ... source electrode, 117 ... drain electrode, 118 ... interlayer insulation layer.

Claims (9)

Forming a metal layer having a rectangular shape or a chamfered rectangular shape on a first surface of a substrate, or a planar shape including a longitudinal direction and a lateral direction;
Forming a silicon nitride layer so as to overlap the first surface side;
Forming a silicon oxide layer so as to overlap the first surface side;
Forming a silicon layer overlying the first surface;
Irradiating the silicon layer with a pulsed excimer laser beam while scanning in the longitudinal direction of the metal layer, and modifying the silicon layer into a polycrystalline silicon layer;
Forming a plurality of thin film transistors using the polycrystalline silicon layer overlapping the metal layer in a planar manner as a channel;
A method for producing a thin film transistor, comprising:   2. The thin film transistor manufacturing method according to claim 1, wherein a plurality of the metal layers are provided on the first surface of the substrate with a shape and an interval between the metal layers being aligned. 3. A method for manufacturing a transistor.   3. The method of manufacturing a thin film transistor according to claim 1, wherein the metal layer has a light shielding property, and a plurality of the thin film transistors are aligned in a longitudinal direction of the metal layer, and at least the channel is the channel. A method for manufacturing a thin film transistor, wherein the thin film transistor overlaps with a metal layer in a planar manner.   4. The method of manufacturing a thin film transistor according to claim 3, wherein the thin film transistor has the channel, the source, and the drain aligned in the longitudinal direction of the metal layer. .   5. The method of manufacturing a thin film transistor according to claim 1, wherein the pulsed excimer laser light is irradiated 40 times or more and 150 times or less to the same portion of the silicon layer. A method for producing a thin film transistor.   6. The method for manufacturing a thin film transistor according to claim 1, wherein the silicon oxide layer has a thickness of 200 nm to 500 nm.   6. The method of manufacturing a thin film transistor according to claim 1, wherein the metal layer has a thickness of 50 nm to 500 nm.   8. The method for manufacturing a thin film transistor according to claim 1, wherein the silicon nitride layer has a thickness of not less than 50 nm and not more than 500 nm. 9. 9. The method for manufacturing a thin film transistor according to claim 1, wherein the silicon layer has a thickness of 30 nm to 100 nm.