JP2011040521A - Protective circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective circuit capable of surely protecting an internal circuit against ESD, and inputting a signal to be input to the internal circuit without any loss. <P>SOLUTION: The protective circuit 100 provided between differential input terminals 103a, 103b and the internal circuit 101 that receives differential input or performs differential output includes a pair of MOS transistors 105a, 105b interposed between a pair of nodes N3, N4 connecting the differential input terminals 103a, 103b and internal circuit 101, and a reference power source GND for setting a reference potential. Then, gate terminals g1, g2 of the MOS transistors 105a, 105b are connected to each other, and a connection node N1 thereof is connected to a wiring node N3 through a capacitive element 104a, connected to the node N4 through a capacitive element 104b, and connected to the reference power source GND through a resistance element 108. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a protection circuit, and more particularly to a protection circuit for protecting a circuit from electrostatic discharge (ESD).

  The semiconductor device incorporates a protection circuit including a protection element that protects the internal circuit of the semiconductor chip from electrostatic discharge. The protection circuit operates to draw an ESD surge input from an external terminal of the semiconductor device and flow it to the ground wiring. As a result, the ESD surge does not flow into the internal circuit, and a high voltage can be prevented from being applied to the internal circuit. In the present specification, such a protection circuit is also referred to as an ESD (Electrostatic Discharge) circuit.

  FIG. 3 is a diagram illustrating a conventional ESD protection circuit. The illustrated ESD protection circuit includes two diodes 54 and 55, so that when an ESD is input from the external terminal 53, the ESD flows to the protection element 56. Note that r1 shown in the figure is a path through which a negative pulse ESD flows with respect to VSS. R2 is a path through which positive pulse ESD flows with respect to VSS. The prior art shown in FIG. 3 is described in Patent Document 1, for example.

FIG. 4 is a diagram showing another conventional ESD protection circuit. The ESD protection circuit shown in FIG. 4 does not have the diode 54 shown in FIG. 3, and instead uses the capacitive element C, the resistive element R, and the MOS transistor 61 to flow an ESD surge.
When a high-pulse ESD is input, the MOS transistor 61 causes a snapback phenomenon to flow a surge current, thereby protecting the internal circuit. At this time, the capacitive element C and the resistance element R apply a voltage to the gate of the MOS transistor 61 when ESD is input, so that snapback easily occurs.

  The ESD circuit shown in FIG. 4 can be applied when the diode 54 cannot be provided in the ESD circuit shown in FIG. 3 because a voltage higher than the power supply voltage is applied.

JP 2006-13446 A

  However, a high-speed signal may be input to the internal circuit. Therefore, the ESD protection circuit of FIG. 4 does not increase the gate voltage of the MOS transistor 61 with respect to the pulse of the signal to be input, and applies the gate voltage only when the ESD pulse is input. Therefore, it is required to flow a surge current. Such an operation is made possible by increasing the time constant determined by the capacitance and resistance value of the capacitive element C and the resistive element R for signal pulses and large for ESD.

However, in recent years, semiconductor devices have been required to have higher reliability against ESD. In addition, since a high-speed signal should be input to the internal circuit without loss, it is difficult to design the capacitive element C and the resistive element R so that only the ESD surge flows through the protection circuit.
The present invention has been made in view of these points, and provides a protection circuit that can reliably protect an internal circuit from ESD and that can input a signal to be input to the internal circuit without loss. With the goal.

  In order to solve the above problems, a protection circuit according to a first aspect of the present invention includes a pair of terminals that are differential input terminals or differential output terminals (for example, the differential input terminals 103a and 103b shown in FIG. A protection circuit provided between the output terminals 103c and 103d) and a protected circuit that receives or outputs a differential input (for example, the internal circuit 101 shown in FIG. 1), the pair of terminals And a pair of transistor elements (for example, the MOS transistors 105a and 105b shown in FIG. 1) interposed between each of the pair of wirings connecting the protected circuits and a reference power source for setting a reference potential, When the gates of the transistor elements (for example, the gate terminal g1 of the MOS transistor 105a and the gate terminal g2 of the MOS transistor 105b shown in FIG. 1) are connected to each other. In both cases, the connection node is connected to one of the pair of wirings via a first capacitor element (for example, the capacitor element 104a shown in FIG. 1), and a second capacitor having the same capacity as the first capacitor element. It is connected to the other of the pair of wirings via an element (for example, the capacitive element 104b shown in FIG. 1), and is connected to the reference power source via a resistance element.

  According to the first aspect of the present invention, when the differential input signal is input to the pair of terminals or the differential output signal is output from the pair of terminals, the transistor element can be turned off. Further, in the case where signals input to and output from the two nodes are not differential signals such as ESD, the signal can be prevented from being input to the protected circuit by snapping back the transistor. For this reason, the present invention can provide a protection circuit that can reliably protect the internal circuit from ESD and can input a signal to be input to the internal circuit without loss.

It is a circuit diagram for demonstrating the protection circuit of one Embodiment of this invention. FIG. 2 is a diagram for explaining a relationship between a gate voltage shown in FIG. 1 and a high-speed pulse that is differentially input. It is the figure which illustrated the conventional ESD protection circuit. It is another figure which illustrated the conventional ESD protection circuit.

Hereinafter, an embodiment of a protection circuit according to the present invention will be described with reference to the drawings.
(Constitution)
FIG. 1 is a circuit diagram for explaining a protection circuit according to an embodiment of the present invention. FIG. 1 shows an internal circuit 101 that is a protected circuit, and a protection circuit 100 according to this embodiment that protects the internal circuit 101.
The protection circuit 100 receives and outputs a differential input between a pair of differential input terminals 103a and 103b which are differential input terminals, and a differential output terminal 103c and 103d which is a pair of differential output terminals. It is provided between the internal circuit 101. A pair of MOS transistors 105a and 105b interposed between the pair of wiring nodes N3 and N4 connecting the differential input terminals 103a and 103b and the internal circuit and a reference power supply GND for setting a reference potential are provided. . The gate terminal g1 of the MOS transistor 105a and the gate terminal g2 of the MOS transistor 105b are connected to each other, and the connection node N1 is connected to the node N3 through the capacitive element 104a, and the capacitive element 104b having the same capacity as the capacitive element 104a. Is connected to the node 4 through the resistor element 108 and is connected to the reference power supply GND through the resistance element 108.

Note that the MOS transistors 105a and 105b are so-called normally-off transistors that are turned off when no voltage is applied to the gate electrodes.
The two nodes N3 and N4 shown in FIG. 1 are connected to differential input terminals 103a and 103b that input differential signals to the internal circuit 101, and differential output terminals 103c and 103d that output differential signals from the internal circuit 101. Has been. A pad connected to the differential input terminal 103a is shown as pad P, and a pad connected to the differential input terminal 103b is shown as pad N.

  The differential input signal is a signal pair formed by two signals having opposite polarities (positive and negative) of the potential input to the internal circuit 101. The differential output signal is a signal pair composed of two signals output from the internal circuit 101 and having opposite polarities. In the present embodiment, it is assumed that, in both the differential input signal and the differential output signal, the two signals constituting the signal pair have the same absolute value, that is, the average value is constant.

In the protection circuit of this embodiment, as described above, the node N3 is connected to the differential input terminal 103a and the differential output terminal 103c, and the node N4 is connected to the differential input terminal 103b and the differential output terminal 103d. It is not limited to. For example, the node N3 and the node N4 may be connected to at least one of the differential input terminals 103a and 103b and the differential output terminals 103c and 103d.
The protection circuit of this embodiment is further provided with diodes 106 and 107. The diodes 106 and 107 function to rectify the current input to the internal circuit 101.

(Operation)
Hereinafter, the operation of the protection circuit 100 of the present embodiment will be described. The protection circuit 100 can receive a high-speed signal by ESD (hereinafter also referred to as an ESD pulse) and a high-speed signal that should be input to the internal circuit 101 (hereinafter also referred to as a high-speed pulse).
When a high-speed pulse is input As described above, in the present embodiment, differential signals having the same absolute value and opposite polarities, that is, signals having a constant average value are input to the differential input terminals 103a and 103b. come. Further, the capacitors 104a and 104b have the same capacitance. Therefore, a voltage having the same value and opposite polarity is applied to the connection point p1 between the nodes N1 and N2 and the capacitive elements 104a and 104b by the capacitive elements 104a and 104b. As a result, the applied voltages cancel each other, and the potential applied to the connection point p1 becomes zero.

The potential at the connection point p1 becomes the gate voltage Vg applied to the gate terminals g1 and g2 of the MOS transistors 105a and 105b as it is. For this reason, the voltage applied to the gate terminals g1 and g2 of the MOS transistors 105a and 105b is 0V. In such a case, the MOS transistors 105a and 105b do not cause snapback.
With the above operation, in the present embodiment, a high-speed pulse can be input to the internal circuit 101 without flowing to the GND by the MOS transistors 105a and 105b.

  2A and 2B are diagrams for explaining the relationship between the gate voltage Vg shown in FIG. 1 and a high-speed pulse that is differentially input, and the vertical axis indicates the voltage of the high-speed pulse. Time is shown on the horizontal axis. FIG. 2A shows the case where the average value of the high-speed pulse varies, and FIG. 2B shows the case where the average value is constant. 2A and 2B, VP indicates a pulse input from the pad P shown in FIG. 1, and VN indicates a pulse input from the pad N shown in FIG.

As shown in FIG. 2A, when the average value of the high-speed pulse is different, the difference between the two is applied to the connection point p1, and the gate voltage Vg shown in FIG. 2A is generated. Thereafter, it attenuates due to the time constants of the capacitive element C and the resistive element R. At this time, depending on the value of the gate voltage Vg, there is a possibility that the input high-speed pulse may flow to the GND due to the snapback of the MOS transistors 105a and 105b. .
On the other hand, as shown in FIG. 2B, if the average value of the high-speed pulse is constant, the gate voltage Vg ′ applied to the connection point p1 hardly appears. Therefore, snapback of the MOS transistors 501a and 105b does not occur, and the input high-speed pulse is input to the internal circuit 101 without loss.

When an ESD pulse is input When an ESD pulse is input from either pad P or pad N, the potential at the connection point p1 rises. For this reason, the potentials of the gate terminals g1 and g2 rise, and the MOS transistors 105a and 105b perform a snapback operation. For this reason, the ESD pulse flows through the MOS transistors 105 a and 105 b to the GND and does not flow into the internal circuit 101.
Note that it is considered that the possibility that the ESD pulses are simultaneously input from the pads P and N, the average value of the signals is constant, and the potential is canceled at the connection point p1 is extremely low. Therefore, according to the present embodiment, it is possible to input a high-speed pulse to the internal circuit 101 without loss and flow only an ESD pulse to GND.

  The protection circuit of the present invention described above can be applied to any configuration as long as it is a protection circuit that protects an internal circuit that receives and processes an analog AC signal. Particularly, it is suitable for a semiconductor device to which electrostatic discharge can be input in a test process or the like.

53 External terminal 54 Diode 55 Diode 56 Protection element 61 Transistor 100 Protection circuit 101 Internal circuit 103 External terminal 103a, 103b Differential input terminal 103c, 103d Differential output terminal 104a, 104b Capacitance element 105a, 105b MOS transistor 106, 107 Diode

Claims (1)

A protection circuit provided between a pair of terminals that are a differential input terminal or a differential output terminal and a protected circuit that receives or outputs a differential input,
A pair of transistor elements interposed between each of the pair of wirings connecting the pair of terminals and the protected circuit and a reference power source for setting a reference potential;
The gates of the pair of transistor elements are connected to each other, and the connection node is connected to one of the pair of wirings via the first capacitor element, and the second capacitor has the same capacitance as the first capacitor element. A protective circuit connected to the other of the pair of wirings through a capacitive element and connected to the reference power supply through a resistive element.

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