JP2011040520A - Protective circuit - Google Patents

Protective circuit Download PDF

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Publication number
JP2011040520A
JP2011040520A JP2009185544A JP2009185544A JP2011040520A JP 2011040520 A JP2011040520 A JP 2011040520A JP 2009185544 A JP2009185544 A JP 2009185544A JP 2009185544 A JP2009185544 A JP 2009185544A JP 2011040520 A JP2011040520 A JP 2011040520A
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Japan
Prior art keywords
mos transistor
circuit
protection circuit
esd
gate terminal
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Pending
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JP2009185544A
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Japanese (ja)
Inventor
Koji Tomioka
幸治 富岡
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Asahi Kasei Electronics Co Ltd
旭化成エレクトロニクス株式会社
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Priority to JP2009185544A priority Critical patent/JP2011040520A/en
Publication of JP2011040520A publication Critical patent/JP2011040520A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective circuit capable of surely protecting an internal circuit against ESD, and inputting a signal to be input to the internal circuit without any loss. <P>SOLUTION: The protective circuit which is supplied with electric power from VDD and GND to protect the internal circuit 101 includes: a MOS transistor 104 connected between an external terminal 103 connected to the internal circuit 101, and GND; a MOS transistor 105 connected to a gate terminal g1 of the MOS transistor 104; and a delay circuit 106 which controls the MOS transistor 104 so as to supply a current input from the external terminal 103 connected to the internal circuit 101 to GND when the electric power is not supplied from VDD, and controls the MOS transistor 105 to turn off the MOS transistor 104 when the electric power is supplied from VDD. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a protection circuit, and more particularly to a protection circuit for protecting a circuit from electrostatic discharge (ESD).

  The semiconductor device incorporates a protection circuit including a protection element that protects the internal circuit of the semiconductor chip from electrostatic discharge. The protection circuit operates to draw an ESD surge input from an external terminal of the semiconductor device and flow it to the ground wiring. As a result, the ESD surge does not flow into the internal circuit, and a high voltage can be prevented from being applied to the internal circuit. In the present specification, such a protection circuit is also referred to as an ESD (Electrostatic Discharge) circuit.

  FIG. 5 is a diagram illustrating a conventional ESD protection circuit. The illustrated ESD protection circuit includes two diodes 54 and 55, so that when an ESD is input from the external terminal 53, the ESD flows to the protection element 56. Note that r1 shown in the figure is a path through which a negative pulse ESD flows with respect to VSS. R2 is a path through which positive pulse ESD flows with respect to VSS. The prior art shown in FIG. 5 is described in Patent Document 1, for example.

FIG. 6 is a diagram showing another conventional ESD protection circuit. The ESD protection circuit shown in FIG. 6 does not have the diode 54 shown in FIG. 5, and instead uses the capacitive element C, the resistive element R, and the MOS transistor 61 to flow an ESD surge.
When a high-pulse ESD is input, the MOS transistor 61 causes a snapback phenomenon to flow a surge current, thereby protecting the internal circuit. At this time, the capacitive element C and the resistance element R apply a voltage to the gate of the MOS transistor 61 when ESD is input, so that snapback easily occurs.

  The ESD circuit shown in FIG. 6 is different from the ESD circuit shown in FIG. 5 in that the diode 54 is provided for reasons such as a voltage higher than the power supply voltage is applied, the distance between the power supplies to the protection circuit is long, and the wiring resistance is high. It can be applied when the effect cannot be expected.

JP 2006-13446 A

  However, a high-speed signal may be input to the internal circuit. Therefore, the ESD protection circuit of FIG. 6 does not increase the gate voltage of the MOS transistor 61 with respect to the pulse of the signal to be input, and applies the gate voltage only when the ESD pulse is input. Therefore, it is required to flow a surge current. Such an operation is made possible by increasing the time constant determined by the capacitance and resistance value of the capacitive element C and the resistive element R for signal pulses and large for ESD.

However, in recent years, semiconductor devices have been required to have higher reliability against ESD. In addition, since a high-speed signal should be input to the internal circuit without loss, it is difficult to design the capacitive element C and the resistive element R so that only the ESD surge flows through the protection circuit.
The present invention has been made in view of these points, and provides a protection circuit that can reliably protect an internal circuit from ESD and that can input a signal to be input to the internal circuit without loss. With the goal.

In order to solve the above problems, the protection circuit according to claim 1 of the present invention receives power from at least a first power source (for example, VDD) and a second power source (for example, VSS) to provide an internal circuit (for example, in FIG. 1). A first MOS connected between the external power source (for example, external terminal 103 shown in FIG. 1) connected to the internal circuit and the second power source. Power is supplied by a transistor (for example, the MOS transistor 104 shown in FIG. 1), a second MOS transistor (for example, the MOS transistor 105 shown in FIG. 1) connected to the gate terminal of the first MOS transistor, and the first power source. If not, the first MOS transistor is controlled so that the current input from the external terminal flows to the second power source, and power is supplied by the first power source. If it is fed, characterized in that it comprises a a (delay circuit shown in for example FIG. 1) transistor control circuit, wherein the first 1MOS transistor controls said first 2MOS transistor so as to turn off.
The protection circuit according to a second aspect of the present invention is the delay circuit according to the first aspect, wherein the transistor control circuit turns on the second MOS transistor after the timing at which the first MOS transistor starts a snapback operation. It is characterized by including.

  A protection circuit according to a third aspect of the present invention is the protection circuit according to the first or second aspect, wherein the transistor control circuit is connected to a gate terminal of the first MOS transistor (for example, shown in FIG. 1). A capacitor element 109) and a first resistor element (for example, the resistor element 110 shown in FIG. 1), and a second capacitor element (for example, the capacitor element 108 shown in FIG. 1) connected to the gate terminal of the second MOS transistor. 2 resistance elements (for example, the resistance element 107 shown in FIG. 1), the first capacitance element is connected between the external terminal and the gate terminal of the first MOS transistor, and the first resistance element is The first MOS transistor is connected between the gate terminal of the first MOS transistor and the second power supply, and the drain of the second MOS transistor is connected to the gate terminal of the first MOS transistor. The second resistive element is connected between the gate terminal of the second MOS transistor and the first power supply, and the second capacitive element is connected between the gate terminal of the second MOS transistor and the second power supply. It is characterized by.

  A protection circuit according to a fourth aspect of the present invention is the protection circuit according to the first aspect, wherein the transistor control circuit (for example, the control circuit 301 shown in FIG. 3) outputs a digital signal to the second MOS transistor. The second MOS transistor is turned on after the timing at which the 1MOS transistor starts the snapback operation.

According to invention of Claim 1, when electric power is not supplied, the electric current input from the external terminal connected to the internal circuit can be sent to a 2nd power supply. For this reason, when electrostatic discharge is input from the external terminal, this electrostatic discharge can be passed to the power supply to protect the internal circuit. In addition, when power is supplied, it is possible to prevent a current input from the external terminal from flowing to the second power source, and thus a signal to be input to the internal circuit can be efficiently input to the internal circuit. .
According to the second aspect of the present invention, the delay circuit of the transistor control circuit can turn on the second MOS transistor after the timing at which the first MOS transistor starts the snapback operation. It is possible to protect the internal circuit by supplying the discharged electrostatic discharge to the power source.

According to the invention of claim 3, the first capacitor element is connected between the external terminal and the gate terminal of the first MOS transistor, the first resistor element is connected to the connection node between the first capacitor element and the gate terminal, and the second power source. Between the gate terminal of the second MOS transistor and the first power supply. The connection node of the connection and the second power supply are connected to the connection node. A transistor control circuit can be configured by connecting a second capacitor between the first and second capacitors. Therefore, the protection circuit of claim 1 can be realized with a relatively simple configuration.
According to the invention of claim 4, the transistor control circuit outputs a digital signal to the second MOS transistor and turns on the second MOS transistor after the timing at which the first MOS transistor starts the snapback operation. Can be further simplified.

It is a circuit diagram for demonstrating the protection circuit of one Embodiment of this invention. It is a figure for demonstrating operation | movement of the protection circuit shown in FIG. It is a circuit diagram for demonstrating the modification of embodiment of this invention. It is a circuit diagram for demonstrating the other modification of embodiment of this invention. It is a circuit diagram for demonstrating the conventional ESD protection circuit. It is a circuit diagram for demonstrating the other conventional ESD protection circuit.

Hereinafter, an embodiment of a protection circuit according to the present invention will be described with reference to the drawings.
(Constitution)
FIG. 1 is a circuit diagram for explaining a protection circuit according to an embodiment of the present invention. FIG. 1 shows an internal circuit 101 to be protected, a protection element 102 for protecting the internal circuit 101, and a protection circuit 100 of the present embodiment that protects the internal circuit 101 together with the protection element 102. Yes.
The protection circuit 100 is an ESD protection circuit that receives power from VDD and VSS (GND in this embodiment) and protects the internal circuit 101. The protection circuit 100 includes a MOS transistor 104 connected between the external terminal 103 connected to the internal circuit 101 and GND, a MOS transistor 105 connected to the gate terminal g1 of the MOS transistor 104, a MOS transistor 104, A transistor control circuit for controlling 105 is included.

The transistor control circuit controls the MOS transistor 104 so that the current input from the external terminal 103 connected to the internal circuit 101 flows to GND when the power is not supplied by VDD, and the power is supplied by VDD. If so, the MOS transistor 105 is controlled so that the current input from the external terminal 103 is prevented from flowing to the GND by the MOS transistor 104.
Further, the transistor control circuit of the present embodiment includes a delay circuit 106 that turns on the MOS transistor 105 after the timing at which the MOS transistor 104 starts the snapback operation in order to realize such control. The delay circuit 106 according to the present embodiment includes a resistance element 107 and a capacitance element 108, and functions as a low-pass filter having a large time constant.

  More specifically, the delay circuit 106 of the present embodiment is configured by a capacitive element 109 connected to the gate terminal g1 of the MOS transistor 104, a resistance element 110, and a delay circuit 106 connected to the gate terminal g2 of the MOS transistor 105. Has been. The capacitive element 109 is connected between the external terminal 103 and the gate terminal g1 of the MOS transistor 104, and the resistance element 110 is connected between the gate terminal of the MOS transistor 104 and GND. A connection point between the resistance element 110 and the gate terminal of the MOS transistor 104 is hereinafter referred to as a connection point p1.

The gate terminal of the MOS transistor 104 is connected to the drain d2 of the MOS transistor 105, and the resistance element 107 is connected between the gate terminal g2 of the MOS transistor 105 and VDD. Further, a capacitive element 108 is connected between the gate terminal g2 of the MOS transistor 105 and GND. The point p2 on the connection node of this connection is hereinafter referred to as a connection point p2.
Furthermore, the protection circuit shown in FIG. 1 is provided with a protection element 102 and diodes 111 and 112 for flowing an ESD current through the protection element 102.

Here, ESD assumed in the present embodiment will be described.
The protection circuit 100 according to the present embodiment protects an internal circuit from an ESD surge generated in a process of mounting a semiconductor device on a printed circuit board or a process of testing the semiconductor device. In the mounting and testing processes, semiconductor device packages and apparatus jigs are charged by frictional static electricity. When the static electricity is charged, the potential of the semiconductor device is increased, and the static electricity is discharged to other semiconductor devices. When the semiconductor device is in a single state, the discharged static electricity cannot be flowed elsewhere, so that there is a high possibility that the internal circuit of the semiconductor device is destroyed.

On the other hand, when a semiconductor device is mounted and incorporated in a device and power is supplied, the impedance of the power source is low. For this reason, ESD can flow to the outside in the same way on both the power supply (VDD and VSS) paths.
In the present embodiment, an internal circuit is protected from ESD flowing into a semiconductor device to which power is not supplied, and the protection circuit is controlled so that a high-speed signal is efficiently input to the internal circuit.

(Operation)
Hereinafter, the operation of the protection circuit 100 of the present embodiment will be described. Here, the operation will be described separately for the case where VDD is supplied to the protection circuit 100 and the case where VDD is not supplied.
FIG. 2 illustrates the operation of the protection circuit 100 according to the present embodiment. FIG. 2 illustrates high-speed signals (hereinafter referred to as ESD) for a plurality of nodes of the circuit illustrated in FIG. It is a figure which shows the change of an electric potential when (it is also described with a pulse) is input. FIG. 2A shows the potential of the external terminal 103 shown in FIG. 2 (b) shows the potential of the node of VDD shown in FIG. 1, FIG. 2 (c) shows the potential at the connection point p2, FIG. 2 (d) shows the potential at the connection point p1, and FIG. ) Indicates the current flowing through the MOS transistor 104, respectively.

2A to 2E show a state where VDD is not supplied to the protection circuit 100. When VDD is not supplied to the protection circuit 100, the MOS transistor 105 is assumed to be off.
When the ESD pulse is input to the external terminal 103, the potential of the external terminal rises in proportion to the time as shown by the straight line indicated by the broken line in FIG. However, in the circuit shown in FIG. 1, the ESD pulse that enters the external terminal 103 is applied to the drain of the MOS transistor 104. As a result, a current flows through the drain and breakdown occurs between the drain and the substrate (not shown).

  When the current due to breakdown increases, current is injected into the source and reaches the drain, and the MOS transistor 104 performs a bipolar operation. The transition of the MOS transistor 104 to the bipolar operation is referred to as a snapback operation in this specification. In addition, since the technique which protects a device from ESD using a snapback phenomenon is a well-known thing, further description is abbreviate | omitted.

  Due to the snapback of the MOS transistor 104, the potential of the external terminal does not exceed a certain value as shown by the solid line in FIG. For this reason, in this embodiment, the ESD pulse can be prevented from flowing into the internal circuit 101. Note that the MOS transistor 105 operates so as to easily cause snapback of the MOS transistor 104. The specific contents of the operation will be described later with reference to FIG.

Further, the ESD pulse is caused to flow to the protection element 102 by the diode 111. Therefore, as shown in FIG. 2B, the potential of the VDD node does not exceed a certain value.
Further, the ESD pulse flows to a node downstream from the protection element 102. At this time, the potential at the connection point p <b> 2 rises with a delay by the delay circuit 106. FIG. 2C shows that the potential at the connection point p2 rises at a timing t2 later than the timing t1 at which the potential at the node of the external terminal 103 or VDD starts to rise.

  As the potential at the connection point p2 rises, a voltage is applied to the gate terminal g2 of the MOS transistor 105, and the MOS transistor 105 is turned on. However, in this embodiment, as described above, the potential at the connection point p2 rises later than the potential rise at the VDD node. Therefore, as shown in FIG. 2D, before the potential at the connection point p2 rises and the MOS transistor 105 is turned on, charges are accumulated in the capacitor 109, and the potential at the connection point p1 rises. The snapback phenomenon of the MOS transistor 104 occurs due to the potential rise at the connection point p1.

The MOS transistor 104 enters a snapback operation, and the current generated by the ESD pulse flows to the GND via the MOS transistor 104 as shown in FIG. As a result, it is possible to avoid the ESD pulse from entering the internal circuit 101 and damaging the internal circuit 101.
With the above operation, it can be said that the delay circuit 106 of this embodiment turns on the MOS transistor 105 after the timing at which the MOS transistor 104 starts snapback.

When VDD is supplied to the protection circuit When VDD is supplied to the protection circuit 100, the MOS transistor 105 is on. For this reason, the potential of the connection point p1 does not increase, and the snap back of the MOS transistor 104 does not occur. Therefore, when a high-speed signal to be input by the internal circuit 101 (hereinafter also referred to as a high-speed pulse) is input, the high-speed pulse is not lost by the MOS transistor 104, and a signal having a high amplitude is efficiently input to the internal circuit 101. be able to.

In addition, an ESD pulse may be input while VDD is supplied to the protection circuit 100. At this time, the ESD pulse flows to VDD through the protection diode 111 and mainly flows through an external power source having a low impedance.
Note that the present embodiment is not limited to the configuration described above. For example, in the present embodiment described above, the protection element 102 is provided, but the protection element 102 is not an essential component of the protection circuit 100 of the present embodiment.

  However, since ordinary power supply terminals are also external terminals, they are often provided as protection. Even in this case, if the resistance value is 5 ohms when the distance to the protection element 102 is long and the wiring resistance is large, the current value of the ESD pulse is generally 1 to 2 A, and 5 V to 10 V is the protection value of the protection element 102. The voltage added to the voltage is generated at the PAD 103, that is, the input terminal of the internal circuit. In the case of the protection circuit 100, the voltage of the PAD 103 is generated by the MOS transistor 104 as can be seen from the explanation when VDD is not supplied. Therefore, the internal circuit 101 can be reliably prevented from being damaged.

(Modification)
・ Modification 1
(Constitution)
FIG. 3 is a diagram for explaining a modification of the above-described embodiment. In FIG. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and the description of the components will be partially omitted.
As shown in the figure, the protection circuit of the first modification is different from the first embodiment shown in FIG. 1 in that there are two VDD power supply systems, VDD1 and VDD2. In the example shown in FIG. 3, it is assumed that VDD1 is an analog power supply and VDD2 is a digital power supply. In addition, an ESD pulse is applied to the circuit shown in FIG. 3 with respect to GND.

(Operation)
In the protection circuit shown in FIG. 3, the digital power supply VDD2 turns off the MOS transistor 105 when power is not supplied to the protection circuit, and turns on the MOS transistor 105 when power is not supplied to the protection circuit. A control circuit 301 is provided.
In this way, when power is not supplied to the protection circuit, the potential at the connection point p1 rises, and the MOS transistor 104 prompts the snapback operation to cause the ESD pulse to flow to GND. Further, when power is supplied to the protection circuit, the potential at the connection point p1 can be maintained at a constant value. That is, in the protection circuit illustrated in FIG. 3, when the power is not supplied by VDD, the control circuit 301 controls the MOS transistor 105 so that the current input from the external terminal 103 flows to the GND, and also by VDD. When power is supplied, the transistor functions as a transistor control circuit that controls the MOS transistor 104 so that the current input from the external terminal 103 is prevented from flowing to the GND by the MOS transistor 105.

・ Modification 2
(Constitution)
FIG. 4 is a diagram for explaining the protection circuit according to the second modification of the first embodiment. The protection circuit shown in FIG. 4 is a circuit in which signals are differentially input from the external terminals 103 a and 103 b and differentially output to the internal circuit 101. Capacitance elements 402a and 402b are connected in series between the external terminals 103a and 103b, and a MOS transistor 401a, a point p3 (hereinafter referred to as a connection point p3) on a connection node between the capacitance elements 402a and 402b. The gate terminals g3 and g4 of 401b are connected.
A resistance element 403 and a MOS transistor 404 are further connected in parallel to the connection point p3. The gate terminal g5 of the MOS transistor 404 is connected to the power supply VDD, and the MOS transistor 404 is turned off when power is not supplied from VDD, and the MOS transistor 404 is turned on when power is supplied.

(Operation)
In the configuration shown in FIG. 4, when high-speed pulses having phases different from each other by 180 degrees are input from the external terminals 103a and 103b, the potential change of the connection point p3 caused by the capacitive element 402a and the connection point p3 caused by the capacitive element 402b. The change in potential cancels out. Therefore, the potential at the connection point p3 hardly increases and the gate potentials of the MOS transistors 401a and 401b do not increase.
On the other hand, it is unlikely that the ESD pulse is input from the external terminals 103a and 103b with the phase being 180 degrees out of phase simultaneously. For this reason, when an ESD pulse is input, the potential of the connection point p3 rises, and snapback of the MOS transistors 401a and 401b easily occurs.

Further, in the circuit shown in FIG. 4, as described above, the MOS transistor 404 is connected to the connection point p3, and when the MOS transistor 404 is in the ON state, the connection point p3 and GND have the same potential. The gate terminal g5 of the MOS transistor 404 is connected to VDD. For this reason, when power is supplied to the protection circuit, the MOS transistor 404 is turned on, and the potential at the connection point p3 can be reliably prevented from rising.
In the circuit shown in FIG. 4, the MOS transistor 404 is turned off when power is not supplied to the protection circuit. Therefore, when the ESD pulse is input, the potential at the connection point p3 rises, and the MOS transistors 401a and 401b can be snapped back to protect the internal circuit 101.

  The protection circuit of the present invention described above can be applied to any configuration as long as it is a protection circuit that protects an internal circuit that receives and processes an analog AC signal. Particularly, it is suitable for a semiconductor device to which electrostatic discharge can be input in a test process or the like.

100 Protection circuit 101 Internal circuit 102 Protection element 103, 103a, 103b External terminals 104, 105, 401a, 401b, 404 MOS transistor 106 Delay circuit 107 Resistance element 108, 109 Capacitance element 110 Resistance element 111 Diode 301 Control circuit 402a Capacitance element 402b Capacitance element 403 Resistance element

Claims (4)

  1. A protection circuit that receives power from at least a first power supply and a second power supply to protect an internal circuit;
    A first MOS transistor connected between an external terminal connected to the internal circuit and the second power supply;
    A second MOS transistor connected to control the voltage of the gate terminal of the first MOS transistor;
    When power is not supplied from the first power source, the first MOS transistor is controlled so that a current input from the external terminal flows to the second power source, and power is supplied from the first power source. And a transistor control circuit for controlling the second MOS transistor so that the first MOS transistor is turned off.
  2. The transistor control circuit is
    2. The protection circuit according to claim 1, further comprising a delay circuit that turns on the second MOS transistor after a timing at which the first MOS transistor starts a snapback operation.
  3. The transistor control circuit is
    A first capacitance element and a first resistance element connected to a gate terminal of the first MOS transistor;
    A second capacitance element and a second resistance element connected to the gate terminal of the second MOS transistor;
    Including
    The first capacitive element is connected between the external terminal and a gate terminal of the first MOS transistor, and the first resistance element is connected between a gate terminal of the first MOS transistor and the second power supply. The drain of the second MOS transistor is connected to the gate terminal of the first MOS transistor, the second resistance element is connected between the gate terminal of the second MOS transistor and the first power source, and the gate of the second MOS transistor. The protection circuit according to claim 1, wherein the second capacitive element is connected between a terminal and the second power source.
  4. The transistor control circuit is
    2. The protection circuit according to claim 1, wherein a digital signal is output to the second MOS transistor, and the second MOS transistor is turned on after a timing at which the first MOS transistor starts a snapback operation.
JP2009185544A 2009-08-10 2009-08-10 Protective circuit Pending JP2011040520A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014063854A (en) * 2012-09-20 2014-04-10 Toshiba Corp Semiconductor circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269437A (en) * 1999-03-18 2000-09-29 Hyundai Electronics Ind Co Ltd Electrostatic discharge protecting circuit
JP2005093496A (en) * 2003-09-12 2005-04-07 Toshiba Corp Semiconductor integrated circuit device
JP2005123570A (en) * 2003-10-15 2005-05-12 Realtek Semiconductor Corp Static discharge protective circuit
JP2005235947A (en) * 2004-02-18 2005-09-02 Fujitsu Ltd Electrostatic discharge protective circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269437A (en) * 1999-03-18 2000-09-29 Hyundai Electronics Ind Co Ltd Electrostatic discharge protecting circuit
JP2005093496A (en) * 2003-09-12 2005-04-07 Toshiba Corp Semiconductor integrated circuit device
JP2005123570A (en) * 2003-10-15 2005-05-12 Realtek Semiconductor Corp Static discharge protective circuit
JP2005235947A (en) * 2004-02-18 2005-09-02 Fujitsu Ltd Electrostatic discharge protective circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014063854A (en) * 2012-09-20 2014-04-10 Toshiba Corp Semiconductor circuit

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