JP2011038781A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2011038781A
JP2011038781A JP2009183453A JP2009183453A JP2011038781A JP 2011038781 A JP2011038781 A JP 2011038781A JP 2009183453 A JP2009183453 A JP 2009183453A JP 2009183453 A JP2009183453 A JP 2009183453A JP 2011038781 A JP2011038781 A JP 2011038781A
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insulating film
semiconductor device
electrode
semiconductor substrate
semiconductor
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Hironobu Kawachi
宏信 河内
Haruhiko Nishikage
治彦 西影
Yushin Fujita
有真 藤田
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Rohm Co Ltd
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Rohm Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of stabilizing electric potential of a substrate without complicating a structure, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate 10 of a single-crystal structure on whose upper surface a recess 100 is formed; a beam-shaped movable part 20 which includes a movable electrode 21 disposed in the recess 100 and having a lower insulating film 50 disposed on a lower surface, and is fixed to the semiconductor substrate 10 at a position spaced apart from the movable electrode 21; a beam-shaped stationary electrode 30 disposed in the recess 100 so as to face the movable electrode 21 and fixed to the semiconductor substrate 10; an insulating isolation film 40 which is disposed between the movable and stationary electrodes 20, 30 and the semiconductor substrate 10, and electrically isolates the movable and stationary electrodes 21, 30 from the substrate 10; and a contact electrode 63 connected to the substrate 10. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、梁型の可動部を備える半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device having a beam-shaped movable portion and a method for manufacturing the semiconductor device.

外部から加えられた力(以下において、「外力」という。)に応じて変位する可動部を備えるMEMS(Micro Electro Mechanical System)装置が、加速度センサやジャイロセンサ等の物理量を検知するセンサに使用されている。例えば、外力により振動する可動電極と固定電極間の静電容量の変化を検知して加速度を検出する静電容量型加速度センサ等が実用化されている。   2. Description of the Related Art A MEMS (Micro Electro Mechanical System) device having a movable portion that is displaced according to an externally applied force (hereinafter referred to as “external force”) is used as a sensor for detecting a physical quantity such as an acceleration sensor or a gyro sensor. ing. For example, a capacitive acceleration sensor that detects acceleration by detecting a change in capacitance between a movable electrode and a fixed electrode that vibrates due to an external force has been put to practical use.

梁型の可動部を形成するために、半導体基板上に絶縁膜層と半導体層を積層したSOI基板等の積層体が使用されている(例えば、特許文献1参照。)。半導体層の一部が可動部として使用され、絶縁膜層は犠牲層として使用される。   In order to form a beam-shaped movable portion, a stacked body such as an SOI substrate in which an insulating film layer and a semiconductor layer are stacked on a semiconductor substrate is used (for example, see Patent Document 1). A part of the semiconductor layer is used as a movable part, and the insulating film layer is used as a sacrificial layer.

特開2005−342808号公報JP-A-2005-342808

しかしながら、微小な静電容量の変化を検知するセンサは、ノイズの影響により誤動作しやすい。このため、基板の電位を安定させる必要があり、例えば基板を接地する。したがって、半導体基板上に絶縁膜層と半導体層を積層した積層体を使用した場合、半導体基板と半導体層の2箇所を接地する必要があり、半導体装置の上側と下側に接地用の電極を配置しなければならない。その結果、半導体装置の構造が複雑になるという問題があった。   However, a sensor that detects a minute change in electrostatic capacitance is likely to malfunction due to the influence of noise. For this reason, it is necessary to stabilize the potential of the substrate. For example, the substrate is grounded. Therefore, when a laminated body in which an insulating film layer and a semiconductor layer are stacked on a semiconductor substrate is used, it is necessary to ground the semiconductor substrate and the semiconductor layer at two locations, and grounding electrodes are provided on the upper side and the lower side of the semiconductor device. Must be placed. As a result, there is a problem that the structure of the semiconductor device is complicated.

上記問題点を鑑み、本発明は、構造を複雑にすることなく、基板の電位を安定にすることが可能な半導体装置及び半導体装置の製造方法を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can stabilize the potential of the substrate without complicating the structure.

本発明の一態様によれば、(イ)上面に凹部が形成された、単一の結晶構造体の半導体基板と、(ロ)凹部内に配置され、下面に下面絶縁膜が配置された可動電極を有し、可動電極より離間した位置において半導体基板に固定された梁型の可動部と、(ハ)可動電極に対向して凹部内に配置され、半導体基板に固定された梁型の固定電極と、(ニ)可動部及び固定電極と半導体基板との間に配置され、可動電極及び固定電極と半導体基板とを電気的に分離する分離絶縁膜と、(ホ)半導体基板に接続するコンタクト電極とを備える半導体装置が提供される。   According to one aspect of the present invention, (a) a semiconductor substrate having a single crystal structure having a recess formed on the upper surface, and (b) a movable substrate disposed in the recess and having a lower surface insulating film disposed on the lower surface. A beam-type movable part having an electrode and fixed to the semiconductor substrate at a position away from the movable electrode, and (c) a beam-type fixed part disposed in the recess facing the movable electrode and fixed to the semiconductor substrate. (D) an isolation insulating film that is disposed between the movable part and the fixed electrode and the semiconductor substrate and electrically separates the movable electrode and the fixed electrode from the semiconductor substrate; and (e) a contact connected to the semiconductor substrate. A semiconductor device comprising an electrode is provided.

本発明の他の態様によれば、可動電極を有する可動部と、可動電極に対向して半導体基板に固定された固定電極とを有する半導体装置の製造方法であって、(イ)半導体基板の上面の一部をエッチングして、第1の凹部を形成するステップと、(ロ)第1の凹部の側壁上に分離絶縁膜、底面上に下面絶縁膜をそれぞれ形成するステップと、(ハ)分離絶縁膜及び下面絶縁膜上に埋め込み半導体膜を形成して、第1の凹部を埋め込み半導体膜で埋め込むステップと、(ニ)埋め込み半導体膜の一部をエッチングして、可動部及び固定電極の側面が露出する側面溝を形成するステップと、(ホ)側面溝に露出した可動部と固定電極の側面に側面絶縁膜を形成するステップと、(ヘ)側面溝の底面に露出した下面絶縁膜を除去するステップと、(ト)側面絶縁膜及び下面絶縁膜をマスクに用いたエッチングによって半導体基板の上部の一部に第2の凹部を形成して、可動部及び固定電極の下面を半導体基板から分離するステップとを含む半導体装置の製造方法が提供される。   According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a movable part having a movable electrode and a fixed electrode fixed to the semiconductor substrate so as to face the movable electrode, and (B) forming a first recess by etching a part of the upper surface; (b) forming an isolation insulating film on the sidewall of the first recess and a lower insulating film on the bottom; Forming a buried semiconductor film on the isolation insulating film and the lower insulating film and filling the first recess with the buried semiconductor film; and (d) etching a part of the buried semiconductor film to form the movable portion and the fixed electrode. A step of forming a side surface groove in which the side surface is exposed; (e) a step of forming a side surface insulating film on the side surface of the movable portion and the fixed electrode exposed in the side surface groove; and (f) a lower surface insulating film exposed on the bottom surface of the side surface groove. And steps to remove ( Forming a second recess in a part of the upper portion of the semiconductor substrate by etching using the side surface insulating film and the lower surface insulating film as a mask, and separating the lower surface of the movable portion and the fixed electrode from the semiconductor substrate. A manufacturing method is provided.

本発明によれば、構造を複雑にすることなく、基板の電位を安定にすることが可能な半導体装置及び半導体装置の製造方法を提供できる。   According to the present invention, it is possible to provide a semiconductor device and a semiconductor device manufacturing method capable of stabilizing the potential of the substrate without complicating the structure.

本発明の実施形態に係る半導体装置の構成を示す模式的な上面図である。It is a typical top view showing the composition of the semiconductor device concerning the embodiment of the present invention. 図1に示した半導体装置のII−II方向に沿った断面図である。It is sectional drawing along the II-II direction of the semiconductor device shown in FIG. 図1に示した半導体装置のIII−III方向に沿った断面図である。FIG. 3 is a cross-sectional view taken along the III-III direction of the semiconductor device shown in FIG. 1. 図1に示した半導体装置のIV−IV方向に沿った断面図である。FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. 1 along the IV-IV direction. 図1に示した半導体装置の領域Aの斜視図である。FIG. 2 is a perspective view of a region A of the semiconductor device shown in FIG. 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その1)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その2)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 2). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その3)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 3). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その4)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 4). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その5)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 5). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その6)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 6). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その7)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 7). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その8)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 8). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その9)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 9). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その10)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 10). 本発明の実施形態に係る半導体装置の製造方法を説明するための工程図である(その11)。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 11). 本発明の実施形態に係る半導体装置に蓋を配置した例を示す模式的な断面図である。It is typical sectional drawing which shows the example which has arrange | positioned the cover to the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の基板の例を示す模式的な断面図である。It is typical sectional drawing which shows the example of the board | substrate of the semiconductor device which concerns on embodiment of this invention. 関連技術に係る半導体装置の可動部の形状を示す模式的な断面図である。It is typical sectional drawing which shows the shape of the movable part of the semiconductor device which concerns on related technology.

次に、図面を参照して、本発明の実施形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。   Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

又、以下に示す実施形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。   The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, and arrangement of components. Etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

本発明の実施形態における半導体装置は、図1に示すように、上面に凹部100が形成された、単一の結晶構造体の半導体基板10と、凹部100内に配置され、下面に下面絶縁膜50が配置された可動電極21を有し、可動電極21より離間した位置において半導体基板10に固定された梁型の可動部20と、可動電極21に対向して凹部100内に配置され、半導体基板10に固定された梁型の固定電極30と、可動部20及び固定電極30と半導体基板10との間に配置され、可動電極21及び固定電極30と半導体基板10とを電気的に分離する分離絶縁膜40と、半導体基板10に接続するコンタクト電極63とを備える。   As shown in FIG. 1, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate 10 having a single crystal structure having a recess 100 formed on the upper surface, and a lower insulating film disposed on the lower surface. 50, a movable electrode 20 having a beam shape, which is fixed to the semiconductor substrate 10 at a position spaced from the movable electrode 21, and disposed in the recess 100 so as to face the movable electrode 21, A beam-shaped fixed electrode 30 fixed to the substrate 10 and the movable portion 20 and the fixed electrode 30 are disposed between the semiconductor substrate 10 and electrically isolate the movable electrode 21 and the fixed electrode 30 from the semiconductor substrate 10. An isolation insulating film 40 and a contact electrode 63 connected to the semiconductor substrate 10 are provided.

図2、図3に示すように、凹部100は、可動部20及び固定電極30と同一の高さにあり、周囲を分離絶縁膜40で囲まれた第1の領域と、第1の領域の下方にあり、半導体基板10が側面に露出した第2の領域からなる。詳細は後述するが、第1の領域は、側面溝500として形成される領域であり、第2の領域は、半導体基板10を等方性エッチングして形成される第2の凹部120である。   As shown in FIGS. 2 and 3, the recess 100 is at the same height as the movable portion 20 and the fixed electrode 30, and the first region surrounded by the isolation insulating film 40 and the first region It consists of the 2nd area | region which is below and the semiconductor substrate 10 was exposed to the side surface. Although details will be described later, the first region is a region formed as the side surface groove 500, and the second region is the second recess 120 formed by isotropic etching of the semiconductor substrate 10.

図2、図3、図5に示すように、分離絶縁膜40は凹部100の側壁上に形成されており、分離絶縁膜40は凹部100を囲むように配置されている。   As shown in FIGS. 2, 3, and 5, the isolation insulating film 40 is formed on the sidewall of the recess 100, and the isolation insulating film 40 is disposed so as to surround the recess 100.

可動部20は、図1に示すように、中心ストライプ部22、中心ストライプ部22から中心ストライプ部22が延伸する方向と垂直方向に延伸する複数の可動電極21、及び中心ストライプ部と半導体基板10を接続するバネ部23とを備える、フィッシュボーン構造の梁型振動子である。バネ部23は、分離絶縁膜40を介して半導体基板10に固定されている。   As shown in FIG. 1, the movable portion 20 includes a central stripe portion 22, a plurality of movable electrodes 21 extending in a direction perpendicular to the direction in which the central stripe portion 22 extends from the central stripe portion 22, and the central stripe portion and the semiconductor substrate 10. Is a beam-type vibrator having a fishbone structure. The spring portion 23 is fixed to the semiconductor substrate 10 via the isolation insulating film 40.

図2に示すように、可動部20の下面に下面絶縁膜50が配置されている。更に、可動部20の側面に側面絶縁膜52、上面に上面絶縁膜54が配置され、可動部20の周囲全体が絶縁膜で覆われている。   As shown in FIG. 2, a lower surface insulating film 50 is disposed on the lower surface of the movable portion 20. Further, a side insulating film 52 is disposed on the side surface of the movable portion 20, and an upper surface insulating film 54 is disposed on the upper surface, and the entire periphery of the movable portion 20 is covered with the insulating film.

固定電極30は、凹部100を囲む周辺部において半導体基板10に固定された固定端と凹部100内に延在する自由端とを有する梁型振動子である。固定電極30は、図1及び図3に示すように、分離絶縁膜40を介して半導体基板10に固定されている。図2、図3に示したように、固定電極30の下面に下面絶縁膜50、側面に側面絶縁膜52、上面に上面絶縁膜54がそれぞれ配置されて、固定電極30の周囲全体が絶縁膜で覆われている。   The fixed electrode 30 is a beam-type vibrator having a fixed end fixed to the semiconductor substrate 10 and a free end extending into the recess 100 at a peripheral portion surrounding the recess 100. As shown in FIGS. 1 and 3, the fixed electrode 30 is fixed to the semiconductor substrate 10 via an isolation insulating film 40. As shown in FIGS. 2 and 3, a lower insulating film 50 is disposed on the lower surface of the fixed electrode 30, a side insulating film 52 is disposed on the side surface, and an upper insulating film 54 is disposed on the upper surface, so that the entire periphery of the fixed electrode 30 is an insulating film. Covered with.

上記に説明したように、可動部20及び固定電極30は分離絶縁膜40を介して半導体基板10に固定されている。分離絶縁膜40により、可動電極21と固定電極30とは電気的に分離される。したがって、可動電極21と固定電極30がキャパシタプレートとして機能する。   As described above, the movable portion 20 and the fixed electrode 30 are fixed to the semiconductor substrate 10 via the isolation insulating film 40. The movable electrode 21 and the fixed electrode 30 are electrically separated by the separation insulating film 40. Therefore, the movable electrode 21 and the fixed electrode 30 function as a capacitor plate.

半導体装置に外部から加えられた外力に応じて可動部20の位置は変化し、可動電極21と固定電極30間の距離が変化する。このため、可動電極21と固定電極30間に電圧を印加した状態で半導体装置に外力が加わると、可動電極21と固定電極30間の距離の変化は、静電容量の変化として検知される。半導体装置は、検知された静電容量の変化を検出信号で信号処理回路(図示略)に伝達する。信号処理回路は、検出信号を処理して半導体装置に生じた加速度を検出する。つまり、図1に示した半導体装置は、可動電極21と固定電極30間の静電容量の変化に基づいて加速度を検出する静電容量型加速度センサの一部である。信号処理回路は、半導体装置と同一チップ上に配置してもよいし、半導体装置が配置されたチップと異なるチップ上に配置してもよい。   The position of the movable portion 20 changes according to the external force applied to the semiconductor device from the outside, and the distance between the movable electrode 21 and the fixed electrode 30 changes. Therefore, when an external force is applied to the semiconductor device with a voltage applied between the movable electrode 21 and the fixed electrode 30, a change in the distance between the movable electrode 21 and the fixed electrode 30 is detected as a change in capacitance. The semiconductor device transmits the detected change in capacitance to a signal processing circuit (not shown) as a detection signal. The signal processing circuit processes the detection signal to detect acceleration generated in the semiconductor device. That is, the semiconductor device shown in FIG. 1 is a part of a capacitance type acceleration sensor that detects acceleration based on a change in capacitance between the movable electrode 21 and the fixed electrode 30. The signal processing circuit may be arranged on the same chip as the semiconductor device, or may be arranged on a different chip from the chip on which the semiconductor device is arranged.

図1に示したように、可撓性を有するバネ形状のバネ部23によって可動部20と半導体基板10とが接続され、可動部20を振動しやすくしている。これにより、半導体装置の検出感度が向上する。   As shown in FIG. 1, the movable portion 20 and the semiconductor substrate 10 are connected by a spring-shaped spring portion 23 having flexibility, so that the movable portion 20 is easily vibrated. Thereby, the detection sensitivity of the semiconductor device is improved.

図1に示した半導体装置では、可動電極21の電圧値を信号処理回路に伝達するための電極配線61は、上面絶縁膜54の一部を除去して形成した開口部610において可動部20と接続する。一方、固定電極30の電圧値を信号処理回路に伝達するための電極配線62は、上面絶縁膜54の一部を除去して形成した開口部620において固定電極30と接続する。   In the semiconductor device shown in FIG. 1, the electrode wiring 61 for transmitting the voltage value of the movable electrode 21 to the signal processing circuit is the same as the movable portion 20 in the opening 610 formed by removing a part of the upper surface insulating film 54. Connecting. On the other hand, the electrode wiring 62 for transmitting the voltage value of the fixed electrode 30 to the signal processing circuit is connected to the fixed electrode 30 in the opening 620 formed by removing a part of the upper surface insulating film 54.

図1に示すように、可動電極21と固定電極30は交差指状に配置されている。これにより、可動電極21と固定電極30の互いに対向する面積が増大し、可動電極21と固定電極30間の静電容量が増大する。したがって、高い感度で加速度を検出できる。可動部20と固定電極30とが対向する領域における可動部20及び固定電極30の幅は、例えば3μm〜10μm程度であり、可動部20と固定電極30間の距離は、例えば1μm〜2μm程度である。   As shown in FIG. 1, the movable electrode 21 and the fixed electrode 30 are arranged in a crossed finger shape. Thereby, the area where the movable electrode 21 and the fixed electrode 30 face each other increases, and the capacitance between the movable electrode 21 and the fixed electrode 30 increases. Therefore, acceleration can be detected with high sensitivity. The width of the movable part 20 and the fixed electrode 30 in the region where the movable part 20 and the fixed electrode 30 face each other is, for example, about 3 μm to 10 μm, and the distance between the movable part 20 and the fixed electrode 30 is, for example, about 1 μm to 2 μm. is there.

図1に示すように、半導体基板10の凹部100を囲む周辺領域上にコンタクト電極63が配置されている。図4に示すように、半導体基板10上に形成された上面絶縁膜54及び表面絶縁膜15に形成した開口部630において、コンタクト電極63は半導体基板10に接続している。このため、半導体装置の上面に配置されたコンタクト電極63を用いて、半導体基板10の電位を設定可能である。   As shown in FIG. 1, a contact electrode 63 is disposed on a peripheral region surrounding the recess 100 of the semiconductor substrate 10. As shown in FIG. 4, the contact electrode 63 is connected to the semiconductor substrate 10 in the upper surface insulating film 54 formed on the semiconductor substrate 10 and the opening 630 formed in the surface insulating film 15. Therefore, the potential of the semiconductor substrate 10 can be set using the contact electrode 63 disposed on the upper surface of the semiconductor device.

例えば、半導体基板10を接地することが可能であり、これにより、半導体基板10の電位が安定する。その結果、図1に示した半導体装置では、ノイズの影響による誤動作を防止できる。また、半導体基板10は単一の結晶構造体であるため、1つのコンタクト電極63により、半導体基板10全体の電位を安定にできる。つまり、半導体装置の上側と下側に接地用の電極を配置する必要がなく、半導体装置の構造は複雑にならない。このため、図1に示した半導体装置によれば、構造を複雑にすることなく、半導体基板10の電位を安定にすることが可能である。   For example, the semiconductor substrate 10 can be grounded, so that the potential of the semiconductor substrate 10 is stabilized. As a result, the semiconductor device shown in FIG. 1 can prevent malfunction due to the influence of noise. Further, since the semiconductor substrate 10 is a single crystal structure, the potential of the entire semiconductor substrate 10 can be stabilized by one contact electrode 63. That is, it is not necessary to arrange grounding electrodes on the upper and lower sides of the semiconductor device, and the structure of the semiconductor device is not complicated. Therefore, according to the semiconductor device shown in FIG. 1, the potential of the semiconductor substrate 10 can be stabilized without complicating the structure.

コンタクト電極63を半導体装置の上面に配置する例を図1に示したが、半導体装置の上面以外、例えば下面にコンタクト電極63を配置することも可能である。   Although an example in which the contact electrode 63 is disposed on the upper surface of the semiconductor device is shown in FIG. 1, the contact electrode 63 can be disposed on the lower surface, for example, on the lower surface of the semiconductor device.

図6〜図16を参照して、本発明の実施形態に係る半導体装置の製造方法を説明する。なお、以下に述べる半導体装置の製造方法は一例であり、この変形例を含めて、これ以外の種々の製造方法により実現可能であることは勿論である。   A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. The semiconductor device manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other manufacturing methods including this modification.

(イ)図6(a)、図6(b)に示すように、半導体基板10の上面に表面絶縁膜15を形成する。例えば、半導体基板10にシリコン(Si)基板を使用し、熱酸化法或いは化学的気相成長(CVD)法等により、膜厚0.5μm程度の酸化シリコン(SiO2)膜を表面絶縁膜15として形成する。図6(a)は斜視図、図6(b)は断面図である(図7(a)、図7(b)〜図11(a)、図11(b)において同様。)。 (A) As shown in FIGS. 6A and 6B, a surface insulating film 15 is formed on the upper surface of the semiconductor substrate 10. For example, a silicon (Si) substrate is used as the semiconductor substrate 10, and a silicon oxide (SiO 2 ) film having a thickness of about 0.5 μm is formed on the surface insulating film 15 by a thermal oxidation method or a chemical vapor deposition (CVD) method. Form as. 6A is a perspective view, and FIG. 6B is a cross-sectional view (the same applies to FIGS. 7A, 7B to 11A, and 11B).

(ロ)フォトレジスト膜をエッチングマスクに用いて、表面絶縁膜15の一部を選択的にエッチング除去し、図7(a)〜図7(b)に示すように、第1の凹部110を形成する。半導体基板10がSi基板の場合は、第1の凹部110の形成に、フッ硝酸系のエッチング液等を用いたウェットエッチング法が採用可能である。或いは、深堀り反応性イオンエッチング(D−RIE)法等のドライエッチング法を使用してもよい。   (B) Using the photoresist film as an etching mask, a part of the surface insulating film 15 is selectively removed by etching, so that the first recess 110 is formed as shown in FIGS. 7A to 7B. Form. When the semiconductor substrate 10 is a Si substrate, a wet etching method using a hydrofluoric acid-based etchant or the like can be used to form the first recess 110. Alternatively, a dry etching method such as a deep reactive ion etching (D-RIE) method may be used.

(ハ)熱酸化法やCVD法、スパッタ法、SOG(Spin On Glass)塗布等によって、第1の凹部110の表面にSiO2膜等の絶縁膜を形成する。或いは、酸素をインプラにより打ち込むSIMOX(Separation by Implanted Oxygen)技術を用いて半導体基板10内部に酸化膜を設けることにより、第1の凹部110の表面に絶縁膜を形成してもよい。具体的には、図8(a)〜図8(b)に示すように、第1の凹部110の側壁上に分離絶縁膜40を形成し、底面上に下面絶縁膜50を形成する。分離絶縁膜40と下面絶縁膜50は同時に形成することができる。その場合、分離絶縁膜40と下面絶縁膜50は同一材料からなる。また、分離絶縁膜40と下面絶縁膜50とは接続した状態で形成される。 (C) An insulating film such as a SiO 2 film is formed on the surface of the first recess 110 by thermal oxidation, CVD, sputtering, SOG (Spin On Glass) coating, or the like. Alternatively, an insulating film may be formed on the surface of the first recess 110 by providing an oxide film inside the semiconductor substrate 10 using a SIMOX (Separation by Implanted Oxygen) technique in which oxygen is implanted by implantation. Specifically, as shown in FIGS. 8A to 8B, the isolation insulating film 40 is formed on the side wall of the first recess 110, and the lower surface insulating film 50 is formed on the bottom surface. The isolation insulating film 40 and the lower surface insulating film 50 can be formed simultaneously. In that case, the isolation insulating film 40 and the lower insulating film 50 are made of the same material. The isolation insulating film 40 and the lower insulating film 50 are formed in a connected state.

(ニ)図9(a)、図9(b)に示すように、分離絶縁膜40及び下面絶縁膜50上に埋め込み半導体膜700を形成して、第1の凹部110を埋め込み半導体膜700で埋め込む。例えば、エピタキシャル成長法等によりポリシリコン膜を半導体基板10上に堆積させて、埋め込み半導体膜700を形成する。その後、化学的機械的研磨(CMP)法等により表面絶縁膜15の表面が露出するまで埋め込み半導体膜700の上部を研磨する。次いで、ケミカルドライエッチング(CDE)等により、図10(a)、図10(b)に示すように、埋め込み半導体膜700の上部を厚さdだけエッチバックする。厚さdは、例えば0.5μm〜2.0μm程度である。   (D) As shown in FIGS. 9A and 9B, an embedded semiconductor film 700 is formed on the isolation insulating film 40 and the lower insulating film 50, and the first recess 110 is formed by the embedded semiconductor film 700. Embed. For example, a buried semiconductor film 700 is formed by depositing a polysilicon film on the semiconductor substrate 10 by an epitaxial growth method or the like. Thereafter, the upper portion of the embedded semiconductor film 700 is polished by chemical mechanical polishing (CMP) or the like until the surface of the surface insulating film 15 is exposed. Next, as shown in FIGS. 10A and 10B, the upper portion of the embedded semiconductor film 700 is etched back by a thickness d by chemical dry etching (CDE) or the like. The thickness d is, for example, about 0.5 μm to 2.0 μm.

(ホ)CVD法等を用いて、図11(a)、図11(b)に示すように、膜厚0.5μm〜4.0μm程度の上面絶縁膜54を全面に形成する。半導体基板10上に表面絶縁膜15と上面絶縁膜54の積層体が形成され、埋め込み半導体膜700には上面絶縁膜54が形成される。上面絶縁膜54には例えばSiO2膜を採用可能であるが、SiO2膜に限らず、単層の他の絶縁膜であってもよく、複数の絶縁膜を重ねた積層体であってもよい。例えば、低圧形成により形成された窒化シリコン(LP−SiN)膜等のストレスに強い絶縁膜を単層の酸化膜上に配置した積層体や、熱酸化膜(SiO2膜)とLP−SiN膜とCVD法で形成されたCVD−SiO2膜からなる積層体等が、上面絶縁膜54に採用可能である。 (E) As shown in FIGS. 11A and 11B, an upper surface insulating film 54 having a film thickness of about 0.5 μm to 4.0 μm is formed on the entire surface by CVD or the like. A stacked body of the surface insulating film 15 and the upper surface insulating film 54 is formed on the semiconductor substrate 10, and the upper surface insulating film 54 is formed in the embedded semiconductor film 700. For example, a SiO 2 film can be used as the upper surface insulating film 54, but the insulating film is not limited to the SiO 2 film, and may be another insulating film of a single layer or a laminated body in which a plurality of insulating films are stacked. Good. For example, a stacked body in which an insulating film resistant to stress such as a silicon nitride (LP-SiN) film formed by low-pressure formation is disposed on a single oxide film, a thermal oxide film (SiO 2 film), and an LP-SiN film A laminated body made of a CVD-SiO 2 film formed by the CVD method can be used for the upper surface insulating film 54.

(へ)例えばフォトリソグラフィ技術を用いて上面絶縁膜54上に形成したフォトレジスト膜をエッチングマスクにしたRIE等によって上面絶縁膜54を選択的にエッチングし、上面絶縁膜54を所望のパターンに形成する。具体的には、図12(a)、図12(b)、図12(c)に示すように、可動部20及び固定電極30を形成する領域上の上面絶縁膜54を残して、埋め込み半導体膜700上の上面絶縁膜54を除去する。図12(b)は図12(a)のXIIb−XIIb方向に沿った断面図であり、図12(c)は図12(a)の領域Aの斜視図である。   (F) For example, the upper surface insulating film 54 is selectively etched by RIE or the like using a photoresist film formed on the upper surface insulating film 54 by photolithography as an etching mask to form the upper surface insulating film 54 in a desired pattern. To do. Specifically, as shown in FIGS. 12A, 12B, and 12C, the embedded semiconductor is left with the upper surface insulating film 54 on the region where the movable portion 20 and the fixed electrode 30 are formed. The top insulating film 54 on the film 700 is removed. 12B is a cross-sectional view taken along the XIIb-XIIb direction of FIG. 12A, and FIG. 12C is a perspective view of the region A of FIG.

(ト)図13(a)〜図13(e)に示すように、パターニングした上面絶縁膜54をエッチングマスクに用いて、埋め込み半導体膜700の一部を下面絶縁膜50が露出するまで選択的にエッチングする。これにより、可動部20及び固定電極30の側面が露出する側面溝500が形成される。埋め込み半導体膜700から形成された可動部20及び固定電極30は、第1の凹部110の側壁に形成された分離絶縁膜40をそれぞれ介して、半導体基板10と接続する。側面溝500を形成するエッチングには、D−RIE法を用いたボッシュ法等が採用可能である。図13(b)は図13(a)のXIIIb−XIIIb方向に沿った断面図、図13(c)は図13(a)のXIIIc−XIIIc方向に沿った断面図、図13(d)は図13(a)のXIIId−XIIId方向に沿った断面図、図13(e)は図13(a)の領域Aの斜視図である(図14(a)〜図14(e)〜図16(a)〜図16(e)において同様)。   (G) As shown in FIGS. 13A to 13E, using the patterned upper surface insulating film 54 as an etching mask, a part of the embedded semiconductor film 700 is selectively selected until the lower surface insulating film 50 is exposed. Etch into. Thereby, the side surface groove | channel 500 which the side surface of the movable part 20 and the fixed electrode 30 is exposed is formed. The movable portion 20 and the fixed electrode 30 formed from the embedded semiconductor film 700 are connected to the semiconductor substrate 10 via the isolation insulating film 40 formed on the side wall of the first recess 110. For the etching for forming the side groove 500, a Bosch method using a D-RIE method or the like can be employed. 13B is a cross-sectional view along the XIIIb-XIIIb direction of FIG. 13A, FIG. 13C is a cross-sectional view along the XIIIc-XIIIc direction of FIG. 13A, and FIG. 13A is a cross-sectional view taken along the XIIId-XIIId direction in FIG. 13A, and FIG. 13E is a perspective view of the region A in FIG. 13A (FIGS. 14A to 14E to 16). The same applies to (a) to FIG. 16 (e)).

(チ)図14(a)〜図14(e)に示すように、側面溝500に露出した可動部20及び固定電極30の側面に、側面絶縁膜52を形成する。側面絶縁膜52は、膜厚が例えば0.1μm〜0.3μm程度のSiO2膜やSiN膜等の絶縁膜である。側面絶縁膜52の形成には、熱酸化法やCVD法が使用可能である。側面絶縁膜52を薄く形成するほど可動部20と固定電極30間を狭くでき、可動部20と固定電極30を高密度に配置できる。その結果、検出感度を向上できる。 (H) As shown in FIGS. 14A to 14E, the side insulating film 52 is formed on the side surfaces of the movable portion 20 and the fixed electrode 30 exposed in the side groove 500. The side insulating film 52 is an insulating film such as a SiO 2 film or a SiN film having a thickness of, for example, about 0.1 μm to 0.3 μm. For the formation of the side insulating film 52, a thermal oxidation method or a CVD method can be used. The thinner the side insulating film 52 is, the narrower the distance between the movable part 20 and the fixed electrode 30 can be, and the movable part 20 and the fixed electrode 30 can be arranged with high density. As a result, detection sensitivity can be improved.

(リ)例えばテープレジストを使用したフォトリソグラフィ技術と異方性エッチング等によって、図15(a)〜図15(e)に示すように、側面溝500の底面に露出した下面絶縁膜50を除去する。これにより、側面溝500の底面に半導体基板10の表面が露出する。一方、可動部20及び固定電極30の下面には、下面絶縁膜50が残る。下面絶縁膜50の除去と同時に、可動部20、固定電極30上に形成された上面絶縁膜54の一部を除去して、開口部610、620を形成する。また、半導体基板10上に形成された上面絶縁膜54及び表面絶縁膜15の一部を除去して、開口部630を形成する。   (I) The lower surface insulating film 50 exposed on the bottom surface of the side groove 500 is removed as shown in FIGS. 15A to 15E by, for example, a photolithography technique using a tape resist and anisotropic etching. To do. As a result, the surface of the semiconductor substrate 10 is exposed on the bottom surface of the side groove 500. On the other hand, the lower surface insulating film 50 remains on the lower surfaces of the movable portion 20 and the fixed electrode 30. Simultaneously with the removal of the lower surface insulating film 50, a part of the upper surface insulating film 54 formed on the movable portion 20 and the fixed electrode 30 is removed to form openings 610 and 620. Further, a part of the upper surface insulating film 54 and the surface insulating film 15 formed on the semiconductor substrate 10 is removed, and an opening 630 is formed.

(ヌ)図16(a)〜図16(e)に示すように、開口部610を介して可動部20と接続する電極配線61、開口部620を介して固定電極30と接続する電極配線62、及び開口部630を介して半導体基板10と接続するコンタクト電極63を形成する。例えば、所望のパターンに形成したフォトレジスト膜を用いたリフトオフ法、或いはフォトレジスト膜をエッチングマスクに用いたエッチング法によって、アルミニウム(Al)膜等の金属膜からなる電極配線61、62、及びコンタクト電極63を形成する。   (N) As shown in FIGS. 16A to 16E, an electrode wiring 61 connected to the movable portion 20 through the opening 610 and an electrode wiring 62 connected to the fixed electrode 30 through the opening 620. The contact electrode 63 connected to the semiconductor substrate 10 through the opening 630 is formed. For example, the electrode wirings 61 and 62 made of a metal film such as an aluminum (Al) film, and the contact are formed by a lift-off method using a photoresist film formed in a desired pattern or an etching method using the photoresist film as an etching mask. An electrode 63 is formed.

(ル)可動部20と固定電極30の側面に形成された側面絶縁膜52、及び可動部20と固定電極30の下面に形成された下面絶縁膜50をエッチングマスクに用いて、半導体基板10の上部の一部を等方性エッチングによってエッチングし、第2の凹部120を形成する。この等方性エッチング(以下において、「リリースエッチング」という。)により、可動部20及び固定電極30の底部と半導体基板10とが分離され、可動部20及び固定電極30の下面に配置された下面絶縁膜50が露出される。つまり、リリースエッチングによって、第2の凹部120上方に可動部20及び固定電極30が配置される。例えば半導体基板10がシリコン基板の場合には、六フッ化硫黄(SF6)や二フッ化キセノン(XeF2)を使用した等方性エッチャー等により、リリースエッチングを行う。以上により、図1に示した半導体装置が完成する。すなわち、側面溝500と第2の凹部120からなり半導体基板10の上面に形成された凹部100内に、可動部20及び固定電極30が配置される。 (L) The side surface insulating film 52 formed on the side surface of the movable part 20 and the fixed electrode 30 and the lower surface insulating film 50 formed on the lower surface of the movable part 20 and the fixed electrode 30 are used as etching masks. A part of the upper part is etched by isotropic etching to form the second recess 120. By this isotropic etching (hereinafter referred to as “release etching”), the bottom of the movable portion 20 and the fixed electrode 30 and the semiconductor substrate 10 are separated, and the bottom surface disposed on the bottom surfaces of the movable portion 20 and the fixed electrode 30. The insulating film 50 is exposed. That is, the movable portion 20 and the fixed electrode 30 are disposed above the second recess 120 by release etching. For example, when the semiconductor substrate 10 is a silicon substrate, release etching is performed by an isotropic etcher using sulfur hexafluoride (SF 6 ) or xenon difluoride (XeF 2 ). Thus, the semiconductor device shown in FIG. 1 is completed. That is, the movable portion 20 and the fixed electrode 30 are disposed in a recess 100 that is formed of the side surface groove 500 and the second recess 120 and formed on the upper surface of the semiconductor substrate 10.

以上に説明したように、本発明の実施形態に係る半導体装置の製造法によれば、半導体基板10の上面に第1の凹部110を形成し、第1の凹部110上に下面絶縁膜50を形成した後、可動部20及び固定電極30を形成するための埋め込み半導体膜700で第1の凹部110を埋め込む。したがって、基板の張り合わせ工程等の複雑な工程はなく、簡単な構造である。また、犠牲層である絶縁膜層を含むSOI基板等を採用する必要もなく、半導体基板10は単一の結晶構造体である。   As described above, according to the method for manufacturing a semiconductor device according to the embodiment of the present invention, the first recess 110 is formed on the upper surface of the semiconductor substrate 10, and the lower insulating film 50 is formed on the first recess 110. After the formation, the first recess 110 is embedded with an embedded semiconductor film 700 for forming the movable portion 20 and the fixed electrode 30. Therefore, there is no complicated process such as a substrate bonding process, and the structure is simple. Further, it is not necessary to employ an SOI substrate including an insulating film layer that is a sacrificial layer, and the semiconductor substrate 10 has a single crystal structure.

また、図10(b)を参照して説明したように、埋め込み半導体膜700の上面は、厚さdだけエッチバックされ、表面絶縁膜15の上面より低くなる。このため、図17に示すように、半導体装置の上面に蓋90を配置した場合に、可動部20と蓋90の間に空間が生じ、可動部20が上下方向に振動しても蓋90に接触しない構造を実現できる。厚さdは、可動部20の振動幅等を考慮して設定される。蓋90は、例えばガラスやシリコンからなる板形状の蓋を採用可能である。なお、埋め込み半導体膜700の上面をエッチバックしない場合には、埋め込み半導体膜700の上面の位置と表面絶縁膜15の上面の位置とは一致する。この場合には、可動部20及び固定電極30の上面と、凹部100周囲の半導体基板10の周辺領域の上面とは同一平面レベルになる。   Further, as described with reference to FIG. 10B, the upper surface of the embedded semiconductor film 700 is etched back by the thickness d and becomes lower than the upper surface of the surface insulating film 15. For this reason, as shown in FIG. 17, when the lid 90 is arranged on the upper surface of the semiconductor device, a space is generated between the movable portion 20 and the lid 90, and the lid 90 is not affected even if the movable portion 20 vibrates in the vertical direction. A structure without contact can be realized. The thickness d is set in consideration of the vibration width of the movable part 20 and the like. The lid 90 can employ a plate-like lid made of, for example, glass or silicon. If the upper surface of the embedded semiconductor film 700 is not etched back, the position of the upper surface of the embedded semiconductor film 700 and the position of the upper surface of the surface insulating film 15 coincide. In this case, the upper surface of the movable part 20 and the fixed electrode 30 and the upper surface of the peripheral region of the semiconductor substrate 10 around the recess 100 are at the same plane level.

埋め込み半導体膜700によって第1の凹部110を隙間無く埋め込むためには、図7(b)に示したように、第1の凹部110の側壁が底面に対してテーパを持って形成され、第1の凹部110は開口部が底部より広いことが好ましい。第1の凹部110の側壁と底面とがなすテーパ角は、例えば72度〜85度程度である。   In order to fill the first recess 110 with the embedded semiconductor film 700 without a gap, as shown in FIG. 7B, the side wall of the first recess 110 is formed with a taper with respect to the bottom surface. The recess 110 preferably has a wider opening than the bottom. The taper angle formed between the side wall and the bottom surface of the first recess 110 is, for example, about 72 to 85 degrees.

第1の凹部110の深さは、可動部20や固定電極30の厚みに基づいて設定され、例えば30μm〜100μm程度である。可動部20や固定電極30が厚いほど検出感度が高くなるため、第1の凹部110の深さは、所望の検出感度に依存する。半導体基板10の上面に埋め込んだ埋め込み半導体膜700から可動部20及び固定電極30を形成するため、可動部20及び固定電極30の厚さばらつきを容易に低減できる。   The depth of the 1st recessed part 110 is set based on the thickness of the movable part 20 or the fixed electrode 30, for example, is about 30 micrometers-about 100 micrometers. Since the detection sensitivity increases as the movable part 20 and the fixed electrode 30 are thicker, the depth of the first recess 110 depends on the desired detection sensitivity. Since the movable portion 20 and the fixed electrode 30 are formed from the embedded semiconductor film 700 embedded in the upper surface of the semiconductor substrate 10, variations in thickness of the movable portion 20 and the fixed electrode 30 can be easily reduced.

第1の凹部110の深さは、エッチング時間を制御して所定の深さに設定できる。或いは、図18(a)に示すように、不純物濃度の異なる2つの半導体層を積層した半導体基板10を使用することにより、第1の凹部110の深さをより高精度に制御してもよい。例えば、p型不純物濃度が1×1018〜1×1020cm-3程度の半導体層10B上に、p型不純物濃度が1×1017cm-3程度の半導体層10Aを積層して半導体基板10を構成する。不純物濃度の違いから半導体層10Aと半導体層10Bのエッチングレートが異なり、半導体層10Aと半導体層10Bの界面でエッチングをほぼ停止させることができる。このため、図18(b)に示すように、半導体層10Aの膜厚が深さである第1の凹部110を形成できる。半導体層10Aと半導体層10Bの不純物濃度の差は1桁程度あればよい。このように、不純物濃度の異なる2つの半導体層を積層した半導体基板10を使用することによって、第1の凹部110の深さを精密に制御することができ、可動部20及び固定電極30の厚みのばらつきを低減できる。 The depth of the first recess 110 can be set to a predetermined depth by controlling the etching time. Alternatively, as shown in FIG. 18A, the depth of the first recess 110 may be controlled with higher accuracy by using a semiconductor substrate 10 in which two semiconductor layers having different impurity concentrations are stacked. . For example, a semiconductor substrate 10A having a p-type impurity concentration of about 1 × 10 17 cm −3 is stacked on a semiconductor layer 10B having a p-type impurity concentration of about 1 × 10 18 to 1 × 10 20 cm −3. 10 is configured. The etching rates of the semiconductor layer 10A and the semiconductor layer 10B are different due to the difference in impurity concentration, and the etching can be almost stopped at the interface between the semiconductor layer 10A and the semiconductor layer 10B. For this reason, as shown in FIG. 18B, the first recess 110 having the depth of the semiconductor layer 10A can be formed. The difference in impurity concentration between the semiconductor layer 10A and the semiconductor layer 10B may be about one digit. As described above, by using the semiconductor substrate 10 in which two semiconductor layers having different impurity concentrations are stacked, the depth of the first recess 110 can be precisely controlled, and the thickness of the movable portion 20 and the fixed electrode 30 can be controlled. The variation of can be reduced.

更に、図1に示した半導体装置では、可動部20及び固定電極30の下面に下面絶縁膜50が配置されている。このため、リリースエッチングにおいて、例えば図19に示すように可動部20や固定電極30の下面がエッチングされることが防止される。図19に示した矢印は、エッチングの進む方向である。したがって、可動部20及び固定電極30の下面に下面絶縁膜50を配置することにより、可動部20や固定電極30が薄くなることが防止される。その結果、可動部20及び固定電極30の厚みにばらつきが生じない。更に、可動電極21と固定電極30の互いに対向する面積の減少が抑制される。   Further, in the semiconductor device shown in FIG. 1, a lower surface insulating film 50 is disposed on the lower surfaces of the movable portion 20 and the fixed electrode 30. For this reason, in the release etching, for example, as shown in FIG. 19, the lower surface of the movable portion 20 and the fixed electrode 30 is prevented from being etched. The arrow shown in FIG. 19 is the direction in which etching proceeds. Therefore, by disposing the lower surface insulating film 50 on the lower surfaces of the movable portion 20 and the fixed electrode 30, it is possible to prevent the movable portion 20 and the fixed electrode 30 from becoming thin. As a result, the thickness of the movable part 20 and the fixed electrode 30 does not vary. Furthermore, a decrease in the area where the movable electrode 21 and the fixed electrode 30 face each other is suppressed.

したがって、可動部20及び固定電極30の下面に下面絶縁膜50が配置された図1に示した半導体装置では、可動部20及び固定電極30の下面がエッチングされる検出装置に比べて、検出感度が向上する。下面絶縁膜50の膜厚は、リリースエッチングにおいて下面絶縁膜50がエッチングされて可動部20及び固定電極30の下面が露出されない程度の厚さであればよく、リリースエッチングでの半導体基板10と下面絶縁膜50とのエッチングレート差等により決定される。下面絶縁膜50の膜厚は、例えば0.5μm程度である。   Therefore, in the semiconductor device shown in FIG. 1 in which the lower surface insulating film 50 is disposed on the lower surfaces of the movable portion 20 and the fixed electrode 30, the detection sensitivity is higher than that of the detection device in which the lower surfaces of the movable portion 20 and the fixed electrode 30 are etched. Will improve. The film thickness of the lower surface insulating film 50 may be such a thickness that the lower surface insulating film 50 is etched in release etching and the lower surfaces of the movable portion 20 and the fixed electrode 30 are not exposed. It is determined by the etching rate difference with the insulating film 50 or the like. The film thickness of the lower surface insulating film 50 is, for example, about 0.5 μm.

なお、可動部20及び固定電極30が梁型形状であるため、リリースエッチング時にエッチャントが可動部20及び固定電極30の横方向(短手方向)から回り込んで、可動部20及び固定電極30と半導体基板10とを分離する。このため、第2の凹部120を深くする必要がない。   Since the movable part 20 and the fixed electrode 30 have a beam shape, the etchant turns around from the lateral direction (short direction) of the movable part 20 and the fixed electrode 30 during the release etching, and the movable part 20 and the fixed electrode 30 The semiconductor substrate 10 is separated. For this reason, it is not necessary to make the 2nd recessed part 120 deep.

上記のように絶縁膜層のない半導体基板10を使用するため、1つのコンタクト電極63によって半導体基板10全体の電位を安定にし、ノイズの影響による誤動作を防止できる。例えば、半導体装置の上側と下側に接地用の電極を配置する必要がない。したがって、本発明の実施形態に係る半導体装置の製造法によれば、構造を複雑にすることなく、基板の電位を安定にすることが可能な半導体装置を提供できる。   Since the semiconductor substrate 10 without an insulating film layer is used as described above, the potential of the entire semiconductor substrate 10 can be stabilized by one contact electrode 63, and malfunction due to the influence of noise can be prevented. For example, it is not necessary to arrange grounding electrodes on the upper and lower sides of the semiconductor device. Therefore, according to the method for manufacturing a semiconductor device according to the embodiment of the present invention, it is possible to provide a semiconductor device capable of stabilizing the potential of the substrate without complicating the structure.

なお、半導体装置の上面全体ではなく、一部に埋め込み半導体膜700が埋め込まれる。例えば埋め込み半導体膜700がポリシリコン膜である場合、可動部20及び固定電極30を厚くするために第1の凹部110を深くすると、第1の凹部110に埋め込まれたポリシリコンのグレインサイズの影響によって半導体装置の表面が荒れる。しかし、図1に示した半導体装置の場合は、凹部100周辺の、例えば単結晶シリコンである半導体基板10の表面にアライメントキーを形成できる。アライメント部分の表面が荒れていないため、アライメント精度が低下しない。したがって、検出感度を向上するために可動部20及び固定電極30を厚く形成する場合でも、微細加工の精度が低下しない。   Note that the embedded semiconductor film 700 is embedded not in the entire top surface of the semiconductor device but in a part thereof. For example, when the embedded semiconductor film 700 is a polysilicon film, if the first recess 110 is deepened to make the movable portion 20 and the fixed electrode 30 thick, the influence of the grain size of the polysilicon embedded in the first recess 110 is affected. As a result, the surface of the semiconductor device is roughened. However, in the case of the semiconductor device shown in FIG. 1, an alignment key can be formed on the surface of the semiconductor substrate 10 made of, for example, single crystal silicon, around the recess 100. Since the surface of the alignment portion is not rough, alignment accuracy does not decrease. Therefore, even when the movable part 20 and the fixed electrode 30 are formed thick in order to improve the detection sensitivity, the precision of microfabrication does not decrease.

(その他の実施形態)
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

例えば、一方向の加速度を検出するだけでなく、複数の方向の加速度を検出する多軸加速度センサに本発明は適用可能である。また、半導体装置が加速度センサである例を示したが、加速度センサに限られず、外力に応じて変位する構造を利用して物理量を検出する種々のセンサ等に本発明は適用可能である。例えば、角速度センサ、圧力センサ、力センサ等にも本発明は適用可能である。   For example, the present invention is applicable to a multi-axis acceleration sensor that detects not only acceleration in one direction but also acceleration in a plurality of directions. In addition, although an example in which the semiconductor device is an acceleration sensor has been described, the present invention is not limited to an acceleration sensor, and the present invention can be applied to various sensors that detect a physical quantity using a structure that is displaced according to an external force. For example, the present invention can be applied to an angular velocity sensor, a pressure sensor, a force sensor, and the like.

このように、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。   As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

本発明の半導体装置は、可動部を有する半導体センサを製造する製造業を含む電子機器産業に利用可能である。   The semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry that manufactures semiconductor sensors having movable parts.

10…半導体基板
15…表面絶縁膜
20…可動部
21…可動電極
22…中心ストライプ部
23…バネ部
30…固定電極
40…分離絶縁膜
50…下面絶縁膜
52…側面絶縁膜
54…上面絶縁膜
61、62…電極配線
63…コンタクト電極
90…蓋
100…凹部
110…第1の凹部
120…第2の凹部
500…側面溝
610、620、630…開口部
700…埋め込み半導体膜
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 15 ... Surface insulating film 20 ... Movable part 21 ... Movable electrode 22 ... Center stripe part 23 ... Spring part 30 ... Fixed electrode 40 ... Isolation insulating film 50 ... Lower surface insulating film 52 ... Side surface insulating film 54 ... Upper surface insulating film 61, 62 ... electrode wiring 63 ... contact electrode 90 ... lid 100 ... recess 110 ... first recess 120 ... second recess 500 ... side groove 610, 620, 630 ... opening 700 ... buried semiconductor film

Claims (13)

上面に凹部が形成された、単一の結晶構造体の半導体基板と、
前記凹部内に配置され、下面に下面絶縁膜が配置された可動電極を有し、前記可動電極より離間した位置において前記半導体基板に固定された梁型の可動部と、
前記可動電極に対向して前記凹部内に配置され、前記半導体基板に固定された梁型の固定電極と、
前記可動部及び前記固定電極と前記半導体基板との間に配置され、前記可動電極及び前記固定電極と前記半導体基板とを電気的に分離する分離絶縁膜と、
前記半導体基板に接続するコンタクト電極と
を備えることを特徴とする半導体装置。
A semiconductor substrate of a single crystal structure having a recess formed on the upper surface;
A movable electrode having a movable electrode disposed in the recess and having a lower surface insulating film disposed on the lower surface, and fixed to the semiconductor substrate at a position spaced apart from the movable electrode;
A beam-shaped fixed electrode disposed in the recess facing the movable electrode and fixed to the semiconductor substrate;
An isolation insulating film disposed between the movable part and the fixed electrode and the semiconductor substrate, and electrically separating the movable electrode and the fixed electrode from the semiconductor substrate;
And a contact electrode connected to the semiconductor substrate.
前記分離絶縁膜が、前記凹部を囲んで前記凹部の側壁上に配置されていることを特徴とする請求項1に記載の半導体装置。   The semiconductor device according to claim 1, wherein the isolation insulating film is disposed on a sidewall of the recess so as to surround the recess. 前記分離絶縁膜と前記下面絶縁膜とが同一材料からなることを特徴とする請求項1又は2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the isolation insulating film and the lower surface insulating film are made of the same material. 前記分離絶縁膜と前記下面絶縁膜が接続していることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the isolation insulating film and the lower surface insulating film are connected to each other. 前記コンタクト電極が、前記凹部を囲む前記半導体基板の周辺領域上に配置されていることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the contact electrode is disposed on a peripheral region of the semiconductor substrate surrounding the recess. 前記可動電極と前記固定電極とが交差指状に配置されていることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the movable electrode and the fixed electrode are arranged in a crossed finger shape. 前記可動部の前記半導体基板との接続部分がバネ形状であることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a connection portion of the movable portion with the semiconductor substrate is a spring shape. 可動電極を有する可動部と、前記可動電極に対向して半導体基板に固定された固定電極とを有する半導体装置の製造方法であって、
前記半導体基板の上面の一部をエッチングして、第1の凹部を形成するステップと、
前記第1の凹部の側壁上に分離絶縁膜、底面上に下面絶縁膜をそれぞれ形成するステップと、
前記分離絶縁膜及び前記下面絶縁膜上に埋め込み半導体膜を形成して、前記第1の凹部を前記埋め込み半導体膜で埋め込むステップと、
前記埋め込み半導体膜の一部をエッチングして、前記可動部及び前記固定電極の側面が露出する側面溝を形成するステップと、
前記側面溝に露出した前記可動部と前記固定電極の側面に側面絶縁膜を形成するステップと、
前記側面溝の底面に露出した前記下面絶縁膜を除去するステップと、
前記側面絶縁膜及び前記下面絶縁膜をマスクに用いたエッチングによって前記半導体基板の上部の一部に第2の凹部を形成して、前記可動部及び前記固定電極の下面を前記半導体基板から分離するステップと
を含むことを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, comprising: a movable part having a movable electrode; and a fixed electrode fixed to a semiconductor substrate facing the movable electrode,
Etching a part of the upper surface of the semiconductor substrate to form a first recess;
Forming a separation insulating film on the side wall of the first recess and a lower surface insulating film on the bottom surface;
Forming a buried semiconductor film on the isolation insulating film and the bottom insulating film, and embedding the first recess with the buried semiconductor film;
Etching a part of the embedded semiconductor film to form a side groove in which side surfaces of the movable part and the fixed electrode are exposed;
Forming a side surface insulating film on the side surface of the movable part exposed to the side surface groove and the fixed electrode;
Removing the lower surface insulating film exposed at the bottom of the side groove;
A second recess is formed in a part of the upper portion of the semiconductor substrate by etching using the side surface insulating film and the lower surface insulating film as a mask, and the lower surface of the movable part and the fixed electrode is separated from the semiconductor substrate. A method for manufacturing a semiconductor device comprising the steps of:
前記埋め込み半導体膜の上部をエッチバックするステップを更に含むことを特徴とする請求項8に記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of etching back an upper portion of the embedded semiconductor film. 前記埋め込み半導体膜上に配置された上面絶縁膜をマスクにして前記埋め込み半導体膜の一部をエッチングし、前記側面溝を形成することを特徴とする請求項8又は9に記載の半導体装置の製造方法。   10. The manufacturing method of a semiconductor device according to claim 8, wherein a part of the embedded semiconductor film is etched using an upper surface insulating film disposed on the embedded semiconductor film as a mask to form the side groove. Method. 前記可動部及び前記固定電極上に形成された前記上面絶縁膜の一部を除去して開口部を形成するステップと、
前記開口部で前記可動部又は前記固定電極とそれぞれ接続する電極配線を前記上面絶縁膜上に形成するステップと
を更に含むことを特徴とする請求項10に記載の半導体装置の製造方法。
Removing a part of the upper surface insulating film formed on the movable part and the fixed electrode to form an opening;
The method for manufacturing a semiconductor device according to claim 10, further comprising: forming, on the upper surface insulating film, electrode wirings respectively connected to the movable part or the fixed electrode in the opening.
前記半導体基板上に形成された前記上面絶縁膜の一部を除去して開口部を形成するステップと、
前記開口部で前記半導体基板と接続するコンタクト電極を前記上面絶縁膜上に形成するステップと
を更に含むことを特徴とする請求項10又は11に記載の半導体装置の製造方法。
Removing a part of the upper surface insulating film formed on the semiconductor substrate to form an opening;
The method for manufacturing a semiconductor device according to claim 10, further comprising: forming a contact electrode connected to the semiconductor substrate at the opening on the upper surface insulating film.
前記側面溝の底面に露出した前記下面絶縁膜の除去と同時に、前記上面絶縁膜の一部を除去して前記開口部を形成することを特徴とする請求項11又は12に記載の半導体装置の製造方法。   13. The semiconductor device according to claim 11, wherein the opening is formed by removing a part of the upper surface insulating film simultaneously with the removal of the lower surface insulating film exposed on the bottom surface of the side surface groove. Production method.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101539197B1 (en) * 2015-02-05 2015-07-24 주식회사 스탠딩에그 Method of micromachining having improved movement performance along z-axis and minimized structure depth variance, and accelerometer using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101539197B1 (en) * 2015-02-05 2015-07-24 주식회사 스탠딩에그 Method of micromachining having improved movement performance along z-axis and minimized structure depth variance, and accelerometer using the same
WO2016126126A1 (en) * 2015-02-05 2016-08-11 주식회사 스탠딩에그 Micromachining method enabling improvement of z-axis movement performance and minimizing of depth deviation of structure, and acceleration sensor using same

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