KR100613604B1 - Method Of Forming Floating Structure By SOI Wafer - Google Patents

Method Of Forming Floating Structure By SOI Wafer Download PDF

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KR100613604B1
KR100613604B1 KR1020050008496A KR20050008496A KR100613604B1 KR 100613604 B1 KR100613604 B1 KR 100613604B1 KR 1020050008496 A KR1020050008496 A KR 1020050008496A KR 20050008496 A KR20050008496 A KR 20050008496A KR 100613604 B1 KR100613604 B1 KR 100613604B1
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floating
soi wafer
wafer
floating structure
soi
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KR1020050008496A
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KR20060087694A (en
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나경원
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삼성전자주식회사
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5719—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using planar vibrating masses driven in a translation vibration along an axis
    • G01C19/5769—Manufacturing; Mounting; Housings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/095—Feed-through, via through the lid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers

Abstract

개시된 본 발명에 의한 SOI 웨이퍼를 이용한 부유 구조체 형성방법은, a) 부유공간이 미리 형성된 SOI 웨이퍼를 준비하는 단계; b) 상기 SOI 웨이퍼와 캡을 본딩하는 단계; c) 상기 SOI 웨이퍼를 일정 두께로 가공하는 단계; 및 d) 상기 SOI 웨이퍼에 부유부재를 형성하는 단계;를 포함하는 것을 특징으로 한다.Floating structure forming method using a SOI wafer according to the present invention, the method comprising the steps of: a) preparing a SOI wafer in which the floating space is formed; b) bonding the SOI wafer and a cap; c) processing the SOI wafer to a predetermined thickness; And d) forming a floating member on the SOI wafer.

마이크로 자이로스코트, 부유 구조체, SOI 웨이퍼, 부유부재Micro Gyros Coat, Floating Structure, SOI Wafer, Floating Material

Description

ＳＯＩ 웨이퍼를 이용한 부유 구조체 형성방법{Method Of Forming Floating Structure By SOI Wafer}Method of Forming Floating Structure By SOI Wafer

도 1a 내지 1d는 종래 부유 구조체 형성 공정도,1a to 1d is a conventional floating structure forming process chart,

도 2a 내지 2d는 본 발명의 일 실시예에 따른 부유 구조체 형성 공정도,2a to 2d is a floating structure forming process according to an embodiment of the present invention,

도 3은 본 발명의 일 실시예에 따른 부유 구조체 형성 공정을 나타낸 흐름도이다.3 is a flow chart showing a floating structure forming process according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

90..캡 100..SOI 웨이퍼90..Cap 100..SOI wafer

110..제1웨이퍼 130..산화막110. First wafer 130. Oxide film

140..제2웨이퍼 151,152..금속막140. Second wafer 151, 152 Metal film

210,220..부유부재 S3,S4..부유공간Floating member S3, S4 Floating space

본 발명은 마이크로 자이로스코프 또는 마이크로 가속도센서를 제조하기 위한 부유 구조체 형성방법에 관한 것이다.The present invention relates to a floating structure forming method for manufacturing a micro gyroscope or micro acceleration sensor.

최근, 자이로스코프 또는 가속도센서에 대한 소형화, 고감도화 및 저가격화 를 이룰 수 있는 MEMS(Micro Electro Mechanical System) 기술을 이용한 마이크로 자이로스코프 또는 마이크로 가속도센서가 개발되어 자동차, 가전제품, 정보통신등에 폭넓게 이용되고 있다.Recently, micro gyroscopes or micro accelerometers have been developed using MEMS (Micro Electro Mechanical System) technology that can achieve miniaturization, high sensitivity, and low price of gyroscopes or acceleration sensors, and are widely used in automobiles, home appliances, and information communication. It is becoming.

일 예로, 마이크로 자이로스코프는 부유 구조체내 형성된 위 아래 운동이 가능한 부유부재를 좌우방향의 정전력(electrostatic force)으로 구동한 상태에서, 회전이 가해지면 코리올리 힘(Coriolis force)에 의해 부유부재가 위 아래 방향으로 진동하고, 이때 센서회로는 정전용량으로 변화된 진동의 크기를 검출하는 방식으로 회전방향과 크기를 감지한다. 참고적으로, 이러한 부유부재는 한쪽 부분이 기판으로부터 띄어져 있는 캔티레버와 양단을 제외한 가운데 부분을 기판으로부터 띄워서 공간을 형성한 브릿지 등으로 구성된다. 따라서, 이러한 부유부재가 형성된 부유 구조체를 어떻게 형성하는냐에 따라 마이크로 자이로스코프의 성능이 좌우된다.For example, the micro gyroscope is driven by the electrostatic force in the left and right directions of the floating member formed in the floating structure to move up and down, when the rotation is applied, the floating member is moved by the Coriolis force Vibrating in the downward direction, in which the sensor circuit detects the rotation direction and the magnitude by detecting the magnitude of the vibration changed by the capacitance. For reference, the floating member is composed of a cantilever in which one portion is lifted from the substrate and a bridge in which a center portion is lifted from the substrate to form a space, except for both ends. Therefore, the performance of the micro gyroscope depends on how the floating structure in which the floating member is formed is formed.

한편, 이러한 부유 구조체를 형성하기 위하여 종래에는 다음과 같은 방법이 사용되었다.Meanwhile, in order to form such a floating structure, the following method has been conventionally used.

도 1a을 참조하면, 제1단계로 캡(9)에 부유공간(S1)(S2)을 형성한다. 참고적으로 부유공간(S1)(S2)이란 부유부재(20)가 움직일 수 있는 공간을 말한다. Referring to FIG. 1A, floating spaces S1 and S2 are formed in the cap 9 in a first step. For reference, the floating space (S1) (S2) refers to the space in which the floating member 20 can move.

도 1b를 참조하면, 제2단계로 캡(9)을 SOI(Sillicon On Insulator) 웨이퍼(10)에 본딩한다. 이러한 SOI(Sillicon On Insulator) 웨이퍼(10)는 제1웨이퍼(11)와 제2웨이퍼(12)와 이러한 제1,2웨이퍼(11)(12)사이에 소정의 두께를 가진 산화막(13)을 포함한다.Referring to FIG. 1B, a cap 9 is bonded to a SOI (Sillicon On Insulator) wafer 10 in a second step. The SOI (Sillicon On Insulator) wafer 10 includes an oxide film 13 having a predetermined thickness between the first wafer 11, the second wafer 12, and the first and second wafers 11 and 12. Include.

도 1c를 참조하면, 제3단계로 제2웨이퍼(12, 도 1b참조)를 에칭(etching)작업을 통해 제거하고, 산화막(13, 도 1b참조)을 스트립(Strip)작업을 통해 제거한다. 도 1d를 참조하면, 제4단계로 제1웨이퍼(11)에 건식 에칭을 통해 부유부재(21)(22)를 형성한다.Referring to FIG. 1C, in a third step, the second wafer 12 (see FIG. 1B) is removed by etching, and the oxide film 13 (see FIG. 1B) is removed by stripping. Referring to FIG. 1D, the floating members 21 and 22 are formed on the first wafer 11 through dry etching in a fourth step.

그러나, 상술한 바와 같은 종래의 부유 구조체 형성 공정은 다음과 같은 문제점을 가지고 있다. 첫째, 캡(9)에 부유공간(S1)(S2)을 형성하는 단계가 필요해 공정이 다소 복잡하다. 둘째, 부유부재(21)(22)의 하부에 식각이온이 충전되며, 이로 인해 이온이 반사되어 부유부재(21)(22)에 노치(Notch)가 발생될 수 있다.However, the conventional floating structure forming process as described above has the following problems. First, it is necessary to form the floating space (S1) (S2) in the cap (9) is a rather complicated process. Second, the etching ions are filled in the lower portion of the floating members 21 and 22, and thus ions are reflected to generate notches in the floating members 21 and 22. As shown in FIG.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창안된 것으로, 부유 구조체 형성과정이 간단한 부유 구조체 형성방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a floating structure having a simple floating structure forming process.

본 발명의 다른 목적은, 노치(Notch)의 발생이 방지된 부유 구조체 형성방법을 제공하는데 목적이 있다.Another object of the present invention is to provide a method for forming a floating structure in which generation of notches is prevented.

상기 목적을 달성하기 위한 본 발명에 의한 부유 구조체 형성방법은, a) 부유공간이 미리 형성된 SOI 웨이퍼를 준비하는 단계; b) 상기 SOI 웨이퍼와 캡을 본딩하는 단계; c) 상기 SOI 웨이퍼를 일정 두께로 가공하는 단계; 및 d) 상기 SOI 웨이퍼에 부유부재를 형성하는 단계;를 포함하는 것을 특징으로 한다. 여기서, 상기 부유부재가 형성될 상기 SOI 웨이퍼의 하단에는, 금속막이 설치된 것이 바람직하다. 이럴 경우, 부유 구조체 형성방법은 e) 상기 금속막을 제거하는 단계;를 더 포함하는 것이 바람직하다. 그리고, 상기 부유부재는, 실리콘(Si) Deep RIE(Reactive Lion Etching) 방법으로 형성된 것이 바람직하다.Floating structure formation method according to the present invention for achieving the above object comprises the steps of: a) preparing a SOI wafer in which the floating space is formed in advance; b) bonding the SOI wafer and a cap; c) processing the SOI wafer to a predetermined thickness; And d) forming a floating member on the SOI wafer. Here, it is preferable that a metal film is provided at the bottom of the SOI wafer on which the floating member is to be formed. In this case, the method of forming the floating structure preferably further comprises e) removing the metal film. In addition, the floating member is preferably formed by a silicon (Si) Deep RIE (Reactive Lion Etching) method.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 따른 SOI 웨이퍼를 이용한 부유 구조체 형성방법을 자세히 설명하기로 한다.Hereinafter, a method of forming a floating structure using an SOI wafer according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 3을 참조하면, 본 실시예에 의한 부유 구조체 형성방법의 첫번째 단계는 부유공간(S3)(S4)이 미리 형성되고, 금속막(151)(152)이 설치된 SOI 웨이퍼(100)를 준비하는 단계이다.2A and 3, the first step of the floating structure forming method according to the present embodiment is a SOI wafer 100 in which floating spaces S3 and S4 are formed in advance and metal films 151 and 152 are installed. To prepare.

이러한 SOI(Sillicon On Insulator) 웨이퍼(100)는 제1웨이퍼(110)와 제2웨이퍼(140)와 제1,2웨이퍼(110)(140)사이에 소정의 두께를 가진 산화막(130)을 포함한다. 이러한 SOI 웨이퍼(100)에 부유부재(210)(220)가 움직일 수 있는 부유공간(S3)(S4)이 미리 형성된 관계로 종래와 같이 캡(90)에 부유공간(S1)(S2)을 형성하는 과정을 줄일 수 있다.(도 1a 참조) 따라서, 부유부재(210)(220)를 형성하는 과정이 간단해 지며, 부유공간(S1)(S2)의 깊이(H1)를 정확하게 조절할 수 있다.The SOI (Sillicon On Insulator) wafer 100 includes an oxide film 130 having a predetermined thickness between the first wafer 110, the second wafer 140, and the first and second wafers 110 and 140. do. Since the floating spaces S3 and S4 on which the floating members 210 and 220 are movable are formed in the SOI wafer 100 in advance, the floating spaces S1 and S2 are formed in the cap 90 as in the related art. Therefore, the process of forming the floating members 210 and 220 can be simplified, and the depth H1 of the floating spaces S1 and S2 can be accurately adjusted.

또한, 이러한 부유공간(S3)(S4)내에는 금속막(151)(152)이 설치되며, 구체적으로 부유부재(210)(220)가 형성될 제1웨이퍼(110)의 하면에 설치된다. 이러한 금속막(151)(152)으로 인해 부유부재(210)(220)를 형성하기 위해 제1웨이퍼(110)를 식각하더라도, 캡(90)은 식각되지 않는다. 즉, 금속막(151)(152)이 식각의 장벽 역할을 한다. 또한, 캡(90)에 식각 이온이 충전되지 않아, 이온의 반사가 일어나지 않는다. 따라서, 반사된 이온으로 인해 부유부재에 노치(Notch)가 발생되는 것이 방지된다.(ST1)In addition, the metal films 151 and 152 are installed in the floating spaces S3 and S4, and are specifically installed on the bottom surface of the first wafer 110 on which the floating members 210 and 220 are to be formed. Even if the first wafer 110 is etched to form the floating members 210 and 220 due to the metal layers 151 and 152, the cap 90 is not etched. That is, the metal films 151 and 152 serve as a barrier for etching. In addition, since the etch ions are not filled in the cap 90, the reflection of the ions does not occur. Therefore, the generation of notches in the floating member due to the reflected ions is prevented. (ST1)

도 2b 및 도 3을 참조하면, 두번째 단계는 SOI(Sillicon On Insulator) 웨이퍼(100)와 캡(90)을 본딩하는 단계이다. 구체적으로 제2웨이퍼(140)와 유리재질로 된 캡(90)이 본딩된다.(ST2)Referring to FIGS. 2B and 3, a second step is bonding the caps 90 and the sillicon on insulator (SOI) wafer 100. Specifically, the second wafer 140 and the glass cap 90 are bonded. (ST2)

도 2c 및 도 3를 참조하면, 세번째 단계는 SOI(Sillicon On Insulator) 웨이퍼(100)를 원하는 두께의 멤브레인(Membrane)으로 가공하는 단계로, 구체적으로 랩핑(Lapping) 공정과 CMP(Chemical Mechanical Polishing)공정을 사용하여 제1웨이퍼(110)를 원하는 부유부재(210)(220)가 형성될 수 있는 두께(H2)로 만든다. 이러한 두께(H2)는 대략 40㎛정도이다.(ST3)2C and 3, the third step is to process a SOI (Sillicon On Insulator) wafer 100 into a membrane of a desired thickness, specifically, a lapping process and a chemical mechanical polishing (CMP). Using the process, the first wafer 110 is made to have a thickness H2 at which the desired floating members 210 and 220 can be formed. This thickness H2 is approximately 40 mu m. (ST3)

네번째 단계는 SOI(Sillicon On Insulator) 웨이퍼(100)에 부유부재(210)(220)를 형성하는 단계로, 구체적으로 제1웨이퍼(110)에 이러한 부유부재(210)(220)를 형성한다. 이러한 부유부재(210)(220)는 제1웨이퍼(110)의 해당부분을 포토리소그라피 공정을 통하여, 예컨대 도면에서와 같은 다수의 전극 형태로 패터닝한다. 그런 다음 패터닝된 포토레지스터를 마스크로, 그리고, 부유공간(S3)(S4)에 설치된 금속막(151)(152)을 식각의 장벽으로 하여 실리콘(Si) Deep RIE(Reactive Lion Etching)으로 에칭한다.(ST4)The fourth step is to form the floating members 210 and 220 in the SOI (Sillicon On Insulator) wafer 100. Specifically, the floating members 210 and 220 are formed in the first wafer 110. The floating members 210 and 220 pattern a corresponding portion of the first wafer 110 through a photolithography process, for example, in the form of a plurality of electrodes as shown in the drawing. Then, the patterned photoresist is used as a mask, and the metal layers 151 and 152 provided in the floating spaces S3 and S4 are used as etching barriers and then etched with silicon deep reactive lion etching (Si). (ST4)

도 2d를 참조하면, 다섯번째 단계는 부유부재(210)(220)를 형성한 후, 더 이상 필요가 없는 금속막(151)(152)을 제거하는 단계이다.(ST5)Referring to FIG. 2D, the fifth step is to remove the metal films 151 and 152 that are no longer needed after the floating members 210 and 220 are formed. (ST5)

이상에서 설명한 바와 같은 본 발명의 일 실시예 따른 SOI 웨이퍼를 이용한 부유 구조체 형성방법에 따르면, According to the floating structure forming method using the SOI wafer according to an embodiment of the present invention as described above,                     

첫째, 부유공간이 미리 SOI 웨이퍼에 이미 형성되어 있어 상부캡에 부유공간을 형성하는 과정을 생략할 수 있다. 따라서, 부유 구조체 형성 과정이 간단해진다.First, since the floating space is already formed in the SOI wafer in advance, the process of forming the floating space in the upper cap can be omitted. Therefore, the floating structure forming process is simplified.

둘째, 부유공간에 금속막이 설치되어 있어 부유부재의 하부에 식각이온이 충전되지 않는다. 따라서, 반사된 이온으로 인해 부유부재에 노치(Notch)가 발생되는 것이 방지된다.Second, since a metal film is installed in the floating space, the etching ions are not charged in the lower portion of the floating member. Therefore, notch is prevented from being generated in the floating member due to the reflected ions.

이상, 본 발명을 본 발명의 원리를 예시하기 위한 바람직한 실시예와 관련하여 도시하고 또한 설명하였으나, 본 발명은 그와 같이 도시되고 설명된 그대로의 구성 및 작용으로 한정되는 것이 아니다. 오히려 첨부된 특허청구범위의 사상 및 범주를 일탈함이 없이 본 발명에 대한 다수의 변경 및 수정이 가능함을 당업자들은 잘 이해할 수 있을 것이다. 따라서, 그와 같은 모든 적절한 변경 및 수정과 균등물들도 본 발명의 범위에 속하는 것으로 간주되어야 할 것이다.While the invention has been shown and described in connection with the preferred embodiments for illustrating the principles of the invention, the invention is not limited to the construction and operation as shown and described. Rather, those skilled in the art will appreciate that many modifications and variations of the present invention are possible without departing from the spirit and scope of the appended claims. Accordingly, all such suitable changes, modifications, and equivalents should be considered to be within the scope of the present invention.

Claims (4)

a) 부유공간이 미리 형성된 SOI 웨이퍼를 준비하는 단계;a) preparing a SOI wafer in which the floating space is formed in advance; b) 상기 SOI 웨이퍼와 캡을 본딩하는 단계;b) bonding the SOI wafer and a cap; c) 상기 SOI 웨이퍼를 균일한 두께로 가공하는 단계; 및c) processing the SOI wafer to a uniform thickness; And d) 상기 SOI 웨이퍼에 부유부재를 형성하는 단계;를 포함하는 것을 특징으로 하는 부유 구조체 형성방법.d) forming a floating member on the SOI wafer. 제 1 항에 있어서,The method of claim 1, 상기 부유부재가 형성될 상기 SOI 웨이퍼의 하단에는, 금속막이 설치된 것을 특징으로 하는 부유 구조체 형성방법.And a metal film is provided at a lower end of the SOI wafer on which the floating member is to be formed. 제 2 항에 있어서,The method of claim 2, e) 상기 금속막을 제거하는 단계;를 더 포함하는 것을 특징으로 하는 부유 구조체 형성방법.e) removing the metal film. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서, 상기 부유부재는,The floating member according to any one of claims 1 to 3, wherein 실리콘(Si) Deep RIE(Reactive Lion Etching)방법으로 형성된 것을 특징으로 하는 부유 구조체 형성방법.Floating structure forming method, characterized in that formed by silicon (Si) Deep RIE (Reactive Lion Etching) method.
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KR20010045332A (en) * 1999-11-04 2001-06-05 윤종용 Fablication method of Micro Electromechanical System structure which can be packaged in the state of wafer level
KR20020079040A (en) * 2001-04-12 2002-10-19 조동일 An Electrical Isolation Method for Single-Crystalline Silicon MEMS Using Localized SOI Structure
KR20030077754A (en) * 2002-03-27 2003-10-04 삼성전기주식회사 Micro inertia sensor and method thereof
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010018926A (en) * 1999-08-24 2001-03-15 박종섭 Mobile station having using forced sleep mode
KR20010045332A (en) * 1999-11-04 2001-06-05 윤종용 Fablication method of Micro Electromechanical System structure which can be packaged in the state of wafer level
KR20020079040A (en) * 2001-04-12 2002-10-19 조동일 An Electrical Isolation Method for Single-Crystalline Silicon MEMS Using Localized SOI Structure
KR20030077754A (en) * 2002-03-27 2003-10-04 삼성전기주식회사 Micro inertia sensor and method thereof
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