JP2011035229A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the number of etching processes and to avoid the occurrence of etching damage when a suitable threshold voltage is actualized by adjusting an effective work function of a complementary transistor employing a high dielectric constant film with respect to a semiconductor device and a method of manufacturing the same. <P>SOLUTION: An aluminum film is provided between a first gate insulating film having a higher dielectric constant than that of SiO<SB>2</SB>of an n-channel insulating gate transistor and a first metal gate electrode, and an aluminum oxide film is provided between a second gate insulating film having a higher dielectric constant than that of SiO<SB>2</SB>of a p-channel insulating gate transistor and a second metal gate electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and, for example, relates to a means for adjusting an effective work function in a MIS type semiconductor device using a high dielectric constant film as a gate insulating film.

In recent years, MIS type semiconductor devices have been improved in characteristics by using a high dielectric material for a gate insulating film. For example, a gate insulating film using a hafnium-based material such as HfO ₂ or HfSiON can have a relative dielectric constant of three times or more than that of a conventional silicon oxynitride film, and has a great effect on reducing leakage current. It was.

  However, when a high dielectric material is used, the effective work function is modulated by the fixed charge in the gate insulating film or the dipole at the interface of the gate insulating film, the threshold voltage increases, and sufficient on-current cannot be obtained. There was a problem.

  Therefore, in order to modulate the effective work function, a lanthanum oxide film is formed on the high dielectric material gate insulating film of the n-channel type MISFET, and the effective work function is brought close to 4.8 eV necessary for the n-channel type MISFET. Yes. On the other hand, in the p-channel type MISFET, an aluminum oxide film is formed on the high dielectric material gate insulating film to bring the effective work function close to 4.0 eV necessary for the p-channel type MISFET (for example, Patent Document 1 or Non-patent document 1).

JP 2009-111235 A

H. J. et al. Li and M.M. I. Gardner, “Dual High-k Gate Dielectric With PolyGate Electrode: HfSiON on nMOS and Al 2 O 3 Capping layer on pMOS”, IEEE EDL, 2005, p. p. 441-444

  As described above, in order to adjust the work function, when different types of oxide films are formed on the gate insulating films in the two regions, there are roughly two methods. For example, the gate insulating film and the first adjustment oxide film to be formed in the first region are formed on the entire surface, and the gate insulating film and the first adjustment oxide film formed in the second region are removed. Next, a gate insulating film and a second adjustment oxide film may be formed over the entire surface, and the gate insulating film and the second oxide film formed in the first region may be removed.

  Alternatively, after forming the gate insulating film and the first adjustment oxide film, the portion of the first adjustment oxide film formed on the second region is removed, and then the second adjustment oxidation film is formed on the entire surface. After the film is formed, a portion of the second adjustment oxide film formed on the first region may be removed.

  In the former, it is necessary to form the gate insulating film twice, which increases the number of processes, and affects the substrate more than necessary in order to remove the gate insulating film once formed, thereby deteriorating characteristics and reliability. There is a problem that there is a possibility. On the other hand, the latter has a problem that reliability may be deteriorated because the etching action when removing the oxide film on the insulating film reaches the gate insulating film.

  Therefore, the present invention reduces the number of etching steps and avoids etching damage when adjusting the effective work function of a complementary transistor using a high dielectric constant film to achieve an appropriate threshold voltage. For the purpose.

From one aspect of the present invention, a semiconductor device having an n-channel insulated gate transistor and a p-channel insulated gate transistor, the first gate insulating film having a dielectric constant higher than that of SiO ₂ of the n-channel insulated gate transistor, An aluminum film is provided between one metal gate electrode and an aluminum oxide film is provided between the second gate insulating film having a dielectric constant higher than that of SiO _{2 of the} p-type channel insulated gate transistor and the second metal gate electrode. A semiconductor device is provided.

From another viewpoint of the present invention, a step of forming an n-type region and a p-type region in a semiconductor substrate, and a gate insulating film having a dielectric constant higher than that of SiO ₂ on the surfaces of the n-type region and the p-type region are provided. A step of forming, a step of forming an aluminum film on the gate insulating film, a step of forming a first metal gate film on the aluminum film, and the first metal gate film provided on the n-type region. Selectively removing and exposing the aluminum film provided on the n-type region; oxidizing the exposed aluminum film to form an aluminum oxide film; and A method of manufacturing a semiconductor device, comprising at least a step of forming a two-metal gate film.

  According to the disclosed semiconductor device and the manufacturing method thereof, the effective work function of the n-channel MISFET is adjusted by the Al ultrathin film, and the effective work function of the p-channel MISFET is adjusted by the oxide of the Al ultrathin film. As a result, the number of etching steps can be reduced, and the occurrence of etching damage can be avoided.

1 is a conceptual cross-sectional view of a semiconductor device according to an embodiment of the present invention. It is explanatory drawing of the Al film thickness dependence of an effective work function. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 1 of this invention. FIG. 4 is an explanatory view up to the middle of FIG. 3 and subsequent steps of the manufacturing process of the semiconductor device of Example 1 of the present invention. FIG. 5 is an explanatory view up to the middle of FIG. 4 and subsequent steps of the manufacturing process of the semiconductor device of Example 1 of the present invention. It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of the semiconductor device of Example 1 of this invention. FIG. 7 is an explanatory diagram after FIG. 6 of the manufacturing process of the semiconductor device of Example 1 of the present invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 2 of this invention. FIG. 9 is an explanatory diagram up to the middle of FIG. 8 and subsequent drawings of a manufacturing process of a semiconductor device according to Example 2 of the present invention; FIG. 10 is an explanatory diagram up to the middle of FIG. 9 and subsequent steps of the manufacturing process of the semiconductor device of Example 2 of the present invention; FIG. 11 is an explanatory diagram up to the middle of FIG. 10 and subsequent steps of a manufacturing process of a semiconductor device according to Example 2 of the present invention; FIG. 12 is an explanatory diagram up to the middle of FIG. 11 and subsequent steps of a manufacturing process of a semiconductor device according to Example 2 of the present invention; FIG. 13 is an explanatory diagram after FIG. 12 showing a manufacturing process of a semiconductor device according to Example 2 of the present invention;

  Here, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a conceptual cross-sectional view of a semiconductor device according to an embodiment of the present invention, in which a 0.5 atomic layer to a 2.0 atomic layer are provided between a gate insulating film 3 and a gate electrode 6 of an n-channel insulated gate transistor 1. A layer of aluminum film 4 is provided to reduce the work function and reduce the threshold voltage.

  On the other hand, an aluminum oxide film 5 obtained by oxidizing an aluminum film 4 of 0.5 atomic layer to 2.0 atomic layer is provided between the gate insulating film 3 and the gate electrode 6 of the p-channel insulated gate transistor 2 to obtain a work function. Increase to decrease threshold voltage.

  FIG. 2 is an explanatory diagram of the dependency of the effective work function on the Al film thickness. Here, there are four gates: a TiN single layer film, an Al1 layer / TiN with a single atomic layer Al film underneath, an Al2 layer / TiN with a double atomic layer Al film underneath, and an Al single layer film The results based on the first-principles calculation of the effective work function of the structure are shown.

  As shown in FIG. 2, when there is a monoatomic aluminum film 4 between the gate insulating film 3 and the TiN film 7, the effective work function is lowered by 0.21 eV to 4.30 eV. When the aluminum film 4 is made to be a diatomic layer, it drops to 4.18 eV and approaches the effective work function of aluminum.

  On the other hand, in the p-channel type MISFET, as shown in Non-Patent Document 1 described above, the effective work function is increased by forming the aluminum oxide film 5 on the hafnium oxide film, and the threshold voltage is Get smaller.

  However, as the film thickness of the aluminum film 3 increases, the film thickness of the aluminum oxide film 4 formed by oxidation also increases, and the electrical capacity of the entire gate insulating film decreases.

  For example, the thickness of the aluminum oxide film 5 obtained by oxidizing the aluminum film 3 after laminating two atomic layers is about 0.8 nm, which is about 0.2 nm of the silicon oxide film converted into electric capacity. . If the equivalent film thickness becomes larger than this, the electric capacity of a device having a gate insulating film having a silicon oxide equivalent film thickness of about 1 nm is greatly reduced, and the characteristics deteriorate. Therefore, the aluminum film 3 to be formed needs to be 2 atomic layers or less. In order to maintain the effect of inserting the aluminum film 3, a 0.5 atomic layer is necessary, and a 1 atomic layer or 2 atomic layer is preferable. The atomic layer in this case has a film thickness converted from the film formation rate.

As the gate insulating film 3, a high dielectric constant material containing at least hafnium (Hf) such as HfO ₂ , (HfZr) O ₂ , and HfSiON is suitable.

  The gate electrode 6 preferably has a laminated structure in which the lower layer side is the TiN film 7 and the upper layer side is the polycrystalline silicon film 8 in order to improve the patterning accuracy and prevent other damage in the etching process. is there. That is, if the gate electrode 6 is composed only of the TiN film 7, the patterning accuracy is not sufficient because it is a wet etching process. On the other hand, when the gate electrode 6 is formed using only the polycrystalline silicon film 8, the pattern accuracy is good, but there is a risk of etching damage to other components such as the gate insulating film in the etching process of the polycrystalline silicon film 8. is there.

  Further, in the process of forming the extension region and the source / drain region, sidewalls are provided. In this case, the sidewalls may be silicon oxide films or silicon nitride films, or a combination of both.

  When the source / drain regions and the like are formed using a dummy gate, the gate electrode 6 may be composed of a single layer TiN film 7. The dummy gate preferably has a laminated structure in which the lower layer side is the TiN film 7 and the upper layer side is the polycrystalline silicon film 8 in order to improve the patterning accuracy and prevent other damage in the etching process. However, in this case, it is desirable to provide a silicon nitride film or the like as a cover film so that the surface of the dummy gate is not silicided in the process of forming the silicide electrode.

  Further, the silicide electrode formed on the surface of the source / drain region and the surface of the polycrystalline silicon film 8 is preferably a low resistance Ni silicide electrode, but other silicide materials such as Co silicide may be used.

  In the present invention, as described above, the aluminum oxide film 5 is formed by oxidation with the aluminum film 6 selectively exposed. Therefore, the gate insulating film 3 is formed only once, and the etching effect on the gate insulating film 3 itself can be minimized. Accordingly, a semiconductor device having an n-channel MISFET and a p-channel MISFET having an appropriate effective work function can be easily formed with high reliability.

  Based on the above, next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 3A, an oxide film 12 and a SiN film 13 are sequentially formed on a p-type silicon substrate 11, and the oxide film 12 and the SiN film 13 are patterned by a normal photoetching process. Next, using the patterned oxide film 12 and SiN film 13 as a mask, the exposure of the p-type silicon substrate 11 is etched to form an element isolation trench 14.

  Next, as shown in FIG. 3B, a silicon oxide film is formed on the entire surface so as to embed the element isolation trench 14, and then a CMP (Chemical Mechanical Polishing) process is performed to form an STI (Shallow Trench Isolation) structure. A buried insulating film 15 is formed.

  Next, as shown in FIG. 3C, the oxide film 12 and the SiN film 13 are removed by chemicals to expose the surface of the p-type silicon substrate 11. This exposed region becomes an element formation region.

  Next, as shown in FIG. 3D, patterning with a photoresist and ion implantation are alternately performed, and B is selectively implanted into one element formation region to form a p-type well region 16. An n-type well region 17 is formed by selectively implanting P into the element formation region.

Next, as shown in FIG. 4E, after forming a HfO ₂ film 18 having a thickness of, for example, 2 nm as a gate insulating film using a CVD method, for example, by a sputtering method using Al as a target, For example, a two atomic layer Al film 19 is formed.

  Next, as shown in FIG. 4 (f), the thickness that becomes a part of the gate electrode on the entire surface is, for example, a 10 nm TiN film 20, and the thickness for reducing oxidation resistance and etching damage is, for example, A 30 nm SiN film 21 is sequentially formed.

  Next, as shown in FIG. 4G, a resist pattern 22 covering the p-type well region 16 is formed, and using this resist pattern 22 as a mask, the exposed SiN film 21 is subjected to, for example, RIE (reactive ion etching). Remove. Next, the exposed TiN film 20 is removed using, for example, an aqueous hydrogen peroxide solution to selectively expose the aluminum film 19.

Next, as shown in FIG. 4H, after the resist pattern 22 is removed, the aluminum film 19 exposed on the p-type well region 17 is thermally oxidized at 500 ° C. in an oxygen atmosphere using the SiN film 21 as an oxidation resistant mask. By processing, the Al ₂ O ₃ film 23 is converted.

  Next, as shown in FIG. 5 (m), the thickness that becomes a part of the gate electrode of the p-channel type MISFET is, for example, a 10 nm TiN film 24 and a thickness for reducing oxidation resistance and etching damage. For example, a 30 nm SiN film 25 is sequentially formed.

  Next, as shown in FIG. 5N, a resist pattern 26 is provided so as to selectively cover the n-type well region 17. Next, as shown in FIG. 5 (o), using the resist pattern 22 as a mask, the exposed SiN film 25 is removed by, for example, RIE, and then the exposed TiN film 24 is removed by using, for example, an aqueous hydrogen peroxide solution. .

  Next, as shown in FIG. 6 (p), after the resist pattern 26 is removed, the exposed SiN films 21 and 25 are removed by regions. Next, as shown in FIG. 6 (q), a polycrystalline silicon film 27 having a thickness of, for example, 80 nm is formed on the exposed TiN films 20 and 24.

Next, as shown in FIG. 6R, by using the resist pattern (not shown) as a mask, the polycrystalline silicon film 27 to the HfO ₂ film 18 are sequentially removed by etching, whereby a gate having a width of, for example, 32 nm. Form a structure.

  Next, as shown in FIG. 7S, for example, a SiN film is deposited on the entire surface so as to have a thickness of 5 nm, and then sidewalls 28 are formed by performing anisotropic etching. Next, after patterning with a photoresist and ion implantation using the sidewall 28 and the gate structure as a mask are alternately performed, an activation heat treatment is performed to sequentially form an n-type extension region 29 and a p-type extension region 30.

In forming the n-type extension region 29, for example, As is implanted at an acceleration energy of 1 keV by 1 × 10 ¹⁵ cm ⁻² . On the other hand, when forming the p-type extension region 30, for example, B is implanted by 1 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0.5 keV.

Next, as shown in FIG. 7 (t), for example, a SiN film is deposited on the entire surface so as to have a thickness of 40 nm, and then sidewalls 31 are formed by performing anisotropic etching. Next, patterning with a photoresist and ion implantation using the sidewall 31 and the gate structure as a mask are alternately performed, and then an activation heat treatment is performed, so that the n ⁺ type source / drain region 32 and the p ⁺ type source / drain region 33 are formed. Are sequentially formed.

In forming the n ⁺ -type source / drain regions 32, for example, As is implanted at an acceleration energy of 5 keV by 5 × 10 ¹⁵ cm ⁻² . On the other hand, when forming the p ⁺ type source / drain region 33, for example, B is implanted by 5 × 10 ¹⁵ cm ⁻² at an acceleration energy of 3 keV.

  Next, as shown in FIG. 7 (u), after a Ni film having a thickness of, for example, 10 nm is formed on the entire surface, the exposed silicon surface is silicided by annealing at, for example, 450 ° C. Next, Ni silicide electrodes 34 to 37 are formed by removing the unreacted Ni film deposited on the insulating film.

  Thereafter, although illustration is omitted, after forming the interlayer insulating film, a plug reaching the source / drain region is formed, and then the formation of the wiring layer, the formation of the interlayer insulating film according to the required multilayer wiring structure, By repeating the formation of the connection plug, the semiconductor device of Example 1 of the present invention is completed.

As described above, in Example 1 of the present invention, the number of etching steps is reduced because the HfO ₂ film is formed once and there is no etching step other than the gate structure forming step. It is possible to avoid the occurrence of etching damage.

Next, with reference to FIGS. 8 to 13, a manufacturing process of the semiconductor device of Example 2 of the present invention will be described. First, as shown in FIGS. 3A to 3D, after forming the buried insulating film 15 having the STI structure on the p-type silicon substrate 11, the p-type well region 16 and the n-type well are formed. Region 17 is formed. Next, as shown in FIG. 8A, an HfO ₂ film 18 to be a gate insulating film is formed using a CVD method.

Next, as shown in FIG. 8B, a TiN film 38 having a thickness of, for example, 10 nm, a polycrystalline silicon film 39 having a thickness of, for example, 50 nm, and a thickness serving as a dummy gate over the entire surface. For example, the cover film 40 having a thickness of 30 nm is sequentially formed. In this case, the cover film 40 is provided to prevent the silicide reaction of the dummy gate, and is formed of, for example, a SiN film. The polycrystalline silicon film 39 is provided for accurate patterning by dry etching, while the TiN film 38 causes etching damage to the HfO ₂ film 18 which becomes a gate insulating film by wet etching using a hydrogen peroxide solution or the like. Provide for not.

Next, as shown in FIG. 8C, by using the resist pattern (not shown) as a mask, the cover film 40 to the HfO ₂ film 18 are sequentially removed by etching to form a dummy gate having a width of, for example, 32 nm. Form.

  Next, as shown in FIG. 8D, for example, a SiN film is deposited on the entire surface so as to have a thickness of 5 nm, and then sidewalls 28 are formed by performing anisotropic etching. Next, after patterning with a photoresist and ion implantation using the sidewall 28 and the dummy gate structure as a mask are alternately performed, an activation heat treatment is performed to sequentially form an n-type extension region 29 and a p-type extension region 30. .

In forming the n-type extension region 29, for example, As is implanted at an acceleration energy of 1 keV by 1 × 10 ¹⁵ cm ⁻² . On the other hand, when forming the p-type extension region 30, for example, B is implanted by 1 × 10 ¹⁵ cm ⁻² at an acceleration energy of 0.5 keV.

Next, as shown in FIG. 9E, for example, a SiN film is deposited on the entire surface so as to have a thickness of 40 nm, and then the sidewall 31 is formed by performing anisotropic etching. Next, patterning with a photoresist and ion implantation using the sidewall 31 and the dummy gate structure as masks are alternately performed, and then an activation heat treatment is performed, so that the n ⁺ type source / drain region 32 and the p ⁺ type source / drain region are formed. 33 are formed sequentially.

In forming the n ⁺ -type source / drain regions 32, for example, As is implanted at an acceleration energy of 5 keV by 5 × 10 ¹⁵ cm ⁻² . On the other hand, when forming the p ⁺ -type source / drain region 33, for example, B is implanted by 5 × 10 ¹⁵ cm ⁻² at an acceleration energy of 5 keV.

Next, as shown in FIG. 9F, after a Ni film having a thickness of, for example, 10 nm is formed on the entire surface, the exposed silicon surface is silicided by annealing at, for example, 450 ° C. Next, the Ni silicide electrodes 34 and 36 are formed on the surfaces of the n ⁺ type source / drain region 32 and the p ⁺ type source / drain region 33 by removing the unreacted Ni film deposited on the insulating film.

  Next, as shown in FIG. 9G, after depositing, for example, a silicon oxide film on the entire surface, an interlayer insulating film 41 for embedding a dummy gate is formed by planarization by CMP processing.

  Next, as shown in FIG. 10H, the cover film 40, the polycrystalline silicon film 39, and the TiN film 38 are sequentially removed to form a recess.

  Next, as shown in FIG. 10I, a diatomic layer Al film 19 is formed by sputtering using an Al target, for example. Next, after forming a TiN film 20 to be a gate electrode so as to completely fill the recess, an SiN film 21 having a thickness of, for example, 30 nm for reducing oxidation resistance and etching damage is sequentially formed.

  Next, as shown in FIG. 10K, a resist pattern 42 that covers the p-type well region 16 is formed, and the exposed SiN film 21 is removed by, for example, RIE using the resist pattern 42 as a mask. Next, the exposed TiN film 20 is removed using, for example, an aqueous hydrogen peroxide solution to selectively expose the aluminum film 19.

Next, as shown in FIG. 11L, after removing the resist pattern 42, the aluminum film 19 exposed on the p-type well region 17 is thermally oxidized at 500 ° C. in an oxygen atmosphere using the SiN film 21 as an oxidation resistant mask. By processing, the Al ₂ O ₃ film 23 is converted.

  Next, as shown in FIG. 10 (m), a TiN film 24 that becomes the gate electrode of the p-channel type MISFET is deposited on the entire surface so as to completely fill the recess, and then the thickness for reducing oxidation resistance and etching damage is reduced. For example, a 30 nm SiN film 25 is sequentially formed.

  Next, as shown in FIG. 12 (n), a resist pattern 43 is provided so as to selectively cover the n-type well region 17. Next, as shown in FIG. 12 (o), using the resist pattern 43 as a mask, the exposed SiN film 25 is removed by, for example, RIE, and then the exposed TiN film 24 is removed by using, for example, an aqueous hydrogen peroxide solution. .

  Next, as shown in FIG. 13 (p), the resist pattern 43 is removed. Next, as shown in FIG. 13 (q), after the SiN films 21 and 25 are removed by RIE, a CMP process is performed to form buried gate electrodes made of the TiN films 20 and 24.

  Thereafter, although illustration is omitted, after forming the interlayer insulating film again, plugs reaching the source / drain regions are formed, and then the formation of the wiring layer according to the required multilayer wiring structure, the interlayer insulating film By repeating the formation and the formation of the connection plug, the semiconductor device of Example 2 of the present invention is completed.

Thus, also in Example 2 of the present invention, the etching process for removing the high dielectric constant gate insulating film made of the HfO ₂ film 18 is not a dummy gate structure forming process, so the number of etching processes is reduced. Etching damage can be avoided.

Here, the following supplementary notes are disclosed regarding the embodiment of the present invention including Example 1 and Example 2.
(Supplementary Note 1) A semiconductor device having an n-channel insulated gate transistor and a p-channel insulated gate transistor, the n-channel high dielectric constant than SiO ₂ insulating gate transistor first gate insulating film and the first metal gate electrode And an aluminum oxide film between the second gate insulating film having a higher dielectric constant than SiO ₂ of the p-channel insulated gate transistor and the second metal gate electrode. Semiconductor device.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the gate insulating film having a dielectric constant higher than that of SiO ₂ contains at least hafnium.
(Supplementary note 3) The semiconductor device according to supplementary note 1 or supplementary note 2, wherein the aluminum film has a thickness of 0.5 atomic layer to 2 atomic layer.
(Supplementary Note 4) The supplementary note 1 is characterized in that the first metal gate electrode is either a TiN film or a TiN film / polycrystalline silicon film structure in which the TiN film is on the first gate insulating film side. Or the semiconductor device according to any one of appendix 3;
(Supplementary Note 5) A step of forming an n-type region and a p-type region in a semiconductor substrate, a step of forming a gate insulating film having a dielectric constant higher than that of SiO ₂ on the surfaces of the n-type region and the p-type region, and the gate A step of forming an aluminum film on the insulating film; a step of forming a first metal gate film on the aluminum film; and selectively removing the first metal gate film provided on the n-type region, a step of selectively exposing the aluminum film provided on the n-type region; a step of oxidizing the exposed aluminum film to form an aluminum oxide film; and forming a second metal gate film on the aluminum oxide film. A method for manufacturing a semiconductor device, comprising: at least a step.
(Appendix 6) The step of forming the gate insulating film and the aluminum film is a step of sequentially laminating the gate insulating film and the aluminum film, and selectively exposing the aluminum film provided on the n-type region However, after forming the first metal gate film and the oxidation resistant film on the entire surface of the aluminum film, the first metal gate film and the oxidation resistant film provided on the n-type region are removed to remove the aluminum film. 6. The method of manufacturing a semiconductor device according to appendix 5, wherein the semiconductor device is exposed.
(Appendix 7) In the step of forming the aluminum film, after forming a dummy gate on the gate insulating film, a source / drain region is formed using the dummy gate as a part of a mask, and then an interlayer insulating film is formed. Thereafter, the dummy gate is removed, and then an aluminum film is formed on the entire surface including the recess from which the dummy gate is removed, and the aluminum film provided on the n-type region is selectively exposed. However, after forming the first metal gate film and the oxidation resistant film so as to bury the recess on the aluminum film, the first metal gate film and the oxidation resistant film provided on the n-type region are removed. The method of manufacturing a semiconductor device according to appendix 6, wherein the aluminum film is exposed.
(Appendix 8) The dummy gate has a TiN film / polycrystalline silicon film / oxidation resistant film structure in which a TiN film, a polycrystalline silicon film, and an oxidation resistant film are sequentially laminated from the gate insulating film side. The manufacturing method of the semiconductor device according to appendix 7.
(Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 5 to 8, wherein the gate insulating film having a dielectric constant higher than that of SiO ₂ contains at least hafnium. (Supplementary note 10) The method for manufacturing a semiconductor device according to any one of supplementary notes 5 to 9, wherein the aluminum film has a thickness of 0.5 atomic layer to 2 atomic layer.

1 n-channel insulated gate transistor 2 p-channel insulated gate transistor 3 gate insulating film 4 aluminum film 5 aluminum oxide film 6 gate electrode 7 TiN film 8 polycrystalline silicon film 11 p-type silicon substrate 12 oxide film 13 SiN film 14 element isolation Trench 15 buried insulating film 16 p-type well region 17 n-type well region 18 HfO ₂ film 19 Al film 20, 24, 38 TiN film 21, 25 SiN film 23 Al ₂ O ₃ film 26, 42, 43 resist pattern 27, 39 Polycrystalline silicon films 28, 31 Side walls 29 n-type extension regions 30 p-type extension regions 32 n ⁺ -type source / drain regions 33 p ⁺ -type source / drain regions 34 to 37 Ni silicide electrode 40 cover film 41 interlayer insulating film

Claims (5)

A semiconductor device having an n-channel insulated gate transistor and a p-channel insulated gate transistor between a first gate insulating film and a first metal gate electrode having a dielectric constant higher than that of SiO ₂ of the n-channel insulated gate transistor A semiconductor device having an aluminum film and an aluminum oxide film between a second gate insulating film having a dielectric constant higher than that of SiO ₂ of the p-channel insulated gate transistor and a second metal gate electrode. The semiconductor device according to claim 1, wherein the gate insulating film having a dielectric constant higher than that of SiO ₂ contains at least hafnium.   The semiconductor device according to claim 1, wherein the aluminum film has a thickness of 0.5 atomic layer to 2 atomic layer.   The first metal gate electrode is either a TiN film or a TiN film / polycrystalline silicon film structure in which the TiN film is on the first gate insulating film side. 4. The semiconductor device according to any one of items 3. Forming an n-type region and a p-type region in a semiconductor substrate;
Forming a gate insulating film having a higher dielectric constant than SiO ₂ on the surfaces of the n-type region and the p-type region;
Forming an aluminum film on the gate insulating film;
Forming a first metal gate film on the aluminum film;
Selectively removing the first metal gate film provided on the n-type region and selectively exposing the aluminum film provided on the n-type region;
Oxidizing the exposed aluminum film into an aluminum oxide film;
And forming a second metal gate film on the aluminum oxide film.

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