JP2011035064A - Semiconductor device, semiconductor substrate and processing method of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon layer of which the surface is other than a (111) plane and a nitride semiconductor layer of which the surface is a (0001) plane in a substrate, and to make small the stress caused by the difference in the linear expansion coefficients of silicon and nitride semiconductor. <P>SOLUTION: First, an SOI (silicon-on-insulator) substrate is prepared. The SOI substrate is a substrate in which an insulating layer 120 and a silicon layer 200 are laminated on a silicon substrate 100, of which the surface is the (111) plane. The surface of the silicon layer 200 is a plane orientation of other than (111) plane. After that, an opening 201 of which the silicon substrate 100 is exposed to a bottom face is formed in the insulating layer 120 and the silicon layer 200. After that, a group III nitride semiconductor layer 300 is formed in the opening 201. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a silicon element and a compound semiconductor element are mixedly mounted on the same substrate, a semiconductor substrate, and a semiconductor substrate processing method.

  The semiconductor element is generally manufactured using a silicon substrate or an SOI (Silicon ON Insulator) substrate. On the other hand, in recent years, research has been conducted on manufacturing semiconductor devices using nitride semiconductor layers such as GaN. Since nitride semiconductors have a larger band gap than silicon, elements using nitride semiconductors are expected to have improved characteristics compared to elements using silicon.

  More recently, it has been studied to form an element using silicon and an element using a nitride semiconductor on the same substrate. For example, in Patent Document 1, a (001) 5.3 ° to 9.3 ° silicon off substrate is selectively etched to form a recess, and the (111) surface is in a state of a slope on the bottom surface of this back portion. And the nitride semiconductor layer is epitaxially grown from the (111) plane.

  Patent Document 2 describes that a nitride semiconductor layer is formed on the entire surface of a silicon layer, and an island-like silicon layer is formed thereon.

JP 2004-281454 A Special table 2008-547203 gazette

  When a semiconductor element is formed on silicon, the surface of silicon is preferably a surface other than the (111) plane. On the other hand, when a nitride semiconductor is grown on silicon, the surface of silicon is preferably a (111) plane. However, in the method described in Patent Document 1, since the (111) plane in which the compound semiconductor layer is epitaxially grown in the silicon substrate is inclined, the plane parallel to the substrate surface in the nitride semiconductor layer is (1-101) plane. The nitride semiconductor layer having the (1-101) plane is easily affected by crystal defects, and the quality of the semiconductor element is likely to be lower than that of the nitride semiconductor layer having the (0001) plane.

  In the method described in Patent Document 2, since the nitride semiconductor layer is formed on the entire surface of the silicon layer, the stress due to the difference in the linear expansion coefficient between silicon and the nitride semiconductor increases.

  As described above, a silicon layer having a surface other than the (111) plane and a nitride semiconductor layer having a surface of the (0001) plane are provided on the substrate, and the difference is caused by a difference in linear expansion coefficient between the silicon and the nitride semiconductor. It was difficult to reduce the stress.

According to the present invention, a silicon substrate whose surface is a (111) plane;
An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer and having a surface orientation other than the (111) plane;
An opening formed in the insulating layer and the silicon layer and exposing the silicon substrate on a bottom surface;
A group III nitride semiconductor layer formed in the opening;
A silicon element formed in the silicon layer;
A compound semiconductor element formed in the nitride semiconductor layer;
A semiconductor device is provided.

  According to this semiconductor device, the insulating layer and the silicon layer are formed on the silicon substrate whose surface is the (111) plane. The silicon layer has a surface orientation other than the (111) plane. An opening is formed in the insulating layer and the silicon layer, and the silicon substrate is exposed at the bottom of the opening. The nitride semiconductor layer is formed in the opening. For this reason, the silicon layer whose surface is other than the (111) plane and the nitride semiconductor layer whose surface is the (0001) plane can be provided on the substrate. In addition, since the nitride semiconductor layer is formed only on a part of the silicon substrate, it is possible to reduce stress due to the difference in linear expansion coefficient between silicon and the nitride semiconductor.

According to the present invention, a silicon substrate whose surface is a (111) plane;
An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer and having a surface orientation other than the (111) plane;
An opening formed in the insulating layer and the silicon layer and exposing the silicon substrate on a bottom surface;
A semiconductor substrate is provided.

According to the present invention, a step of preparing an SOI (Silicon On Insulator) substrate in which an insulating layer and a silicon layer having a surface orientation other than the (111) plane are stacked on a silicon substrate having a (111) plane surface; ,
Forming an opening in the bottom surface of the insulating layer and the silicon layer where the silicon substrate is exposed;
Forming a group III nitride semiconductor layer in the opening;
A method for processing a semiconductor substrate is provided.

  According to the present invention, the silicon layer whose surface is other than the (111) plane and the nitride semiconductor layer whose surface is the (0001) plane are provided on the substrate, and the difference between the linear expansion coefficients of silicon and nitride semiconductor is different. The resulting stress can be reduced.

It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 1st Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 1st Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 2nd Embodiment. It is sectional drawing for demonstrating the processing method of the semiconductor substrate which concerns on 3rd Embodiment. It is sectional drawing for demonstrating the processing method of the semiconductor substrate which concerns on 3rd Embodiment. It is sectional drawing for demonstrating the processing method of the semiconductor substrate which concerns on 3rd Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 4th Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 4th Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 5th Embodiment. It is sectional drawing which shows the processing method of the semiconductor substrate which concerns on 5th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 8th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  1 and 2 are cross-sectional views illustrating a semiconductor substrate processing method according to the first embodiment. In this semiconductor substrate processing method, first, an SOI (Silicon On Insulator) substrate is prepared. The SOI substrate is a substrate in which an insulating layer 120 and a silicon layer 200 are stacked on a silicon substrate 100 having a (111) surface. The silicon layer 200 has a surface orientation other than the (111) plane. Next, an opening 201 in which the silicon substrate 100 is exposed on the bottom surface is formed in the insulating layer 120 and the silicon layer 200. Next, a group III nitride semiconductor layer 300 is formed in the opening 201. This will be described in detail below.

  First, as shown in FIG. 2A, an SOI substrate is prepared. As described above, the SOI substrate is a substrate in which the insulating layer 120 and the silicon layer 200 are stacked in this order on the silicon substrate 100. The surface orientation of the surface of the silicon layer 200 is, for example, (100) or (110).

  Next, a hard mask layer 202 is formed on the silicon layer 200. The hard mask layer 202 is a silicon oxide layer, for example, and is formed by, for example, a CVD method.

  Next, as shown in FIG. 2B, a resist pattern (not shown) is formed on the hard mask layer 202, and the hard mask layer 202, the silicon layer 200, and the insulating layer 120 are etched using the resist pattern as a mask. . Thus, an opening 201 is formed in the hard mask layer 202, the silicon layer 200, and the insulating layer 120. The opening 201 exposes the silicon substrate 100 on the bottom surface. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 1A, the silicon substrate 100 exposed on the bottom surface of the opening 201 is cleaned by being heated to 1000 ° C. or higher and then placed in a hydrogen atmosphere. Next, the buffer layer 302 and the nitride semiconductor layer 300 are formed in this order on the silicon substrate 100 exposed at the bottom surface of the opening 201. The nitride semiconductor layer 300 is, for example, GaN, AlGaN, or InAlGaN. Since the surface orientation of the surface of the silicon substrate 100 is (111), the nitride semiconductor layer 300 grows so that the surface becomes a (0001) plane.

  In this embodiment, the buffer layer 302 and the nitride semiconductor layer 300 are selectively grown on the silicon substrate 100 exposed at the bottom surface of the opening 201 by a selective CVD method. The buffer layer 302 is a polycrystalline layer of a nitride semiconductor such as GaN or a polycrystalline layer of AlN. The buffer layer 302 is lower in temperature (for example, 500 ° C. or lower) than the film formation temperature of the nitride semiconductor layer 300 (for example, 1000 ° C. or higher and 1200 ° C. or lower). A film is formed.

  Thereafter, as shown in FIG. 1B, the hard mask layer 202 is removed by, for example, wet etching. When the nitride semiconductor layer 300 is formed, a poorly selected foreign material may grow on the hard mask layer 202. The foreign matter is removed from the SOI substrate together with the hard mask layer 202 when the hard mask layer 202 is removed.

  The SOI substrate formed in this manner is formed on the silicon substrate 100 having a (111) surface, the insulating layer 120 formed on the silicon substrate 100, and the insulating layer 120. An opening 201 formed in the silicon layer 200 having a plane orientation other than the (111) plane, the insulating layer 120 and the silicon layer 200 and exposing the silicon substrate 100 on the bottom surface, and a nitride formed in the opening 201. And a semiconductor layer 300. As described in other embodiments described later, in this SOI substrate, a silicon element such as a MOS transistor is formed in the silicon layer 200, and a nitride semiconductor layer 300 includes a MES transistor, HEMT, bipolar transistor, Alternatively, a compound semiconductor element such as a light emitting element is formed.

  Next, the operation and effect of this embodiment will be described. According to this embodiment, the insulating layer 120 and the silicon layer 200 are formed on the silicon substrate 100 whose surface is the (111) plane. The silicon layer 200 has a surface orientation other than the (111) plane. An opening 201 is formed in the insulating layer 120 and the silicon layer 200, and the silicon substrate 100 is exposed on the bottom surface of the opening 201. The nitride semiconductor layer 300 is formed in the opening 100. For this reason, the silicon layer 200 whose surface is other than the (111) plane and the nitride semiconductor layer 300 whose surface is the (0001) plane can be provided on the SOI substrate. In addition, since the nitride semiconductor layer 300 is formed only on a part of the silicon substrate 100, it is possible to reduce stress due to a difference in linear expansion coefficient between silicon and the nitride semiconductor.

  Further, when the nitride semiconductor layer 300 is selectively grown, the hard mask layer 202 is formed on the silicon layer 200. The hard mask layer 202 is removed after the nitride semiconductor layer 300 is formed. For this reason, even when a poorly selected foreign material is generated in a portion other than the opening 201 when the nitride semiconductor layer 300 is formed, the foreign material is removed together with the hard mask layer 202 when the hard mask layer 202 is removed. It is removed from the SOI substrate.

  FIG. 3 is a cross-sectional view illustrating a semiconductor substrate processing method according to the second embodiment. This semiconductor substrate processing method is different from the first embodiment in the method of forming the nitride semiconductor layer 300.

  First, as shown in FIG. 3A, an SOI substrate having a silicon substrate 100, an insulating layer 120, and a silicon layer 200 is prepared. Next, a hard mask layer 202 and an opening 201 are formed. The method for forming the hard mask layer 202 and the opening 201 is the same as in the first embodiment.

  Next, the buffer layer 302 and the nitride semiconductor layer 300 are formed in this order in the opening 201. In this step, the selective growth method is not used to form the buffer layer 302 and the nitride semiconductor layer 300. Therefore, the buffer layer 302 and the nitride semiconductor layer 300 are also formed on the hard mask layer 202.

  The buffer layer 302 may be the same as that in the first embodiment, or may be a multilayer film in which AlN films and AlGaN films are alternately stacked.

  Next, as shown in FIG. 3B, the buffer layer 302 and the nitride semiconductor layer 300 located on the hard mask layer 202 are removed by etching. Thereafter, the hard mask layer 202 is removed by wet etching.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. When removing the nitride semiconductor layer 300, the silicon layer 200 is covered with the hard mask layer 202. For this reason, it can suppress that the silicon layer 200 receives a damage by an etching.

  Each of FIGS. 4 to 6 is a cross-sectional view for explaining a semiconductor substrate processing method according to the third embodiment. This semiconductor substrate processing method is a method of forming a MOS transistor 210 and a MES (Metal-Semiconductor-Field-Effect-Transistor) transistor 310 on an SOI substrate.

  First, as shown in FIG. 4A, an SOI substrate having a silicon substrate 100, an insulating layer 120, and a silicon layer 200 is prepared. Next, the hard mask layer 202, the opening 201, and the buffer layer 302 are formed. The formation method of the hard mask layer 202, the opening 201, and the buffer layer 302 is the same as that in the first embodiment. In the present embodiment, the surface of the silicon layer 200 is preferably a (100) plane or a (110) plane.

  Next, an intrinsic type nitride semiconductor layer 300 and a first conductivity type (for example, n-type) nitride semiconductor layer 311 are formed in this order. The nitride semiconductor layer 311 is a channel layer of the MES transistor 310. The method for forming the nitride semiconductor layer 300 and the nitride semiconductor layer 311 is the same as the method for forming the nitride semiconductor layer 300 in the first embodiment.

  Thereafter, as shown in FIG. 4B, the hard mask layer 202 is removed by wet etching.

  Next, as shown in FIG. 5A, a mask film 204 is formed on the nitride semiconductor layer 311. The mask film 204 is a silicon oxide film, for example, and is selectively formed on the nitride semiconductor layer 311 by etching using a resist pattern after being formed by a CVD method.

  Next, as shown in FIG. 5B, the silicon layer 200 is selectively removed to form a trench for element isolation, and an insulating film (for example, a silicon oxide film) is embedded in the trench. Thereby, the element isolation insulating film 206 is formed.

  Thereafter, as shown in FIG. 6A, a gate insulating film 212 of a MOS transistor is formed on the silicon layer 200. The gate insulating film 212 may be formed by a thermal oxidation method or may be formed by film formation. Next, a conductive film is formed over the silicon layer 200, the gate insulating film 212, and the nitride semiconductor layer 311, and the conductive film is selectively removed. As a result, the gate electrode 314 of the MES transistor 310 is formed on the nitride semiconductor layer 311, and the gate electrode 214 of the MOS transistor is formed on the gate insulating film 212.

  Thereafter, as shown in FIG. 6B, an ohmic electrode layer 312 of the MES transistor 310 is formed. Thereby, the MES transistor 310 is formed. Thereafter, the MES transistor 310 is covered with a mask film (not shown). Next, an extension region 217 of the MOS transistor 210 is formed by introducing impurities into the silicon layer 200. Thereafter, sidewalls 215 of the MOS transistor 210 are formed, and further source / drain regions 216 of the MOS transistor 210 are formed. Thereafter, the mask film covering the MES transistor 310 is removed.

  The semiconductor device thus formed has a MOS transistor 210 as a silicon element in the silicon layer 200 and a MES transistor 310 as a compound semiconductor element in the nitride semiconductor layer 300.

  According to the present embodiment, the MOS transistor 210 as the silicon element and the MES transistor 310 as the compound semiconductor element can be formed on the SOI substrate. At this time, similarly to the first embodiment, the surface of the nitride semiconductor layer 300 can be a (0001) plane, and therefore, the characteristics of the MES transistor 310 can be prevented from being deteriorated.

  In addition, since the MOS transistor 210 is formed after the nitride semiconductor layers 300 and 311 of the MES transistor 310 are formed, the impurity profile of the MOS transistor 210 is changed by heat in the process of forming the nitride semiconductor layers 300 and 311. Can be prevented.

  7 and 8 are cross-sectional views illustrating a semiconductor substrate processing method according to the fourth embodiment. This semiconductor substrate processing method is the same as the semiconductor substrate processing method according to the third embodiment except for the method of forming the nitride semiconductor layer 300.

  First, as shown in FIG. 7A, an SOI substrate having a silicon substrate 100, an insulating layer 120, and a silicon layer 200 is prepared. Next, a hard mask layer 202 and an opening 201 are formed. The method for forming the hard mask layer 202 and the opening 201 is the same as in the third embodiment.

  Next, an island-shaped insulating layer 304 is formed over the silicon substrate 100 located on the bottom surface of the opening 201. The insulating layer 304 is a silicon oxide film, for example. The insulating layer 304 is formed, for example, by forming an insulating layer on the entire surface of the silicon substrate 100 located on the bottom surface of the opening 201 and then selectively removing the insulating layer.

  Next, the buffer layer 302 is formed lower than the insulating layer 304. The method for forming the buffer layer 302 is the same as in the third embodiment.

  Next, as shown in FIGS. 7B and 8A, a nitride semiconductor layer 300 is formed on the buffer layer 302 by selective growth. At this time, the nitride semiconductor layer 300 first grows upward between the island-shaped insulating layers 304, and then grows laterally after becoming higher than the insulating layer 304. For this reason, crystal defects formed in the initial stage of film formation run in the lateral direction, and it is difficult to reach the surface of the nitride semiconductor layer 300.

  Next, as illustrated in FIG. 8B, a first conductivity type nitride semiconductor layer 311 is formed on the nitride semiconductor layer 300. Since the subsequent steps are the same as those in the third embodiment, the description thereof is omitted.

  According to this embodiment, the same effect as that of the third embodiment can be obtained. In addition, since crystal defects on the surface of the nitride semiconductor layer 300 can be reduced, variation in characteristics of the MES transistor 310 can be suppressed.

  9 and 10 are cross-sectional views illustrating a semiconductor substrate processing method according to the fifth embodiment. This semiconductor substrate processing method is the same as the third method except that the sidewall 306 is formed on the side surface of the opening 201 after the opening 201 is formed and before the buffer layer 302 and the nitride semiconductor layer 300 are formed. This is the same as the semiconductor substrate processing method according to the embodiment. This will be described in detail below.

  First, as shown in FIG. 9A, an SOI substrate having a silicon substrate 100, an insulating layer 120, and a silicon layer 200 is prepared. Next, a hard mask layer 202 and an opening 201 are formed. The method for forming the hard mask layer 202 and the opening 201 is the same as in the third embodiment.

  Next, an insulating film is formed in the opening 201 and on the hard mask layer 202. The insulating film includes, for example, at least one of a silicon oxide film and a silicon nitride film. Next, this insulating film is etched. Thereby, a sidewall 306 is formed on the side surface of the opening 201. The sidewall 306 covers at least a region of the side surface of the opening 201 where the silicon layer 200 is exposed.

  Thereafter, as shown in FIG. 9B, a buffer layer 302, a nitride semiconductor layer 300, and a first conductivity type nitride semiconductor layer 311 are formed. These forming methods are the same as those in the third embodiment.

  Thereafter, as shown in FIG. 10, the MES transistor 310 and the MOS transistor 210 are formed. These forming methods are the same as those in the third embodiment.

  According to this embodiment, the same effect as that of the third embodiment can be obtained. Further, the sidewall 306 covers at least a region of the side surface of the opening 201 where the silicon layer 200 is exposed. For this reason, the MES transistor 310 and the silicon layer 200 can be reliably insulated.

  FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to the sixth embodiment. This semiconductor device has CMOS transistors 220 and 230 and a HEMT (High Electron Mobility Transistor) 320.

  The CMOS transistors 220 and 230 have gate insulating films 222 and 232, gate electrodes 224 and 234, sidewalls 225 and 235, source / drain regions 226 and 236, and extension regions 227 and 237, respectively.

  The HEMT 320 includes an intrinsic type nitride semiconductor layer 300, a first conductivity type (for example, n-type) nitride semiconductor layer 321 and a nitride semiconductor layer 322, a gate electrode 323, and an ohmic electrode located on the nitride semiconductor layer 300. It has a layer 324.

  The nitride semiconductor layer 321 is a channel layer. The nitride semiconductor layer 322 is a first conductivity type semiconductor layer having a higher impurity concentration than the nitride semiconductor layer 321, and is located between the gate electrode 323 and the nitride semiconductor layer 321. The nitride semiconductor layer 322 is a carrier supply layer and is formed on a part of the nitride semiconductor layer 321. Two ohmic electrode layers 324 are formed on the nitride semiconductor layer 321 so as to sandwich the gate electrode 323 and the nitride semiconductor layer 322.

  A method for forming a semiconductor device according to this embodiment is as follows. First, an SOI substrate having the silicon substrate 100, the insulating layer 120, and the silicon layer 200 is prepared. Next, the hard mask layer 202, the opening 201, the buffer layer 302, the nitride semiconductor layer 300, the nitride semiconductor layer 321, and the nitride semiconductor layer 322 illustrated in FIG. 4 and the like are formed in this order. These forming methods are the same as those in the third embodiment. Note that the nitride semiconductor layer 322 is selectively removed except for a necessary region.

  Thereafter, the hard mask layer 202 is removed by wet etching. Thereafter, an element isolation insulating film 206 is formed. Next, gate insulating films 222 and 232 of the CMOS transistors 220 and 230, a gate electrode 323 of the HEMT, and gate electrodes 224 and 234 of the CMOS transistors 220 and 230 are formed. These forming methods are the same as those in the third embodiment.

  Thereafter, an ohmic electrode layer 324 is formed. Thereby, the HEMT 320 is formed. Thereafter, the HEMT 320 is covered with a mask film (not shown). Next, extension regions 227 and 237, sidewalls 225 and 235, and source / drain regions 226 and 236 of the CMOS transistors 220 and 230 are formed. These forming methods are the same as those in the third embodiment. Thereafter, the mask film covering HEMT 320 is removed.

  According to this embodiment, the same effect as that of the third embodiment can be obtained. In this embodiment, the sidewall 306 shown in the fifth embodiment may be provided.

  FIG. 12 is a cross-sectional view showing the configuration of the semiconductor device according to the seventh embodiment. This semiconductor device is the same as that of the sixth embodiment except that a bipolar transistor 330 is provided instead of the HEMT 320.

  The bipolar transistor 330 has a structure in which a first conductivity type collector layer 331, a second conductivity type base layer 332, and a first conductivity type emitter layer 333 are stacked in this order on an intrinsic type nitride semiconductor layer 300. It is. The collector layer 331, the base layer 332, and the emitter layer 333 are each a nitride semiconductor layer.

  The manufacturing method of this semiconductor device is as follows. First, an SOI substrate having the silicon substrate 100, the insulating layer 120, and the silicon layer 200 is prepared. Next, the hard mask layer 202, the opening 201, the buffer layer 302, the nitride semiconductor layer 300, the collector layer 331, the base layer 332, and the emitter layer 333 shown in FIG. 4 and the like are formed in this order. These forming methods are the same as those in the third embodiment. Next, the base layer 332 and the emitter layer 333 are selectively removed except for a necessary region.

  Thereafter, the hard mask layer 202 is removed by wet etching. Thereafter, the bipolar transistor 330 is covered with a mask film (not shown). Next, an element isolation insulating film 206 and CMOS transistors 220 and 230 are formed. These forming methods are the same as those in the sixth embodiment. Thereafter, the mask film covering the bipolar transistor 330 is removed.

  Also in this embodiment, the same effect as that in the sixth embodiment can be obtained. In this embodiment, the sidewall 306 shown in the fifth embodiment may be provided.

  FIG. 13 is a cross-sectional view showing the configuration of the semiconductor device according to the eighth embodiment. This semiconductor device is the same as that of the sixth embodiment except that a light emitting element 340 is provided instead of the HEMT 320. The light emitting element 340 is a semiconductor laser or LED.

  The light emitting element 340 includes a first conductive type nitride semiconductor layer 341, a light emitting layer 342, and a second conductive type nitride semiconductor layer 343 stacked in this order on a part of the first conductive type nitride semiconductor layer 300. This is the structure. When a necessary voltage is applied between the nitride semiconductor layer 300 and the nitride semiconductor layer 343, the light emitting layer 342 emits light.

  The manufacturing method of this semiconductor device is as follows. First, an SOI substrate having the silicon substrate 100, the insulating layer 120, and the silicon layer 200 is prepared. Next, the hard mask layer 202, the opening 201, the buffer layer 302, the nitride semiconductor layer 300, the nitride semiconductor layer 341, the light emitting layer 342, and the nitride semiconductor layer 343 shown in FIG. 4 and the like are formed in this order. These forming methods are the same as those in the third embodiment. Next, the nitride semiconductor layer 341, the light emitting layer 342, and the nitride semiconductor layer 343 are selectively removed except for necessary regions.

  Thereafter, the hard mask layer 202 is removed by wet etching. Thereafter, the light emitting element 340 is covered with a mask film (not shown). Next, an element isolation insulating film 206 and CMOS transistors 220 and 230 are formed. These forming methods are the same as those in the sixth embodiment. Thereafter, the mask film covering the light emitting element 340 is removed.

  Also in this embodiment, the same effect as that in the sixth embodiment can be obtained. In this embodiment, the sidewall 306 shown in the fifth embodiment may be provided.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable. For example, the manufacturing method of the semiconductor device shown in the third to eighth embodiments is not limited to the above example.

100 silicon substrate 120 insulating layer 200 silicon layer 201 opening 202 hard mask layer 204 mask film 206 element isolation insulating film 210 MOS transistor 212 gate insulating film 214 gate electrode 215 sidewall 216 source / drain region 217 extension region 220 CMOS transistor 222 gate Insulating film 224 Gate electrode 225 Side wall 226 Source / drain region 227 Extension region 230 CMOS transistor 232 Gate insulating film 234 Gate electrode 235 Side wall 236 Source / drain region 237 Extension region 300 Nitride semiconductor layer 302 Buffer layer 304 Insulating layer 306 Side Wall 310 MES transistor 311 Nitride semiconductor layer 312 Ohmic electrode layer 31 The gate electrode 320 HEMT
321 Nitride semiconductor layer 322 Nitride semiconductor layer 323 Gate electrode 324 Ohmic electrode layer 330 Bipolar transistor 331 Collector layer 332 Base layer 333 Emitter layer 340 Light emitting element 341 Nitride semiconductor layer 342 Light emitting layer 343 Nitride semiconductor layer

Claims (14)

A silicon substrate whose surface is a (111) plane;
An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer and having a surface orientation other than the (111) plane;
An opening formed in the insulating layer and the silicon layer and exposing the silicon substrate on a bottom surface;
A group III nitride semiconductor layer formed in the opening;
A silicon element formed in the silicon layer;
A compound semiconductor element formed in the nitride semiconductor layer;
A semiconductor device comprising: The semiconductor device according to claim 1,
The silicon layer is a semiconductor device whose surface is a (100) plane or a (110) plane. The semiconductor device according to claim 1 or 2,
The semiconductor device in which the silicon element is a MOS transistor and the compound semiconductor element is a MES transistor, HEMT, bipolar transistor, or light emitting element. In the semiconductor device as described in any one of Claims 1-3,
A semiconductor device having an insulating coating layer that covers at least a region of the side surface of the opening where the silicon layer is exposed. The semiconductor device according to claim 4,
The semiconductor device, wherein the insulating coating layer includes at least one of a silicon oxide layer and a silicon nitride layer. A silicon substrate whose surface is a (111) plane;
An insulating layer formed on the silicon substrate;
A silicon layer formed on the insulating layer and having a surface orientation other than the (111) plane;
An opening formed in the insulating layer and the silicon layer and exposing the silicon substrate on a bottom surface;
A group III nitride semiconductor layer formed in the opening;
A semiconductor substrate. Preparing an SOI (Silicon On Insulator) substrate in which an insulating layer and a silicon layer having a surface orientation other than the (111) plane are laminated on a silicon substrate having a (111) plane surface;
Forming an opening in the bottom surface of the insulating layer and the silicon layer where the silicon substrate is exposed;
Forming a group III nitride semiconductor layer in the opening;
A method for processing a semiconductor substrate comprising: In the processing method of the semiconductor substrate according to claim 7,
After the step of forming the nitride semiconductor layer,
A method for processing a semiconductor substrate, comprising: forming a silicon element on the silicon layer; and forming a compound semiconductor element on the nitride semiconductor layer. In the processing method of the semiconductor substrate according to claim 8,
A method for processing a semiconductor substrate, wherein the compound semiconductor element is formed on the nitride semiconductor layer and then the silicon element is formed on the silicon layer. In the processing method of the semiconductor substrate according to any one of claims 7 to 9,
The method for processing a semiconductor substrate, wherein the silicon layer has a (100) plane or a (110) plane. In the processing method of the semiconductor substrate according to any one of claims 7 to 10,
The step of forming the nitride semiconductor layer is a method of processing a semiconductor substrate, which is a step of selectively growing the nitride semiconductor layer on the silicon substrate exposed at a bottom surface of the opening. In the processing method of the semiconductor substrate according to any one of claims 7 to 10,
The step of forming the nitride semiconductor layer includes
Forming the nitride semiconductor layer in the opening and on the silicon layer;
Removing the nitride semiconductor layer located on the silicon layer;
A method for processing a semiconductor substrate comprising: In the processing method of the semiconductor substrate according to claim 11 or 12,
A step of forming a hard mask layer on the silicon layer before the step of forming the opening;
A method for processing a semiconductor substrate, comprising a step of removing the hard mask layer after the step of forming the nitride semiconductor layer. In the processing method of the semiconductor substrate as described in any one of Claims 7-13,
After the step of forming the opening, and before the step of forming the nitride semiconductor layer, a step of forming an insulating coating layer that covers at least the region where the silicon layer is exposed on the sidewall of the opening A method for processing a semiconductor substrate comprising:

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