JP2011035048A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem in a BEOL process of manufacturing an LSI having aluminum-based normal wiring mainly, wherein the occurrence of the expansion or chipping of a wiring metal film, among defects relating to aluminum-based wiring, becomes the cause of greatly degrading an EM resistance and an SM resistance for the fact that the improvement of the EM resistance and the SM resistance is especially important relating to the reliability of wiring. <P>SOLUTION: On the wafer stage of a plasma CVD chamber for forming an interlayer dielectric, plasma annealing treatment is executed at a wafer temperature higher than the film formation temperatures of the aluminum-based wiring metal film and the interlayer dielectric under an atmosphere including an inert gas as one of main components to the device surface of a wafer after patterning an aluminum-based wiring metal film and before forming the interlayer dielectric. Thus, deposits on the sidewall of a wiring metal layer are completely removed, and the cause of an expansion defect is removed. Further, by the progress of passivation and stress release, etc., a chipping defect is suppressed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to an aluminum-based wiring forming technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  Japanese Laid-Open Patent Publication No. 2004-288863 (Patent Document 1) describes a process for forming an aluminum-based metal multilayer wiring having an interlayer insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) for LSI (Large Scale Integration). In order to prevent the formation of wiring voids after the patterning of the aluminum-based metal wiring layer and before coating with the interlayer insulating film, in the hydrogen atmosphere, the aluminum sputtering temperature and the subsequent interlayer insulating film forming temperature A technique for heat treatment using a normal heat treatment furnace at about 420 degrees Celsius is disclosed.

  Japanese Laid-Open Patent Publication No. 2003-332338 (Patent Document 2) discloses a process for forming an aluminum-based metal multilayer wiring having an interlayer insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) for LSI (Large Scale Integration). In order to prevent the formation of wiring voids after the patterning of the aluminum-based metal wiring layer and before the coating with the interlayer insulating film, the aluminum sputtering temperature and the subsequent interlayer insulation are performed in an oxygen-free non-oxidizing atmosphere. A technique is disclosed in which heat treatment is performed using a normal heat treatment furnace at a temperature higher than the film formation temperature.

  Japanese Unexamined Patent Publication No. 2007-128976 (Patent Document 3) describes a bipolar transistor or the like after patterning of an aluminum-based metal electrode in order to prevent a plasma PSG (Phospho-Silicate Glass) film from being cracked. A technique is disclosed in which heat treatment is performed at a temperature of 350 degrees Celsius to 450 degrees Celsius in a nitrogen atmosphere or an oxygen atmosphere before forming the PSG film.

JP 2004-288863 A JP 2003-332338 A JP 2007-128976 A

  In the manufacturing process of an LSI having a multilayer wiring mainly composed of aluminum-based normal wiring, that is, in the BEOL (Back End of Line) process in the wafer process, with regard to wiring reliability, EM (Electro-Migration) resistance and SM ( It is particularly important to improve the resistance to stress migration. Among the defects related to the aluminum-based wiring, the expansion or chipping of the wiring metal film is a factor that greatly deteriorates the EM resistance and SM resistance.

  According to the study of the failure mode such as expansion and chipping of the wiring metal film, the following points have been clarified. That is, the expansion failure of the wiring metal film is caused by the fact that the passivation due to the subsequent ashing process does not sufficiently proceed due to the adhering component adhering to the side wall of the wiring metal layer during the patterning of the aluminum-based wiring metal layer. This is because gas components remaining on the side walls of the wiring metal layer are discharged due to thermal stress during the film formation.

  On the other hand, chipping defects in the wiring metal film are caused by passivation of the sidewalls of the wiring metal layer, etc., when the wiring metal is covered with the interlayer insulating film or due to thermal stress in the subsequent process. As a result of stress relaxation occurring in the grain portion of the insufficient portion, chipping is generated.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, on the wafer stage of the plasma CVD chamber for forming the interlayer insulating film, the wafer is formed after the patterning of the aluminum-based wiring metal film and before the formation of the interlayer insulating film. A plasma annealing process is performed at a wafer temperature higher than the deposition temperature of the aluminum wiring metal film and the interlayer insulating film in an atmosphere containing an inert gas as one of the main components on the device surface of It is.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, on the wafer stage of the plasma CVD chamber for forming the interlayer insulating film, after the patterning of the aluminum-based wiring metal film and before the formation of the interlayer insulating film, In an atmosphere containing an inert gas as one of the main components, plasma annealing is performed at a wafer temperature higher than the deposition temperature of the aluminum-based wiring metal film and the interlayer insulating film, thereby forming the interlayer insulating film. It is possible to prevent the gas component remaining on the side wall of the wiring metal layer from being discharged due to thermal stress during film formation, and as a result, it is possible to suppress poor expansion.

1 is a plan layout view of a multi-chamber type wafer processing apparatus including a plurality of HDP-CVD chambers used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. FIG. FIG. 2 is a front sectional view of the HDP-CVD chamber of FIG. 1. FIG. 3 is a schematic cross-sectional configuration diagram of the entire wafer cooling system of the HDP-CVD chamber of FIG. 2. FIG. 4 is a top view of the wafer stage showing an area between the wafer back surface and the wafer stage that each section of the wafer cooling system of FIG. 3 takes charge of. 1 is a general cross-sectional structure diagram of a device manufactured by a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. It is a process block flow diagram of a unit wiring layer in a method for manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. Device cross-sectional process flow diagram of unit wiring layer (second layer wiring is taken as an example) in the method for manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application (when the first layer wiring is completed) ). Device cross-sectional process flow diagram (lower layer barrier metal film formation) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application At the time of membrane). Device cross-sectional process flow diagram (aluminum-based wiring metal film formation) of a unit wiring layer (second-layer wiring is taken as an example) in a manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application At the time of membrane). Device cross-sectional process flow diagram (upper layer barrier metal film formation) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application At the time of membrane). Device cross-sectional process flow diagram (when antireflection film is formed) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application ). Device cross-sectional process flow diagram (at time of photo resist film application) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application ). Device cross-section process flow diagram (photo resist film development time point) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application ). Device cross-sectional process flow diagram (wiring metal film dry etching) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application At the time of completion). Device cross-sectional process flow diagram (photo resist film ashing removal) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application At the time of completion). FIG. 4 is a device cross-sectional process flow diagram (at the time of removal of the sidewall polymer) of a unit wiring layer (second layer wiring is taken as an example) in a manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application; (FIG. 21 to FIG. 21 correspond to the XX ′ cross section of FIG. 17). FIG. 17 is a top view of the wafer corresponding to FIG. 16. Device cross-sectional process flow diagram (at the time of completion of HDP-CVD) of a unit wiring layer (second layer wiring is taken as an example) in a method for manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application It is. Device cross-sectional process flow diagram (at the time of plasma TEOS film formation) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application ). FIG. 4 is a device cross-sectional process flow diagram (at the time of completion of CMP) of a unit wiring layer (second layer wiring is taken as an example) in a method for manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application; . Device cross-sectional process flow diagram (cap silicon oxide film formation) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application At the time of membrane). It is a process block flow diagram of an interlayer film forming peripheral process group which is a main process of a manufacturing method of a semiconductor integrated circuit device (a product of aluminum-based normal wiring) according to an embodiment of the present application. FIG. 23 is a process block flow diagram showing a specific example of a detailed configuration of the plasma annealing step of FIG. 22. FIG. 23 is a wafer temperature change schematic diagram showing a change in wafer temperature in the interlayer film forming peripheral process group of FIG. 22; 23 is a chart summarizing processing conditions and the like of each step in the interlayer film forming peripheral process group of FIG.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a multilayer wiring metal film including an aluminum-based wiring metal film on the first main surface of the wafer at a first wafer temperature;
(B) patterning the multilayer wiring metal film including the aluminum-based wiring metal film on the first main surface of the wafer;
(C) after the step (a), setting the wafer on a wafer stage in a first plasma CVD chamber;
(D) A first atmosphere containing an inert gas as one of main components with respect to the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber. Performing a first plasma surface treatment at a second wafer temperature higher than the first wafer temperature;
(E) After the step (d), the temperature of the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber is lower than the second wafer temperature. A step of performing an interlayer insulating film forming process by a first plasma CVD process at a third wafer temperature.

  2. In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first atmosphere includes oxygen gas as one of main components.

3. The method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2 further includes the following steps:
(F) The first main surface of the wafer set on the wafer stage in the first plasma CVD chamber after the step (c) and before the step (d) On the other hand, a step of performing the second plasma surface treatment in a second atmosphere containing an inert gas as one of main components at a fourth wafer temperature lower than the first wafer temperature.

  4). In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the second atmosphere does not substantially contain oxygen.

5). The method for manufacturing a semiconductor integrated circuit device according to the item 3 or 4 further includes the following steps:
(G) After the step (f) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber On the other hand, the third plasma surface treatment is performed in a third atmosphere containing an inert gas and an oxygen gas as one of the main components at a fifth wafer temperature lower than the first wafer temperature. Process.

  6). In the method of manufacturing a semiconductor integrated circuit device according to the item 5, the fourth wafer temperature and the fifth wafer temperature are substantially the same.

7). The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 6 further includes the following steps:
(H) After the step (e), the temperature of the wafer set on the wafer stage in the first plasma CVD chamber is changed from the third wafer temperature to the first wafer temperature. Lowering the temperature to a lower sixth wafer temperature or lower.

  8). In the method of manufacturing a semiconductor integrated circuit device according to the item 7, the sixth wafer temperature is 200 degrees Celsius.

  9. 9. In the method of manufacturing a semiconductor integrated circuit device according to the item 7 or 8, the average temperature drop rate between 300 degrees Celsius and 200 degrees Celsius in the step (h) is 2 degrees / second or more and 5 degrees / second or less. .

  10. In the method for manufacturing a semiconductor integrated circuit device according to any one of 7 to 9, the plasma is in a lighting state in the step (h).

11. 11. The method for manufacturing a semiconductor integrated circuit device according to any one of 5 to 10 further includes the following steps:
(I) After the step (g) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber In contrast, in a fourth atmosphere containing an inert gas as one of the main components, the temperature of the wafer is raised from the fifth wafer temperature to the second wafer temperature. A step of performing plasma surface treatment.

  12 12. In the method of manufacturing a semiconductor integrated circuit device according to the item 11, the fourth atmosphere includes oxygen gas as one of main components.

  13. 13. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 12, the interlayer insulating film is a silicon oxide insulating film formed by HDP-CVD.

14 14. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 13, further including the following steps:
(J) After the step (b) including the removal of the resist film and the polymer, and before the step (c), the first atmosphere is included in a fifth atmosphere containing oxygen gas as one of main components. Performing a fifth plasma surface treatment at a seventh wafer temperature lower than the wafer temperature;

  15. In the method for manufacturing a semiconductor integrated circuit device according to the item 14, the step (j) is not performed in the first plasma CVD chamber.

  16. 16. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 15, the second wafer temperature is not less than 350 degrees Celsius and not more than 450 degrees Celsius.

  17. 17. In the method for manufacturing a semiconductor integrated circuit device according to any one of 3 to 16, the fourth wafer temperature is not less than 150 degrees Celsius and not more than 270 degrees Celsius.

  18. 18. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 17, the third wafer temperature is not less than 320 degrees Celsius and not more than 370 degrees Celsius.

19. The method for manufacturing a semiconductor integrated circuit device according to the item 3 or 4 further includes the following steps:
(G) After the step (f) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber On the other hand, the third plasma surface treatment is performed in a third atmosphere containing inert gas and nitrogen gas as one of the main components, at a fifth wafer temperature lower than the first wafer temperature. Process.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor integrated circuit device” mainly refers to a device in which resistors, capacitors, and the like are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate) with a focus on various transistors (active elements). . Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, an LSI (Large Scale Integration) wafer process, is usually performed from the introduction of a silicon wafer as a raw material to a pre-metal process (interlayer between the lower end of the M1 wiring layer and the gate electrode structure). Starting from the formation of insulating film, contact hole formation, tungsten plug, embedding, etc. (FEOL (Front End of Line) process) and M1 wiring layer formation, final passivation on the aluminum-based pad electrode The process can be roughly divided into BEOL (Back End of Line) processes up to the formation of pad openings in the film (including the process in the wafer level package process).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS), etc., coating system silicon oxide, silica-based low-k insulating film (porous) with pores introduced in the same material Needless to say, it includes a composite insulating film and other silicon-based insulating films having these as main components.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  SiC has properties similar to those of SiN, but SiON used for an antireflection film or the like should rather be classified as a silicon oxide insulating film in many cases.

  The silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, and also used as a stress applying film in SMT (Stress Memory Technique).

  Similarly, “aluminum wiring”, “aluminum-based wiring metal”, etc., usually contain not only high-purity aluminum but also 0.5 to 5% by weight of copper, silicon, and other additives. ing. In addition, it is common to have a plurality of auxiliary metal layers (further additional insulating antireflection films and the like) above and below.

  Furthermore, as for the gas composition, “inert gas atmosphere” is not limited to argon or helium, but other general-purpose additive gases, that is, hydrogen, oxygen, nitrogen, etc. Addition and inclusion are allowed.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). “Wafer temperature” is the temperature of the wafer measured by a pyrometer. The “stage temperature” is a set temperature of the wafer stage on which the wafer is placed. In heating, the stage temperature is generally slightly lower than the wafer temperature. In the wafer processing apparatus used in the following embodiments, the stage itself does not have a heating temperature adjustment mechanism, and the heating is solely based on the heat from the plasma above the wafer. The temperature of the wafer is controlled by the balance between the heat from the plasma and the cooling helium gas flow supplied from below the wafer.

  7. “Plasma surface treatment” means that a wafer is introduced into a plasma reaction chamber, and a physical or chemical treatment is performed on the surface of the wafer or the vicinity thereof by active species excited by plasma. Specifically, plasma cleaning, plasma oxidation, plasma nitridation, plasma reduction, plasma annealing and the like are typical. HDP-CVD is “plasma treatment” or “plasma film formation treatment”, but is not “plasma surface treatment” here.

  Although only the main atmosphere has been described in the plasma treatment, various gases can be added as long as they do not interfere with the process (unless safety and characteristics are deteriorated). Given these points, addition of nitrogen, oxygen, hydrogen, inert gas, etc. is generally allowed for various purposes.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of HDP-CVD apparatus used for manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (mainly FIGS. 1 to 4)
First, an HDP-CVD apparatus used in an interlayer film deposition peripheral process group which is a main process of the method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application will be described.

  FIG. 1 is a plan layout view of a multi-chamber type wafer processing apparatus incorporating a plurality of HDP-CVD chambers used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 2 is a front sectional view of the HDP-CVD chamber of FIG. FIG. 3 is a schematic cross-sectional configuration diagram of the entire wafer cooling system of the HDP-CVD chamber of FIG. FIG. 4 is a top view of the wafer stage showing the area between the wafer back surface and the wafer stage that each section of the wafer cooling system of FIG. 3 takes charge of.

  First, a planar layout of the multi-chamber type wafer processing apparatus 51 will be described with reference to FIG. As shown in FIG. 1, a multi-chamber type wafer processing apparatus 51 is provided with a plurality of load ports 52, in which a hoop (sealed wafer transfer container) 53 containing a plurality of wafers 1 is provided. It can be set. The hoop 53 set in the load port 52 is docked with the local cleaning chamber 54, and the wafer 1 in the hoop 53 is placed in any of the plurality of load lock chambers 55 by the load / unload robot 59 in the local cleaning chamber 54. Then, the vacuum is transferred to the vacuum transfer robot 58 in the vacuum transfer chamber 56. The vacuum transfer robot 58 introduces the received wafer 1 into any of the plasma processing chambers (plasma CVD chambers) 57a, 57b, 57c (each chamber has substantially the same function). When the series of processing 121 (FIG. 22) is completed, the wafer 1 follows a path opposite to that at the time of introduction and is returned to the FOUP 53.

  Next, the outline of the structure and function of the plasma processing chamber 57a in FIG. 1 (the other chambers have substantially the same structure and function) will be described with reference to FIG. As shown in FIG. 2, the outer wall 61 of the plasma processing chamber 57a has a portion on the upper dome substantially made of ceramic, and the base portion from the middle to the bottom is made of metal or the like whose main component is stainless steel or aluminum. Has been. The wafer 1 is introduced from the wafer loading / unloading gate 71 and set on the wafer stage (lower electrode) 62 in the plasma processing chamber 57a with its device surface 1a (first main surface) facing up. The lower electrode 62 is connected to a wafer-side bias high-frequency power source 63 (for example, 13.56 MHz) via a wafer-side bias capacitor 64. A cooling helium gas is supplied from a helium cooling system control unit 81 for cooling the back surface of the wafer 1. A plurality of gas introduction nozzles 69 for supplying a reaction gas and the like are provided around the wafer stage 62. Above the wafer stage 62, there is a portion where the plasma 41 is generated, and outside the portion of the outer wall 61 on the ceramic dome, there are a plasma excitation side antenna 66 and a plasma excitation top antenna 68. The antenna is connected to a side antenna high-frequency power source 65 (for example, 2 MHz) and a top antenna high-frequency power source 68 (for example, 2 MHz). Below the wafer stage 62, a main exhaust gate valve 70 and a turbo molecular pump 73 forming a part of the vacuum exhaust system are provided, and are connected to a dry roughing pump 74 by a main exhaust pipe 72. Further, a preliminary exhaust path including a preliminary exhaust pipe 75, a preliminary exhaust valve 76, and the like is provided in parallel with the main exhaust path. Further, a cleaning remote plasma excitation chamber 77 is provided outside the upper portion of the plasma processing chamber 57a. The activated fluorine species and the like excited here enter the plasma processing chamber 57a through the cleaning gas transfer pipe 78. It is designed to be transported. A gas introduction baffle 79 is provided in the upper end portion of the plasma processing chamber 57a.

  Next, the helium cooling system shown in FIG. 2 will be described with reference to FIGS. As shown in FIGS. 3 and 4, the helium cooling system supplies helium gas (for example, about 80 degrees Celsius) to the back surface 1 b of the wafer 1 to cool the wafer, thereby reducing the heat from the plasma 41. This is a system that controls the wafer 1 to a desired temperature in a balanced manner. The helium gas supplied from the helium gas source 82 is adjusted to a desired pressure in the wafer inner region helium gas pressure control system 83 and the wafer edge region helium gas pressure control system 84 in the helium cooling system control unit 81. Supplied to a wafer internal region helium gas supply pipe 87 and a wafer edge region helium gas supply pipe 88, which are two systems, through a wafer internal region helium gas supply valve 85 and a wafer edge region helium gas supply valve 86, respectively. Is done. The wafer inner area helium gas supply pipe 87 supplies helium gas to the wafer inner area 93 between the wafer stage and the wafer back surface, and the wafer edge area helium gas supply pipe 88 is supplied between the wafer stage and the wafer. Helium gas is supplied to the wafer edge region 94 between the back surfaces.

  The wafer stage 62 is provided with an electrostatic chuck 91 that electrostatically attracts the wafer 1.

2. Description of a general cross-sectional structure of a device manufactured by a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application (mainly FIG. 5)
In order to facilitate understanding of sections 3 and 4, a general cross-sectional structure (final passivation film) of a device manufactured by the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application The outline of the formation time) will be described. Here, for convenience of explanation, the four-layer wiring will be specifically described, but generally a wiring configuration of about three to eleven layers is widely used.

  FIG. 5 is a general cross-sectional structure diagram (for example, a 300 nm technology node product) of a device manufactured by the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application.

  As shown in FIG. 5, in the surface region of the semiconductor wafer (P-type single crystal silicon wafer) 1 on the device surface 1a (surface opposite to the back surface 1b), the source / drain regions 8 (impurity doped regions) of the MISFET, An STI (Shallow Trench Isolation) that electrically isolates a plurality of MISFETs is provided. A MISFET gate electrode structure 9 is formed on the device surface 1a (first main surface) of the wafer 1, and a pre-metal insulating film having a silicon oxide-based film as a main component so as to cover the gate electrode structure 9 is formed. 20 is provided. A tungsten-based contact plug 40 and a contact plug barrier metal 22 are embedded in the pre-metal insulating film 20. On this pre-metal insulating film 20, there are four wiring layers, that is, a first layer aluminum-based wiring layer M1, a second layer aluminum-based wiring layer M2, a third layer aluminum-based wiring layer M3, and a fourth layer. Aluminum-based wiring layers M4 are sequentially formed.

  The first-layer aluminum wiring layer M1 includes a first-layer multilayer wiring metal film 13 made of a lower barrier metal film (eg, TiN film), an aluminum wiring metal film, an upper barrier metal film (eg, TiN film), or the like. A first layer wiring region HDP-CVD silicon oxide-based interlayer insulating film 24, a first layer wiring region plasma TEOS silicon oxide-based interlayer insulating film 25, and a first layer wiring region plasma TEOS silicon oxide are provided so as to cover it. A first interlayer insulating film made of the system cap insulating film 26 or the like is formed. A first layer wiring region tungsten plug 15 and a barrier metal film 16 of the first layer wiring region tungsten plug are embedded in the first layer interlayer insulating film. Covering the first-layer multilayer wiring metal film 13 is a first-layer wiring antireflection film (CVD-SiON film) 44.

  The second-layer aluminum-based wiring layer M2 includes a second-layer multilayer wiring metal made of a lower barrier metal film 2 (for example, TiN film), an aluminum-based wiring metal film 5, an upper-layer barrier metal film 6 (for example, TiN film), etc. A film 3 is provided, and a second layer wiring region HDP-CVD silicon oxide based interlayer insulating film 14, a first layer wiring region plasma TEOS silicon oxide based interlayer insulating film 7, a first layer wiring region plasma are provided so as to cover the film 3 A second-layer interlayer insulating film made of a TEOS silicon oxide-based cap insulating film 11 or the like is formed. A second layer wiring region tungsten plug 27 and a barrier metal film 28 of the second layer wiring region tungsten plug are embedded in the second layer interlayer insulating film. Covering the second layer multilayer wiring metal film 23 is a second layer wiring antireflection film (CVD-SiON film) 18.

  The third-layer aluminum wiring layer M3 includes a third-layer multilayer wiring metal film 33 made of a lower barrier metal film (for example, TiN film), an aluminum-based wiring metal film, an upper barrier metal film (for example, TiN film), or the like. A third-layer wiring region HDP-CVD silicon oxide-based interlayer insulating film 35, a third-layer wiring region plasma TEOS-silicon oxide-based interlayer insulating film 36, and a third-layer wiring region plasma TEOS-silicon oxide are provided so as to cover them. A third interlayer insulating film made of a system cap insulating film 37 or the like is formed. A third layer wiring region tungsten plug 32 and a barrier metal film 34 of the third layer wiring region tungsten plug are buried in the third layer interlayer insulating film. Covering the third-layer multilayer wiring metal film 33 is a third-layer wiring antireflection film (CVD-SiON film) 45.

  The fourth-layer aluminum wiring layer M4 includes a fourth-layer multilayer wiring metal film 43 made of a lower barrier metal film (for example, TiN film), an aluminum-based wiring metal film, an upper-layer barrier metal film (for example, TiN film), or the like. The fourth layer wiring region HDP-CVD silicon oxide based in-layer insulating film 38, the fourth layer wiring region plasma TEOS silicon oxide based in-layer insulating film 39, the final passivation film 17 and the like are provided so as to cover it. An uppermost insulating film is formed. Covering the fourth-layer multilayer wiring metal film 43 is a fourth-layer wiring antireflection film (CVD-SiON film) 46.

3. Description of device cross-sectional process flow of unit wiring layer in manufacturing method of semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application (mainly FIGS. 6 to 21)
Here, the unit wiring layer in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (the second layer wiring is taken as an example, and the wiring layer portion of the via layer and the wiring layer will be described mainly). The device cross-section process flow will be described. Needless to say, the present invention can be applied as it is except for the second layer wiring.

  FIG. 6 is a process block flow diagram of a unit wiring layer in a method for manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. FIG. 7 is a device cross-sectional process flow diagram (first layer) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. Wiring completion). FIG. 8 is a device cross-sectional process flow diagram of the unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application (lower layer barrier (When the metal film is formed). FIG. 9 is a device cross-sectional process flow diagram (aluminum-based wiring) of a unit wiring layer (second-layer wiring is taken as an example) in the manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. Metal film formation time). FIG. 10 is a device cross-sectional process flow diagram (upper barrier barrier layer) of a unit wiring layer (second layer wiring is taken as an example) in the manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. (When the metal film is formed). FIG. 11 is a device cross-sectional process flow diagram (antireflection film) of a unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. At the time of film formation). FIG. 12 is a device cross-sectional process flow diagram (photo resist) of a unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. Film application time). FIG. 13 is a device cross-sectional process flow diagram (photo resist) of a unit wiring layer (second layer wiring is taken as an example) in the manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. Film development time). FIG. 14 is a device cross-sectional process flow diagram (wiring metal film) of a unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. (When dry etching is completed). FIG. 15 Device cross-sectional process flow diagram (photo resist film) of unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) of one embodiment of the present application Ashing removal completion time). FIG. 16 is a device cross-sectional process flow diagram (side wall polymer removal) of a unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. (FIG. 21 to FIG. 21 correspond to the XX ′ cross section of FIG. 17). FIG. 17 is a top view of the wafer corresponding to FIG. FIG. 18 is a device cross-sectional process flow diagram (HDP-CVD) of a unit wiring layer (second layer wiring is taken as an example) in a manufacturing method of a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. At the time of completion). FIG. 19 is a device cross-sectional process flow diagram (plasma TEOS film) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. At the time of film formation). FIG. 20 is a device cross-sectional process flow chart (at the time of completion of CMP) of a unit wiring layer (second layer wiring is taken as an example) in the method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. ). FIG. 21 is a device cross-sectional process flow diagram (cap silicon oxide type) of a unit wiring layer (second layer wiring is taken as an example) in a method of manufacturing a semiconductor integrated circuit device (aluminum-based normal wiring product) according to an embodiment of the present application. At the time of film formation).

  FIG. 7 shows a device cross-sectional structure when the lower insulating film 10 (including the pre-metal insulating film 20 and the first aluminum wiring layer M1 in FIG. 5) including the premetal insulating film and the first aluminum wiring layer is completed. (Step of forming interlayer insulating film 101 in the lower part of FIG. 6).

  Next, as shown in FIG. 8, first, the second layer wiring region lower layer barrier metal film 2 (for example, about 15 nm thick) is formed on almost the entire surface of the lower insulating film 10 on the almost entire surface 1a of the wafer 1. A lower titanium film, a lower titanium nitride film having a thickness of about 20 nm, etc.) are formed by sputtering. The temperature of the wafer stage on which the wafer 1 is placed during the sputtering is, for example, about 300 degrees Celsius (first wafer temperature).

  Next, as shown in FIG. 9, the second-layer wiring region aluminum-based wiring metal film 5 (for example, on the almost entire surface of the second-layer wiring region lower layer barrier metal film 2 on the almost entire surface 1a of the wafer 1 Aluminum having a thickness of about 250 nm as a main component, for example, adding about 1% by weight of copper) is formed by sputtering. The temperature of the wafer stage on which the wafer 1 is placed during the sputtering is, for example, about 300 degrees Celsius.

  Next, as shown in FIG. 10, the second-layer wiring region upper layer barrier metal film 6 (for example, about 5 nm thick) is formed on almost the entire surface of the aluminum-based wiring metal film 5 on the almost entire surface 1a of the wafer 1. A lower titanium film, a lower titanium nitride film having a thickness of about 50 nm, etc.) is formed by sputtering (the wiring film forming step 102 in FIG. 6). The temperature of the wafer stage on which the wafer 1 is placed during the sputtering is, for example, about 300 degrees Celsius. The second layer wiring region lower layer barrier metal film 2, the second layer wiring region aluminum-based wiring metal film 5, the second layer wiring region upper layer barrier metal film 6 and the like constitute the second layer multilayer wiring metal film 3. .

Next, as shown in FIG. 11, a second-layer wiring antireflection film 18 (plasma CVD-SiON) having a thickness of, for example, about 30 nm is formed on almost the entire surface of the barrier metal film 6 on almost the entire surface 1a of the wafer 1. Film) (an antireflection film forming step 103 in FIG. 6). Examples of the film forming conditions include a gas flow rate of SiH ₄ / N ₂ O / He = 140 sccm / 600 sccm / 750 sccm, a high-frequency power of about 100 watts, an atmospheric pressure of about 300 Pascal, and a wafer temperature of about 400 degrees Celsius.

  Next, as shown in FIG. 12, a photo resist film 19 is applied on almost the entire surface of the antireflection film 18 on almost the entire surface 1a of the wafer 1 (resist coating step 104 in FIG. 6). Subsequently, as shown in FIG. 13, the photoresist film 19 is patterned by photolithography or the like (KrF, ArF, EUV, etc.) (lithography step 105 in FIG. 6).

Next, as shown in FIG. 14, when dry etching is performed using the patterned photoresist film 19 as a mask, the second-layer multilayer wiring metal film 3 is patterned (including the antireflection film 18). (Multilayer wiring metal film etching step 106 in FIG. 6). At this time, the side wall polymer film 21 is formed on the side wall of the patterned second layer multilayer wiring metal film 3 and the like. As the dry etching conditions, for example, the gas atmosphere is Cl ₂ , BCl ₃ or the like, high-frequency power (upper 800 watts / lower 330 watts), atmospheric pressure 0.8 pascals, wafer stage temperature 40 degrees centigrade. can do.

  Next, as shown in FIG. 15, ashing is performed on the first main surface 1a side of the wafer 1 to remove the photo resist film 19 (ashing step 107 in FIG. 6). Examples of the ashing conditions include a gas flow rate of O2 / N2 = about 7500 sccm / 40 sccm, a high frequency power of about 1500 watts, an atmospheric pressure of about 200 Pascal, and a wafer stage temperature of about 250 degrees Celsius.

  Next, as shown in FIG. 16, the sidewall polymer film 21 is removed with an organic solvent (polymer removal step 108 in FIG. 6). A state of the upper surface 1a of the wafer 1 at this time is shown in FIG. The cross section in FIG. 16 corresponds to X-X ′ in FIG. 17. Subsequently, a passivation treatment step 109 (FIG. 6) for stabilizing the aluminum-based wiring metal layer 5 after etching, that is, a fifth plasma surface treatment is performed. As this processing condition, for example, gas flow rate O2 = about 7000 sccm, high-frequency power about 2000 watts, pressure 100 to 300 Pascal, wafer stage temperature about 250 degrees Celsius (seventh wafer temperature) can be exemplified. The process from the previous ashing process 107 to this process is referred to as a multi-layer wiring metal film post-etching process group 120.

  Next, as shown in FIG. 18, the second layer wiring region HDP-CVD silicon oxide-based interlayer insulating film 14 having a thickness of about 400 nm is introduced into the HDP-CVD furnace described with reference to FIGS. A film is formed (HDP interlayer insulating film forming step 111 in FIG. 6). Since the steps before and after this step will be described in detail in section 4 as the interlayer film forming peripheral step group 121 (FIG. 6), only a brief description will be given here. The previous multilayer wiring metal film etching step 106 to HDP interlayer insulating film forming step 111 (including the interlayer film forming peripheral step group 121) is referred to as a multilayer wiring metal film etching & interlayer film forming peripheral step group 122.

  Next, as shown in FIG. 19, the second layer wiring having a thickness of, for example, about 600 nm is formed on almost the entire surface of the second layer wiring region HDP-CVD silicon oxide-based interlayer insulating film 14 on the almost entire surface 1a of the wafer 1. A region plasma TEOS silicon oxide-based interlayer insulating film 7 is formed (plasma TEOS interlayer insulating film forming step 112 in FIG. 6). Examples of the film forming conditions include a gas flow rate TEOS / O2 / He = 5250 (mg / min) / 4200 sccm / 4000 sccm, a high frequency power of about 1400 watts, a pressure of about 300 to 1500 Pascal, and a wafer temperature of about 400 degrees Celsius. be able to.

  Subsequently, as shown in FIG. 20, planarization is performed by polishing by chemical mechanical polishing or the like up to the broken line portion representing the CMP polishing amount 12 in FIG. 19 (chemical mechanical polishing step 113 in FIG. 6). .

  Next, as shown in FIG. 21, a second-layer wiring region plasma TEOS silicon oxide-based cap insulating film 11 is formed (cap insulating film forming step in FIG. 6).

  Thereafter, the second layer wiring region tungsten plug 27 and the barrier metal film 28 of the second layer wiring region tungsten plug are embedded to complete the second layer aluminum-based wiring layer M2.

  This manufacturing method is basically the same even if the wiring layer is changed. That is, the first-layer aluminum-based wiring layer M1 to the third-layer aluminum-based wiring layer M3 are almost the same, and the fourth-layer aluminum-based wiring layer M4 has dimensions when the same layer is used as a bonding pad layer as it is. The difference is almost the same except that there are no vias and plugs.

4). 2. Description of Interlayer Film Forming Peripheral Process Group as Main Process of Manufacturing Method of Semiconductor Integrated Circuit Device (Product of Aluminum Normal Wiring) of One Embodiment of the Present Application (Mainly FIGS. 22 to 25)
Based on Sections 1 to 3, an interlayer film deposition peripheral process group which is a main process of the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  FIG. 22 is a process block flow diagram of an interlayer film forming peripheral process group which is a main process of the manufacturing method of the semiconductor integrated circuit device (aluminum-based normal wiring product) according to the embodiment of the present application. FIG. 23 is a process block flow diagram showing a specific example of a detailed configuration of the plasma annealing step of FIG. FIG. 24 is a wafer temperature change schematic diagram showing the transition of the wafer temperature in the interlayer film forming peripheral process group of FIG. FIG. 25 is a table summarizing the processing conditions and the like of each step in the interlayer film forming peripheral process group of FIG.

  As shown in FIG. 22, the wafer 1 that has undergone the processing of the multi-layer wiring metal film post-etching process step group 120 (FIG. 6) is accommodated in the hoop 53 described in FIG. And loaded on the wafer stage 62 of one of the plasma processing chambers 57a, 57b, 57c (first plasma chamber) according to the procedure described in section 1. In this state, processing belonging to a series of interlayer film formation peripheral process group 121 is performed. From the viewpoint of processing efficiency and processing characteristics, it is desirable that the wafer 1 be placed on the same wafer stage 62 during the processing belonging to the series of interlayer film forming peripheral process group 121.

  First, the outline of the interlayer film forming peripheral process group 121 will be described with reference to FIG. Before forming the interlayer insulating film 14 (FIG. 18) by HDP-CVD or the like, a plasma annealing process 151 is performed on the device surface 1a (first main surface) side of the wafer 1 as a pretreatment. To do. The main purpose of the plasma annealing process 151 is to perform plasma annealing at a wafer temperature higher than the deposition temperature of the aluminum wiring metal film and the interlayer insulating film in an atmosphere containing an inert gas as one of the main components. By performing the process, the gas component remaining on the sidewall of the wiring metal layer is prevented from being discharged due to thermal stress during the formation of the interlayer insulating film, and the stress release inside the metal film (that is, The chipping defect can be suppressed by the progress of passivation and the release of stress of the wiring metal layer before the formation of the interlayer insulating film.

  After the plasma annealing process 151, as shown in FIG. 22, the HDP interlayer insulating film forming step 111 (first plasma CVD process) is performed on the device surface 1a (first main surface) side of the wafer 1. To do. Subsequently, a post-CVD process step 161, that is, a rapid cooling process of the wafer temperature, is performed on the device surface 1a (first main surface) side of the wafer 1. The main purpose of this treatment is to prevent precipitation of copper added to the aluminum-based wiring metal film 5 (FIG. 16) as a measure against electromigration. In addition, as shown by a detour arrow in FIG. 22, this rapid cooling process is not essential, but if implemented, it is beneficial for improving reliability and the like.

  Next, the outline and significance of each processing step desirably performed as a series of plasma annealing processes 151 will be described with reference to FIG. First, in the plasma cleaning process 151a, a surface region such as the aluminum-based wiring metal film 5 is cleaned by a sputtering action by plasma excitation in a gas atmosphere containing an inert gas such as argon as one of main components. . As indicated by a detour arrow in FIG. 23, the plasma cleaning process 151a is not essential, but if implemented, it is beneficial for improving reliability and the like.

  The next plasma oxidation treatment 151b is an aluminum-based wiring that is insufficiently passivated by a sputtering action by plasma excitation and an oxidation action by oxygen radicals in an atmosphere containing inert gas and oxygen gas as one of the main components. Further passivation of the surface region of the metal film 5 or the like is further advanced. As indicated by a detour arrow in FIG. 23, the plasma cleaning process 151a is not essential, but if implemented, it is beneficial for improving reliability and the like.

  The final plasma high-temperature annealing process 151d is a surface region of the aluminum-based wiring metal film 5 and the like by sputtering of the wafer 1 by heating and plasma excitation in a gas atmosphere containing an inert gas such as argon as one of main components. The main purpose is to promote degassing from Therefore, the main value (or average value) of the wafer temperature needs to be higher than the main value (or average value) of the subsequent interlayer insulating film forming step 111 (FIG. 22). In addition, it is effective to add oxygen when it is desired to further suppress insufficient oxidation treatment by utilizing the effect of high temperature and oxygen radicals to suppress aluminum deficiency or the like (specific example of FIG. 25). reference). This also applies to the subsequent in-plasma temperature raising process 151c.

  The plasma temperature raising process 151c is a transition period for increasing the wafer temperature from the preceding step to the plasma high temperature annealing process 151d, and can be omitted if the wafer temperature can be increased instantaneously. Any atmosphere can be used as long as it does not cause harm. However, if the atmosphere is the same as or similar to that of the plasma high temperature annealing process 151d, the processing time of the plasma high temperature annealing process 151d can be shortened.

  Next, a preferred example of the detailed process of the interlayer film forming peripheral process group 121 of FIG. 22 will be described based on FIGS. As shown in FIGS. 24 and 25 (see FIGS. 1, 2, 6, and 16 to 18, FIG. 22, and FIG. 23), the device surface 1a (first main surface) side of the wafer 1 is upside. It is mounted in a state facing toward. In this state, the plasma cleaning process 151a (step A, that is, the second plasma surface process) is executed. As an example of suitable conditions, the processing time is about 30 seconds, the gas flow rate is about argon 250 sccm (second atmosphere), the high frequency power top 67 / side 65 / bias 63 = 3000 watts / 5000 watts / off, and the electrostatic chuck 91 is on. The wafer cooling control system 81 is off, the wafer temperature is about 150 to 270 degrees Celsius (the fourth wafer temperature, that is, the temperature around 250 degrees Celsius), and the processing pressure is about 0.4 to 0.6 Pascals. be able to. Note that the second atmosphere preferably contains substantially no oxygen from the viewpoint of cleaning characteristics. However, oxygen can be added, for example, when it is desired to execute simultaneously with the next step.

  Next, the plasma oxidation process 151b (step B, that is, the third plasma surface process) is performed in the above state. Examples of suitable conditions include a processing time of about 30 seconds, a gas flow rate of argon / oxygen = about 250 sccm / about 250 sccm (third atmosphere), high frequency power top 67 / side 65 / bias 63 = 3000 watt / 5000 watt / off, The electrostatic chuck 91 is on, the wafer cooling control system 81 is off, the wafer temperature is about 200 to 270 degrees Celsius (the fifth wafer temperature, that is, a temperature around 250 degrees Celsius), and the processing pressure is 0.4 Pascal to 0.degree. About 6 Pascals can be exemplified. Here, nitriding treatment can be performed by changing the oxygen gas to nitrogen gas. As described above, the fourth wafer temperature and the fifth wafer temperature belong to substantially the same temperature region.

  Next, the other conditions are almost the same, the electrostatic chuck is turned off, and the temperature rise is started, so that the plasma temperature rise treatment 151c (step C, that is, the fourth plasma surface treatment) is performed. Execute. Examples of suitable conditions include a processing time of about 40 seconds, a gas flow rate of argon / oxygen = about 250 sccm / about 250 sccm (fourth atmosphere), high frequency power top 67 / side 65 / bias 63 = 3000 watt / 5000 watt / off, The electrostatic chuck 91 is off, the wafer cooling control system 81 is off, the wafer temperature is raised toward, for example, about 380 degrees Celsius, and the processing pressure is 0.53 Pascals to 0.66 Pascals.

  Next, when the wafer temperature reaches about 380 degrees Celsius (second wafer temperature), the electrostatic chuck 91 is turned on, and the others are almost as they are. Step D, ie the first plasma surface treatment) is performed. Examples of suitable conditions include a processing time of about 60 seconds, a gas flow rate of argon / oxygen = about 250 sccm / about 250 sccm (first atmosphere), high frequency power top 67 / side 65 / bias 63 = 3000 watt / 5000 watt / off, The electrostatic chuck 91 is on, the wafer cooling control system 81 is off, and the wafer temperature is, for example, about 380 degrees Celsius (the preferred wafer temperature range is about 350 to 450 degrees Celsius, provided that the second wafer temperature is For example, the processing pressure is 0.53 Pascal to 0.66 Pascal.

  Next, while the electrostatic chuck 91 is kept on, the cooling system 81 is turned on, and the HDP interlayer insulating film forming step 111 is performed while the wafer temperature is lowered to about 350 degrees Celsius (third wafer temperature), for example. (Step E, that is, the first plasma CVD process) is executed. As an example of suitable conditions, the processing time is about 80 seconds, the gas flow rate monosilane / oxygen = about 39 sccm / about 65 sccm, the high frequency power top 67 / side 65 / bias 63 = 2500 watts / 6000 watts / 7500 watts, the electrostatic chuck 91 is Off, wafer cooling control system 81 is off, stable wafer temperature, for example, about 350 degrees Celsius (preferred wafer temperature range is about 320 to 370 degrees Celsius, provided that the second wafer temperature is the third wafer temperature. As a precondition that the temperature is higher than the temperature), a processing pressure of 0.53 Pascal to 0.66 Pascal and a film thickness of about 400 nm can be exemplified.

  Next, the gas and the high-frequency power are switched, and the wafer temperature is set to 200 degrees Celsius (sixth wafer temperature, where the sixth wafer temperature is the copper deposition temperature of the aluminum wiring metal film and the first The post-CVD post-treatment process 161 (step F) is performed to cool to below the temperature of Examples of suitable conditions include a processing time of 40 to 80 seconds, a gas flow rate of argon / oxygen = about 250 sccm / about 310 sccm, high frequency power top 67 / side 65 / bias 63 = off / 500 watt / off (all may be off) However, if the plasma is turned on even if it is weak, the processing steps are not complicated and the processing time can be shortened.) The electrostatic chuck 91 is on, the wafer cooling control system 81 is on, and the wafer temperature is, for example, centigrade. Descent toward 200 degrees or less (for example, up to 150 degrees Celsius) (Note that the average temperature drop rate between 300 degrees Celsius and 200 degrees Celsius is preferably 2 degrees / second or more and 5 degrees / second or less), processing An atmospheric pressure of about 0.66 Pascal to 0.75 Pascal can be exemplified.

5). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, an example using the “Centura Ultimate” of an HDP-CVD apparatus manufactured by Applied Materials, Inc. is specifically described, but the present invention is not limited thereto. Of course, it may be carried out using "Concept Three Speed" of Novellus Co., Ltd. or other devices corresponding to other semiconductor device manufacturers.

  Further, in the above-described embodiment, the wiring layer has been specifically described as being an aluminum-based normal wiring, but the present invention is not limited thereto, and a copper-based or silver-based damascene wiring and Needless to say, the present invention can be similarly applied to an aluminum-based normal wiring portion in a wiring structure using a mixture of aluminum-based normal wiring.

1 Semiconductor wafer (P-type single crystal silicon wafer)
1a Device surface of semiconductor wafer (first main surface)
1b Back surface of semiconductor wafer (second main surface)
2 Second layer wiring region lower layer barrier metal film 3 Second layer multilayer wiring metal film 4 STI region 5 Second layer wiring region aluminum-based wiring metal film 6 Second layer wiring region upper layer barrier metal film 7 Second layer wiring region Plasma TEOS silicon oxide based interlayer insulating film 8 Source / drain region 9 Gate electrode structure 10 Lower layer insulating film including premetal insulating film and first layer aluminum based wiring layer 11 Second layer wiring region Plasma TEOS silicon oxide based cap insulating film 12 CMP Abrasive amount 13 First layer multilayer wiring metal film 14 Second layer wiring region HDP-CVD silicon oxide interlayer insulating film 15 First layer wiring region tungsten plug 16 Barrier metal film of first layer wiring region tungsten plug 17 Final Passivation film 18 Antireflection film for second layer wiring (CVD-SiON film)
19 Photo resist film 20 Pre-metal insulating film 21 Side wall polymer film 22 Barrier metal for contact plug 24 First layer wiring region HDP-CVD silicon oxide based interlayer insulating film 25 First layer wiring region Plasma TEOS Silicon oxide based interlayer Insulating film 26 First layer wiring region plasma TEOS Silicon oxide cap insulating film 27 Second layer wiring region tungsten plug 28 Barrier metal film of second layer wiring region tungsten plug 32 Third layer wiring region tungsten plug 33 Three-layer multilayer wiring metal film 34 Third-layer wiring region Tungsten plug barrier metal film 35 Third-layer wiring region HDP-CVD silicon oxide-based interlayer insulating film 36 Third-layer wiring region Plasma TEOS Silicon-oxide-based interlayer insulating film 37 Third layer wiring region plasma TEOS silicon oxide Cap insulating film 38 Fourth-layer wiring region HDP-CVD Insulating silicon oxide-based layer insulating layer 39 Fourth-layered wiring region Plasma TEOS Insulating silicon-based insulating layer 40 Tungsten-based contact plug 41 Plasma 43 Fourth-layer multilayered wiring metal film 44 Antireflection film for first layer wiring (CVD-SiON film)
45 Antireflection film for third layer wiring (CVD-SiON film)
46 Antireflection film for 4th layer wiring (CVD-SiON film)
51 Multi-chamber wafer processing equipment 52 Load port 53 Hoop (sealed wafer transfer container)
54 Local cleaning chamber 55 Load lock chamber 56 Vacuum transfer chamber 57a, 57b, 57c Plasma processing chamber (plasma CVD chamber)
58 Vacuum transfer robot 59 Load / unload robot 61 Chamber outer wall 62 Wafer stage (lower electrode)
63 Wafer side bias high frequency power supply 64 Wafer side bias capacitor 65 Side antenna high frequency power supply 66 Plasma excitation side antenna 67 Top antenna high frequency power supply 68 Plasma excitation top antenna 69 Gas introduction nozzle 70 Main exhaust gate Valve 71 Wafer loading / unloading gate 72 Main exhaust pipe 73 Turbo molecular pump 74 Dry roughing pump 75 Preliminary exhaust pipe 76 Preliminary exhaust valve 77 Cleaning remote plasma excitation chamber 78 Cleaning gas transport pipe 79 Gas introduction baffle 81 Helium cooling system control Part 82 Helium / gas source 83 Wafer inner area helium / gas pressure control system 84 Wafer edge area helium / gas pressure control system 85 Wafer inner area helium / gas supply valve 86 Wafer edge area helicopter Gas supply valve 87 Wafer internal area helium gas supply pipe 88 Wafer edge area helium gas supply pipe 91 Electrostatic chuck 93 Wafer internal area between wafer stage and wafer back surface 94 Wafer edge area 101 between wafer stage and wafer back surface 101 Lower interlayer insulating film forming process (first wiring layer forming process)
102 wiring film forming process 103 antireflection film forming process 104 resist coating process 105 lithography process 106 multilayer wiring metal film etching process 107 ashing process 108 polymer removing process 109 passivation process 111 HDP interlayer insulating film forming process 112 plasma TEOS interlayer insulating Film forming process 113 Chemical mechanical polishing process 114 Cap insulating film forming process 120 Multilayer wiring metal film post-etching process group 121 Interlayer film forming peripheral process group 122 Multilayer wiring metal film etching & interlayer film forming peripheral process group 151 Plasma annealing Process 151a Plasma cleaning process 151b Plasma oxidation process 151c Temperature rising process in plasma 151d Plasma high temperature annealing process 161 Post-CVD process A Plasma cleaning process step B Plasma Treatment step C Plasma temperature rise treatment step D Plasma high temperature annealing treatment E Plasma CVD step F CVD post-treatment step M1 First layer aluminum-based wiring layer M2 Second layer aluminum-based wiring layer M3 Third layer aluminum-based wiring layer M4 First 4-layer aluminum wiring layer

Claims (19)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a multilayer wiring metal film including an aluminum-based wiring metal film on the first main surface of the wafer at a first wafer temperature;
(B) patterning the multilayer wiring metal film including the aluminum-based wiring metal film on the first main surface of the wafer;
(C) after the step (a), setting the wafer on a wafer stage in a first plasma CVD chamber;
(D) A first atmosphere containing an inert gas as one of main components with respect to the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber. Performing a first plasma surface treatment at a second wafer temperature higher than the first wafer temperature;
(E) After the step (d), the temperature of the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber is lower than the second wafer temperature. A step of performing an interlayer insulating film forming process by a first plasma CVD process at a third wafer temperature.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first atmosphere includes oxygen gas as one of main components. The method for manufacturing a semiconductor integrated circuit device according to the item 2, further includes the following steps:
(F) The first main surface of the wafer set on the wafer stage in the first plasma CVD chamber after the step (c) and before the step (d) On the other hand, a step of performing the second plasma surface treatment in a second atmosphere containing an inert gas as one of main components at a fourth wafer temperature lower than the first wafer temperature.     In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the second atmosphere does not substantially contain oxygen. The method for manufacturing a semiconductor integrated circuit device according to the item 3, further includes the following steps:
(G) After the step (f) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber On the other hand, the third plasma surface treatment is performed in a third atmosphere containing an inert gas and an oxygen gas as one of the main components at a fifth wafer temperature lower than the first wafer temperature. Process.     In the method of manufacturing a semiconductor integrated circuit device according to the item 5, the fourth wafer temperature and the fifth wafer temperature are substantially the same. The method for manufacturing a semiconductor integrated circuit device according to the item 5, further includes the following steps:
(H) After the step (e), the temperature of the wafer set on the wafer stage in the first plasma CVD chamber is changed from the third wafer temperature to the first wafer temperature. Lowering the temperature to a lower sixth wafer temperature or lower.     In the method of manufacturing a semiconductor integrated circuit device according to the item 7, the sixth wafer temperature is 200 degrees Celsius.     In the method for manufacturing a semiconductor integrated circuit device according to the item 8, the average temperature drop rate between 300 degrees Celsius and 200 degrees Celsius in the step (h) is 2 degrees / second or more and 5 degrees / second or less.     In the method of manufacturing a semiconductor integrated circuit device according to the item 9, the plasma is in a lighting state in the step (h). The method for manufacturing a semiconductor integrated circuit device according to the item 7, further includes the following steps:
(I) After the step (g) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber In contrast, in a fourth atmosphere containing an inert gas as one of the main components, the temperature of the wafer is raised from the fifth wafer temperature to the second wafer temperature. Process for performing plasma surface treatment     12. In the method of manufacturing a semiconductor integrated circuit device according to the item 11, the fourth atmosphere includes oxygen gas as one of main components.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the interlayer insulating film is a silicon oxide insulating film formed by HDP-CVD. The method for manufacturing a semiconductor integrated circuit device according to the item 1, further includes the following steps:
(J) After the step (b) including the removal of the resist film and the polymer, and before the step (c), the first atmosphere is included in a fifth atmosphere containing oxygen gas as one of main components. Executing a fifth plasma surface treatment at a seventh wafer temperature lower than the wafer temperature     In the method for manufacturing a semiconductor integrated circuit device according to the item 14, the step (j) is not performed in the first plasma CVD chamber.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the second wafer temperature is not less than 350 degrees Celsius and not more than 450 degrees Celsius.     In the method for manufacturing a semiconductor integrated circuit device according to the item 16, the fourth wafer temperature is not less than 150 degrees Celsius and not more than 270 degrees Celsius.     In the method for manufacturing a semiconductor integrated circuit device according to the item 17, the third wafer temperature is not less than 320 degrees Celsius and not more than 370 degrees Celsius. The method for manufacturing a semiconductor integrated circuit device according to the item 3, further includes the following steps:
(G) After the step (f) and before the step (d), the first main surface of the wafer set on the wafer stage in the first plasma CVD chamber On the other hand, the third plasma surface treatment is performed in a third atmosphere containing inert gas and nitrogen gas as one of the main components, at a fifth wafer temperature lower than the first wafer temperature. Process.

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