JP2009054744A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a phenomenon that copper interconnection disappears in some wafers in a lot when polymer deposited at via bottom is removed by wet etching after a copper difffusion barrier insulating film at the via bottom has been removed. <P>SOLUTION: In the method, the polymer is kept in a non-oxidizing dry gas (N<SB>2</SB>gas or Ar) atmosphere (S93) while polymer deposited at the via bottom is being removed after the copper diffusion barrier insulating film at the via bottom has been removed. Thereby, the polymer is prevented from taking in oxygen and moisture in the atmosphere. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a manufacturing process of a semiconductor integrated circuit device including a step of storing a semiconductor wafer using a sealed wafer storage container such as FOUP (Front Opening Unified Pod). And effective technology.

  Japanese Laid-Open Patent Publication No. 8-203993 (Patent Document 1) discloses a sealed container (wafer cassette carrying container) containing a wafer cassette containing semiconductor wafers and sealed with an inert gas atmosphere, and a sealed container. In a gas supply system of a portable closed container equipped with a gas supply device for supplying and exhausting an inert gas to the inside, by constantly flowing a certain amount of replacement gas economically to a semiconductor wafer in the sealed container A technique capable of reducing the contamination of the liquid is disclosed.

  In Japanese Patent Laid-Open No. 7-66274 (Patent Document 2), a portable airtight container (wafer cassette transfer container) that contains a wafer cassette containing a semiconductor wafer is connected to an inert gas source such as a nitrogen cylinder. Therefore, a technique is disclosed in which the inside atmosphere of the sealed container can be replaced with an inert gas atmosphere, and the cost and labor required for the gas purge can be greatly reduced.

In Japanese Patent Laid-Open No. 7-66273 (Patent Document 3), a portable airtight container (wafer cassette transfer container) that contains a wafer cassette containing a semiconductor wafer is connected to an inert gas source such as a nitrogen cylinder. Therefore, a technique is disclosed in which the internal atmosphere of the sealed container can be adjusted to an inert gas atmosphere, and the cost and labor required for regas purging can be greatly reduced.

  In Japanese Patent Laid-Open No. 5-74921 (Patent Document 4), a plasma etching process is performed in a case (wafer cassette container) having a sealed container structure in which a semiconductor wafer is accommodated and an airtight maintaining coupler is attached. When the semiconductor wafer is accommodated, the aluminum alloy on the surface of the semiconductor wafer is removed by removing moisture from the accommodating space in the case using an airtight maintaining coupler and filling the inert gas with a positive pressure. Techniques for preventing film corrosion are disclosed.

  In Japanese Patent Laid-Open No. 2003-168727 (Patent Document 5), the atmosphere inside the container is changed to nitrogen gas or the like without remanufacturing a container (hoop) for transporting a semiconductor wafer or the like and a lid of the container. An apparatus that can be replaced is disclosed.

  Japanese Patent Application Laid-Open No. 11-251397 (Patent Document 6) discloses an object to be processed in which the inner wall surface of a cassette chamber that accommodates an object to be processed (semiconductor wafer) treated with a processing gas containing bromine is not easily corroded. An unloading method and a conveying device are disclosed.

  Japanese Patent Application Laid-Open No. 11-145245 (Patent Document 7) discloses a shielding container for accommodating a substrate container (hoop) capable of accommodating a plurality of substrates (semiconductor wafers) from the outside atmosphere. Use the open / close control mechanism to release the shielding state of the shielding heat, and transport the substrate accommodated in the substrate container to the substrate processing unit through the transportation port communicating with the opening of the opened shielding container. In a substrate processing apparatus that performs processing, a technique for preventing contamination of a substrate by the atmosphere inside the substrate processing apparatus by shielding the atmosphere of the shielding container from the atmosphere inside the substrate processing apparatus is disclosed.

  In Japanese Patent Special Publication No. 2003-515244 (Patent Document 8) or corresponding US Registered Patent Publication No. 6,406,553 (Patent Document 9), a cassette (hoop) containing a semiconductor wafer is provided in the input / output chamber. After being placed, the cassette is sealed from the line and air, and then a cover blanket is formed around the semiconductor wafer by dispersing dry inert gas such as nitrogen at the tip of the I / O chamber and is carried by air Techniques have been disclosed for removing residual contamination from a semiconductor wafer before it is transferred to a processing line by replacing and cleaning out contaminants such as particles, moisture and organic vapors.

  In Japanese Patent Laid-Open No. 2003-45933 (Patent Document 10) and corresponding US Published Patent Publication No. 2003-031537 (Patent Document 11), a carrier door forming one surface of a wafer carrier (hoop) is used as a semiconductor wafer process. A technique for efficiently replacing the atmosphere in the wafer carrier in a short time by purging the inside of the wafer carrier by supplying an inert gas or dry air while being opened by the load port door of the apparatus is disclosed. .

  Furthermore, Japanese Patent Application Laid-Open No. 2006-49683 (Patent Document 12) discloses a case where a processed wafer is accommodated in a FOUP after a polysilicon-doped polysilicon deposition process and waits for the next process. In addition, it is disclosed that a dry gas is supplied into the hoop so that phosphorous components on the wafer and moisture in the atmosphere do not react to form phosphoric acid.

Japanese Patent Laid-Open No. 8-203993 JP-A-7-66274 JP 7-66273 A Japanese Patent Application Laid-Open No. 5-75921 JP 2003-168727 A Japanese Patent Laid-Open No. 11-251397 Japanese Patent Laid-Open No. 11-145245 Special table 2003-515244 gazette US Registered Patent Publication No. 6,406,553 Japanese Patent Laid-Open No. 2003-45933 US Published Patent Publication No. 2003-031537 JP 2006-49683 A

  For storing or transporting semiconductor wafers (hereinafter simply referred to as wafers) in a semiconductor production line, for example, a hoop or front opening unified pod (FOUP) provided with an opening door for inserting and removing the wafer is provided at the front. A hermetic wafer storage container or the like is used. The FOUP is formed by a shell that is a holding unit for storing a wafer and a door that is an opening / closing door unit, and holds the wafer in a sealed space, thereby protecting the wafer from foreign substances or chemical contamination in the atmosphere. Can do. For example, in a semiconductor production line using a wafer having a diameter of 300 mm, a mini-environment technology using FOUP is adopted, and the running cost is reduced by cleaning only the region where the wafer is processed. .

  However, it has been clarified by the inventors of the present invention that there are the following problems even in such a closed type conveyance system. That is, in the copper buried wiring process (single damascene process or dual damascene process), the copper diffusion barrier insulating film etching process at the via bottom is accommodated in the hoop. Then, after storing in an atmosphere equivalent to the atmosphere in a normal clean room (of course, the cleanliness in the hoop is much higher than in the clean room), a wet etching process for polymer removal is performed. Then, the copper at the bottom of the via is greatly etched and disappears.

  This phenomenon is interpreted as follows. That is, as shown in FIG. 29, after etching the copper diffusion barrier insulating film 3 at the via bottom, the copper wiring 2 is present at the via bottom, but the upper surface of the copper wiring 2 around the via bottom, the copper diffusion barrier insulating film. The polymer 11 formed during the etching is formed on the side surface 3 and the side surface of the interlayer insulating film. While this is stored in the hoop, it absorbs oxygen and moisture in the atmosphere in the hoop, and these react with the lower copper wiring to alter the copper wiring (copper oxide layer 15). As a result, the oxidized copper wiring is presumed to be etched at the same time as the polymer etching.

  An object of the present invention is to achieve a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in the present invention, after removing the copper diffusion barrier insulating film at the bottom of the via by dry etching, the polymer is stored in a non-oxidizing dry gas atmosphere while the polymer accumulated at the bottom of the via is removed by wet etching. It is intended to prevent the intake of oxygen and moisture in the atmosphere.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, after removing the copper diffusion barrier insulating film at the bottom of the via by dry etching, the polymer is wet etched by storing it in a non-oxidizing dry gas atmosphere while removing the polymer accumulated at the bottom of the via by wet etching. It is possible to prevent the lower layer copper wiring from disappearing when removing by.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surfaces of the wiring grooves and vias.

2. In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the step (b) includes the following sub-steps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.

  3. In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the wafer transfer container is a sealed type.

  4). In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the wafer transfer container is a hoop.

  5). 5. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the storing of the step (c) is performed in a standby area.

  6). 5. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the storage of the step (c) is performed in a stocker.

  7. 7. In the method of manufacturing a semiconductor integrated circuit device according to any one of 2 to 6, the storing in the step (c) supplies the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container. Is done by.

  8). In the method for manufacturing a semiconductor integrated circuit device according to any one of 2 to 6, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the second breathing hole of the wafer transfer container.

  9. 9. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, wherein the non-oxidizing dry gas atmosphere contains an inert gas as a main component.

  10. 9. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, wherein the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

11. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surface of the wiring groove and via;
Here, the step (a) includes the following substeps:
(A1) performing a dry etching process in an etching atmosphere containing a fluorocarbon-based etching gas in the etching process chamber;
(A2) A step of performing plasma treatment in a non-oxidizing atmosphere containing nitrogen as one of main components in the etching chamber after the step (a1).

  12 12. The manufacturing method of a semiconductor integrated circuit device according to the item 11, wherein the etching atmosphere does not substantially contain a component that generates an oxidizing reactive species.

  13. In the method for manufacturing a semiconductor integrated circuit device according to the item 11 or 12, the etching atmosphere contains trifluoromethane.

14 14. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 13, wherein the step (b) includes the following substeps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.

  15. 15. The method for manufacturing a semiconductor integrated circuit device according to item 14, wherein the wafer transfer container is a sealed type.

  16. 16. The method for manufacturing a semiconductor integrated circuit device according to the item 15, wherein the wafer transfer container is a hoop.

  17. 17. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 16, the storing of the step (c) is performed in a stocker.

  18. In the method of manufacturing a semiconductor integrated circuit device according to any one of 14 to 17, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from a first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the second breathing hole of the wafer transfer container.

  19. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 18, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.

  20. 19. In the method of manufacturing a semiconductor integrated circuit device according to any one of 11 to 18, the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

  21. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 11 to 18, the non-oxidizing dry gas atmosphere does not substantially contain oxygen gas.

  Next, an outline of another embodiment of the invention disclosed in the present application will be described.

22. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) carrying the unloaded wafer into a wet processing apparatus;
(D) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(E) a step of unloading the wafer from the wet processing apparatus after the step (d);
(F) After the step (e), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surface of the wiring groove and via,
Here, the step (a) includes the following substeps:
(A1) performing a dry etching process in an etching atmosphere containing an etching gas containing a fluorocarbon-based etching gas and substantially free of oxidizing reactive species in the etching process chamber;
(A2) A step of performing plasma treatment in a non-oxidizing atmosphere containing nitrogen as one of main components in the etching chamber after the step (a1).

  23. 23. In the method for manufacturing a semiconductor integrated circuit device according to the item 22, the etching atmosphere contains trifluoromethane.

24. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating wiring metal which is formed in an insulating film on the first main surface of the wafer in the etching chamber of the dry etching apparatus and which exists on the bottom surface of the via in the embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a wiring metal diffusion barrier metal film on the surface of the insulating film and the inner surfaces of the wiring grooves and vias.

25. 25. In the method for manufacturing a semiconductor integrated circuit device according to the item 24, the step (b) includes the following sub-steps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.

  26. 26. In the method for manufacturing a semiconductor integrated circuit device according to the item 25, the wafer transfer container is a sealed type.

  27. 27. In the method for manufacturing a semiconductor integrated circuit device according to the item 26, the wafer transfer container is a hoop.

  28. 28. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 24 to 27, the storage of the step (c) is performed in a standby area.

  29. 28. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 24 to 27, the storage of the step (c) is performed in a stocker.

  30. 30. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 25 to 29, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container. Is done by.

  31. 30. In the method of manufacturing a semiconductor integrated circuit device according to any one of 25 to 29, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from a first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the second breathing hole of the wafer transfer container.

  32. 32. In the method of manufacturing a semiconductor integrated circuit device according to any one of 24 to 31, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.

  33. 32. In the method of manufacturing a semiconductor integrated circuit device according to any one of 24 to 31, the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

34. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating wiring metal which is formed in an insulating film on the first main surface of the wafer in the etching chamber of the dry etching apparatus and which exists on the bottom surface of the via in the embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a wiring metal diffusion barrier metal film on the surface of the insulating film and the inner surfaces of the wiring grooves and vias;
Here, the step (a) includes the following substeps:
(A1) performing a dry etching process in an etching atmosphere containing a fluorocarbon-based etching gas in the etching process chamber;
(A2) A step of performing plasma treatment in a non-oxidizing atmosphere containing nitrogen as one of main components in the etching chamber after the step (a1).

  35. In the method for manufacturing a semiconductor integrated circuit device according to the item 34, the etching atmosphere does not substantially contain a component that generates an oxidizing reactive species.

  36. 36. In the method for manufacturing a semiconductor integrated circuit device according to the item 34 or 35, the etching atmosphere contains trifluoromethane.

37. 37. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 34 to 36, the step (b) includes the following substeps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.

  38. 38. In the method for manufacturing a semiconductor integrated circuit device according to the item 37, the wafer transfer container is a sealed type.

  39. 38. In the method for manufacturing a semiconductor integrated circuit device according to the item 38, the wafer transfer container is a hoop.

  40. 40. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 34 to 39, the storing of the step (c) is performed in a stocker.

  41. In the method for manufacturing a semiconductor integrated circuit device according to any one of 37 to 40, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from a first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the second breathing hole of the wafer transfer container.

  42. 42. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 34 to 41, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.

  43. 42. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 41, the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

  44. 42. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 41, the non-oxidizing dry gas atmosphere does not substantially contain oxygen gas.

45. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surface of the wiring groove and via;
Here, the step (a) includes the following substeps:
(A1) A step of performing a dry etching process in an etching atmosphere containing a fluorocarbon-based etching gas and a nitrogen gas as main components in the etching process chamber.

  46. 46. In the method for manufacturing a semiconductor integrated circuit device according to the item 45, the etching atmosphere is a non-oxidizing atmosphere.

  47. 47. In the method for manufacturing a semiconductor integrated circuit device according to the item 45 or 46, the etching atmosphere does not substantially contain oxygen gas.

  48. 48. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 47, the nitrogen gas concentration in the etching atmosphere is 20% or more in a flow rate ratio.

  49. 48. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 47, a nitrogen gas concentration in the etching atmosphere is 30% or more in a flow rate ratio.

  50. 50. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 49, the oxygen gas concentration in the etching atmosphere is less than 0.5% in flow rate ratio.

51. 50. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 49, the step (a) further includes the following substeps:
(A2) A step of performing plasma treatment in a non-oxidizing atmosphere containing nitrogen as one of main components in the etching chamber after the step (a1).

  52. 52. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 51, the etching atmosphere does not substantially include a component that generates an oxidizing reactive species.

  53. 53. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 52, the etching atmosphere includes trifluoromethane.

54. 54. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 53, the step (b) includes the following substeps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.

  55. 54. In the method of manufacturing a semiconductor integrated circuit device according to the item 54, the wafer transfer container is a sealed type.

  56. 55. In the method of manufacturing a semiconductor integrated circuit device according to 55, the wafer transfer container is a hoop.

  57. 57. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 56, the storage of the step (c) is performed in a stocker.

  58. 58. In the method of manufacturing a semiconductor integrated circuit device according to any one of 54 to 57, the storage in the step (c) supplies the non-oxidizing dry gas atmosphere from a first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the second breathing hole of the wafer transfer container.

  59. 59. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 58, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.

  60. 59. In the method for manufacturing a semiconductor integrated circuit device according to any one of the items 45 to 58, the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts or sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Rather, each part of a single example, one of which is a partial detail of the other or a part or all of a modification. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

3. In semiconductor technology, an insulating film frequently used is an organic insulating film mainly containing an organic material (including a copolymer of an organic monomer and an inorganic monomer in addition to a polyimide film, a BCB film, etc.) and The inorganic insulating film is mainly composed of an inorganic material as a main component. Of the inorganic insulating films, the silicon-containing inorganic insulating film is most frequently used. This silicon-containing inorganic insulating film is divided into a silicon oxide film (silicon oxide base insulating film) and a non-oxide silicon film (generally oxygen content is several at% or less, usually about 0.5 at% or less for SiCN or the like). Broadly divided. Typical examples of the non-oxide silicon film are non-silica / glass-based silicon-containing inorganic insulating films such as silicon nitride film (SiN or Si ₃ N ₄ ), silicon carbide (SiC), SiCN (SiN, SiC, SiCN, etc.) But generally contains a significant amount of hydrogen and does not exclude other trace contents). Furthermore, it goes without saying that not only stoichiometric compounds and the like but also non-stoichiometric compounds and the like are included.

  Here, the term “silicon oxide film” refers not only to relatively pure undoped silicon oxide (FS), but also to FSG (Fluorosilicate Glass), TEOS-based silicon oxide, and SiOC (Silicon). Oxicarbide) or carbon-doped silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, inorganic siloxane HSQ (Hydrogen Silsesquioxane) and organic siloxane MSQ (Methyl Silsesquioxane) and other SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC) and other coated silicon oxide (coated silica glass) Needless to say, it includes a silica-based low-k insulating film (porous insulating film) in which pores are introduced into similar members, and a composite film with other silicon-based insulating films having these as main components. Absent. The order of the second and subsequent elements in SiOC and SiCN is generally the order of the element composition. Therefore, silicon oxide carbide SiCO has a lower oxygen composition than carbon-doped silicon oxide SiOC.

  The carbon-doped silicon oxide film and the MSQ film contain a considerable amount of organic components, but are classified as inorganic films in comparison with the organic polymer insulating film.

  4). Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  5). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  6). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but an insulating substrate such as an epitaxial wafer or an SOI wafer and a semiconductor layer or the like. Needless to say, the composite wafer includes a glass substrate or the like for forming a semiconductor device or a semiconductor integrated circuit device thereon. In addition, depending on the situation, not only these non-element-formed substrates but also the entire semiconductor device or semiconductor integrated circuit device forming process on the wafer is also referred to as a wafer.

  7. The device surface is a main surface of a wafer on which a device pattern corresponding to a plurality of chip regions is formed by lithography.

  8). The resist pattern refers to a film pattern obtained by patterning a photosensitive resin film (resist film) by a photolithography technique. This pattern includes a simple resist film having no opening at all for the portion. In general, the photosensitive resin film and photolithography are based on light, but in this application, for the sake of convenience, a resist sensitive to an electromagnetic wave having a wavelength shorter than that of an electron beam or ultraviolet light is used unless otherwise specified. Including pattern forming technology.

  9. The embedded wiring structure refers to damascene embedded wiring represented by the dual damascene method and single damascene method (including some components in the process of production). Wiring trenches and vias made in (including cap layer, insulating copper diffusion barrier film, etc.), copper diffusion barrier metal film embedded in them, good conductor metal such as copper (in the case of copper damascene, It is composed of a wiring member (wiring metal) or the like whose main component is copper (which is silver in silver damascene).

  In general, when there is no need to distinguish between the two, the interlayer and in-layer insulating films are collectively referred to as an interlayer insulating film or ILD (Interlayer Dielectric Film).

  10. An insulating copper diffusion barrier film (more generally, an insulating wiring metal diffusion barrier film) is an inorganic insulating film having a diffusion barrier property provided to prevent the wiring metal from undesirably diffusing. . In general, a non-silica glass-based silicon-containing inorganic insulating film such as a silicon nitride film (SiN), silicon carbide (SiC), or SiCN is used. Further, as a special one, there is SiCO (an oxide based on SiC and having an oxygen content of almost 20%). On the other hand, the oxygen content such as SiOC is often about 20% or more.

  11. A copper diffusion barrier metal film (more generally, a wiring metal diffusion barrier metal film) is a metal film having a diffusion barrier property, a metal nitride film, or These composite membranes. Generally, it is a single film or a composite film containing a refractory metal alone or its nitride as a main component. Usually formed by sputtering or CVD. When the wiring metal metal is a copper-based member and the interlayer insulating film is a silicon oxide film (SiO-based insulating film), tantalum, titanium, ruthenium-based materials are used, and Cu / TaN / Ta / SiO, Cu / TiN are used from the upper layer. / T / SiO, Cu / Ru / SiO (in the case of ruthenium, there is a merit that a copper seed layer is not necessary) is often used.

  12 The inert gas includes not only noble gases such as helium and argon but also nitrogen gas and the like. Of course, it goes without saying that the inert gas is also sufficiently removed of moisture to the extent that it is normally used in semiconductor lines. “Dry gas atmosphere” indicates that water has been sufficiently removed to such an extent that it is normally used in semiconductor lines.

  13. Anti-reflective coating, anti-reflective coating (TARC) or top anti-reflective coating (TARC) or bottom anti-reflective coating (BARC) has the feature of absorbing or attenuating UV light, reducing standing waves and halation generated during exposure. Therefore, a film formed on the upper or lower portion of the resist film. There are anti-reflective films made of coating-type organic materials (some resist-like non-photosensitive coating materials are water-soluble) and inorganic anti-reflective films made by CVD or the like. As the inorganic antireflection film, a TiN film, a SiON (Silicon Oxynitride) film (a film obtained by adjusting the refractive index by adding nitrogen to silicon oxide) or the like is frequently used. Here, the SiON film generally belongs to a silicon oxide film.

  14 A bay refers to a group of devices made up of a plurality of semiconductor manufacturing devices arranged together, and various semiconductor manufacturing devices are often arranged in a clean room in units of bays.

  15. A FOUP is a sealed wafer storage container that is formed of a shell that is a holding portion for storing a wafer and a door that is an opening / closing door portion, and has the door on its side, and holds the wafer in a sealed space. By doing so, the wafer can be protected from foreign substances or chemical contamination in the atmosphere. Even if sealed, it should be a pseudo-sealed type, and it has a pair of breathing holes for adjusting the internal and external air pressure. However, a filter (breathing filter) is attached to the breathing hole so that dust does not enter.

  16. The SMIF (Standard Mechanical InterFace) pod is used in particular before a 200φ wafer, and is formed of a shell that is a holding portion for storing a wafer and a door that is an opening and closing door portion, and a sealed wafer storage container having the door at the bottom. Similarly to FOUP (used after 300φ wafer), the wafer can be protected from foreign substances or chemical contamination in the atmosphere by holding the wafer in the sealed space. These two are collectively referred to as a “sealed wafer transfer container”.

  17. The stocker (the “bay station” corresponds to this in the embodiment) is a place where the interbay transfer and the transfer within the bay are relayed, and the wafers stored in a wafer storage container such as a FOUP or SMIF pod are here. After being temporarily waiting or stored, it is transported into the bay. Here, the wafer standby place is widely referred to. It doesn't matter whether the wafer is stopped or moving.

  18. An RGV (Rail Guided Vehicle) is a transport vehicle used for transporting a wafer storage container such as a FOUP or SMIF pod in a bay, and means a tracked transport vehicle that travels on a track such as a track rail. Compared to an AVG (Automatic Guided Vehicle) that travels on a trackless track, it is possible to perform a stable travel, and therefore, travel control is easy.

  19. AGV is a transport vehicle used for transporting wafer storage containers such as FOUPs or SMIF pods in the bay like RGV, and does not require track rails and follows a guide tape stretched on the floor. Say a trackless transport vehicle.

  20. An OHT (Over-head Hoist transport) is a transport vehicle used for transporting wafer storage containers such as a FOUP or SMIF pod between bays and travels along a track such as a track rail laid on the ceiling. Say a transport vehicle.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

(Embodiment)
1. Description of semiconductor wafer process configuration and processing flow used in this embodiment (mainly FIGS. 1 to 20)
In this section, the description will focus on the configuration of the wafer line used to implement this embodiment and the movement of the wafer to be processed therein.

  FIG. 1 is an overall plan view showing a wafer transfer system of the semiconductor manufacturing line according to the first embodiment.

  Heat treatment apparatus (including thermal oxidation apparatus, plasma nitridation apparatus, etc.), ion implantation apparatus, etching apparatus (including dry etching apparatus, wet etching apparatus, etc.), film forming apparatus (used for semiconductor (circuit or element) manufacturing) CVD apparatus, sputtering apparatus, plating apparatus, etc.), CMP apparatus (including post-CMP cleaning apparatus, etc.), cleaning apparatus (including vapor cleaning apparatus, wet cleaning apparatus, wet polymer removal apparatus, etc.), photoresist processing apparatus Various manufacturing apparatuses (semiconductor manufacturing apparatuses) PE such as a photoresist coating apparatus and an exposure apparatus are divided into a plurality of bays (apparatus groups) and arranged in the clean room CR. The wafer transfer system in the clean room CR corresponds to this arrangement, and includes a bay station (stocker) BS (standby area) that transfers between bays, transfers in the bay, and relays them.

  The transfer between the bays is performed by OHS or the like that transfers a wafer via a track RL1 installed on the ceiling in the clean room CR. On the other hand, the in-bay transport is performed by RGVfc traveling on the track rail RL2 laid on the floor of the clean room CR.

  FIG. 2 is a perspective view showing an example of the external configuration of the FOUP according to the first embodiment, and FIG. 3 is a cross-sectional view showing a state in which the FOUP is arranged on the load port of the manufacturing apparatus PE. 4 is a plan view showing the bottom surface of the FOUP.

  The FOUP (hoop or sealed container) cuc has a shell SHL as a wafer holding part and a door DR (hoop side door) as an opening / closing door part. A top flange TFG that is gripped when the FOUPcuc is automatically conveyed by the robot is provided on the upper part of the shell SHL, and a manual hand MH and a side rail SR are provided on the side of the shell SHL. The manual hand MH is used, for example, when lifting the FOUPcuc manually, and the side rail SR is used, for example, when scooping the FOUPucc by a robot. A breathing filter BRZ is provided at the bottom of the shell SHL. The breathing filter BRZ is a filter provided to eliminate a pressure difference between the inside and the outside of the FOUPcuc (shell SHL). The breathing filter BRZ prevents the intrusion of dust into the FOUPcuc (shell SHL). The pressure inside the SHL) is adjusted. By eliminating the pressure difference between the inside and outside of the FOUPcuc (shell SHL), for example, when the door DR is opened, it is possible to prevent the generation of an air flow due to the pressure difference. It is possible to prevent dust from getting into (shell SHL), and to prevent dust from adhering to wafer WFR. Further, a registration pin hole RPH for determining the position of the FOUPcuc and a latch key hole LKH for opening the door DR by a robot are provided outside the door DR.

  The load port LP of the manufacturing apparatus PE includes a FIMS (Standard Mechanical Interface) door FDR (apparatus side door) on the manufacturing apparatus PE side and a seal material (not shown) provided around the FIMS door FDR. The FOUPcuc door DR and the FIMS door FDR can be matched by advancing the FOUPcuc. Next, the latch key LK is inserted into the latch key hole LKH provided in the door 3 and rotated, whereby the clamping mechanism CRP provided in the door DR is detached, and the door DR is fixed to the FIMS door FDR.

  A FOUP cuc in which a predetermined number of wafers WFR into which a semiconductor device or an IC (Integrated Circuit) is built is stored, for example, from a bay station BS installed in the manufacturing line to the manufacturing apparatus PE. Further, the wafer WFR is placed inside the FOUPcuc and moves between the manufacturing apparatuses PE. However, when the diameter of the wafer WFR is a large diameter such as 300 mm, for example, the FOUP cuc containing the wafer WFR has a weight of about 8 kg or more, and therefore it is difficult to transport the semiconductor manufacturing line manually. Therefore, FOUPcuc is automatically transported using RGVfc and OHT as shown in FIG.

  Although FIG. 1 shows the case where the FOUP in-bay conveyance is performed by RGVfc, as shown in FIG. 5, the in-bay conveyance may be performed using OHThtr. In this case, in OHThtr, FOUPcuc is lowered onto the load port LP of the semiconductor manufacturing apparatus 21 using a hoist mechanism HM provided in the OHThtr. As shown in FIG. 6 (see also FIG. 3), a plurality of (for example, three) kinematic pins KTP (positioning pins) are formed in the load port LP. On the other hand, a plurality of (for example, three) G-shaped grooves (hereinafter referred to as V-grooves) GV having a pair of inclined surfaces and engaging with the kinematic pins KTP are formed on the bottom of the shell SHL of the FOUP 1. Yes. As shown in FIG. 7, the position of the FOUPcuc on the load port LP can be fixed by accommodating the kinematic pin KTP in the V groove GV. After fixing the position of the FOUPcuc on the load port LP, the hoist mechanism HM is detached and the FOUPcuc is left at the transfer location on the load port LP.

  FIG. 8 is a perspective view showing an example of the inner configuration of the door DR of the FOUPcuc. Inside the door DR, a sealing material (packing) SM, a retainer RTN, and a clamping mechanism CM1 for maintaining hermeticity are provided. The sealing material SM made of a rubber material is provided in order to maintain the hermeticity of the FOUPcuc. The retainer RTN is provided to hold the wafer WFR accommodated in the FOUPcuc, and is formed of flexible teeth made of molded plastic. The clamping mechanism CM1 is provided to fix the door DR to the shell SHL, and operates via the latch key hole LKH. That is, the door DR engages with the inside of a door flange (not shown) provided in the shell SHL, and latches to engage with the groove of the door flange by entering and exiting from the outer periphery of the door DR. (Clamping mechanism).

  As shown in FIG. 9, the wafers WFR accommodated in the FOUPcuc can be placed one by one on a beam called wafer teeth WT, and a plurality of wafers WFR are spaced apart from each other by a distance of, for example, about 10 mm. They are arranged in the vertical direction.

FIG. 10 is an explanatory view of the manufacturing apparatus PE shown in FIG. 1 (more details will be described with reference to FIGS. 21 and 32). As shown in FIG. 10, the manufacturing apparatus PE shows a mini environment ME, a load / lock LL, a load port LP, and the like that include a fan filter unit FFU. The fan filter unit FFU is an air purifier that integrates a ULPA (Ultra Low Penetration Air-filter) filter and a small blower. The mini-environment ME is an enclosure for isolating semiconductor products from contamination sources. It refers to a locally clean environment. Further, the mini-environment ME is separated from the outside by the casing surface SF, and the cleanliness inside the mini-environment ME is maintained at, for example, Class1. Here, Class 1 refers to cleanliness in which the number of dust particles having a particle diameter of 0.1 μm or more contained in 1 ft ³ (1 ft = 30.48 cm) air is 1 or less. The cleanliness outside the mini-environment ME is, for example, Class 1000.

  As shown in FIG. 10, when the position of the FOUPucc is fixed on the load port LP, the FOUPucc advances toward the housing surface SF. Next, the load port door opening / closing mechanism LDO is driven to remove the door DR from the shell SHL and move it to the lower part of the manufacturing apparatus PE. With the door DR removed, the wafer WFR is taken out from the opening of the shell SHL by the wafer transfer robot HR provided in the manufacturing apparatus PE, and passes through the load lock chamber LL to produce the manufacturing apparatus PE (for example, the plasma processing apparatus 101 of FIG. The wafer 102 is transferred to a processing chamber (for example, the processing chamber 111 of the plasma processing apparatus 101 in FIG. 21 or the processing chamber 112 of the polymer removing apparatus 102 in FIG. 21), and a predetermined manufacturing process (wafer processing) is performed on the wafer WFR. After completion of the manufacturing process, the wafer WFR is returned again to the shell SHL (hoop cuc) by the wafer transfer robot HR.

  As shown in FIGS. 11 to 13, during storage of the FOUPcuc at the bay station BS, for example, one of the breathing filters BRZ provided at two locations on the bottom surface of the FOUPcuc (first breathing hole, gas inlet) A pipe PP is attached, a non-oxidizing dry gas is allowed to flow into the FOUPcuc from the pipe PP, and the atmosphere in the FOUPucc is exhausted from the other breathing filter (second breathing hole, gas exhaust port) BRZ. Here, FIG. 11 is an explanatory view showing the storage means of the FOUPcuc at the bay station BS, FIG. 12 is a cross-sectional view of the FOUPcuc being stored at the bay station BS, and FIG. 13 is being stored at the bay station BS. It is a top (bottom) figure of FOUPcuc. For example, the pipe PP is attached to the bottom surface (breathing filter BRZ) of the FOUPcuc by its own weight and forms a flow of non-oxidizing dry gas in the FOUPcuc (see FIG. 14). Further, in the FOUPcuc, the flow of the nonoxidizing drying gas is changed by providing the deflector plate CFB on the breathing filter BRZ for introducing the nonoxidizing drying gas into the FOUPcuc (see FIG. 15), or the nonoxidizing into the FOUPcuc The non-oxidizing drying gas may flow more widely in the FOUPcuc by providing the nozzle NZL on the breathing filter BRZ for introducing the oxidizing drying gas (see FIG. 16). In addition, a valve that opens upon detecting the presence of FOUPcuc may be attached to the pipe PP. The non-oxidizing dry gas exhausted from inside the FOUPcuc is removed from the bay station BS by the vacuum exhaust means provided near the breathing filter (second breathing hole, gas exhaust port) BRZ for discharging the non-oxidizing dry gas. Is discharged.

In the present embodiment, an inert gas (for example, N ₂ gas or Ar (argon gas), for example) can be exemplified as the non-oxidizing drying gas. Further, the flow rate of the non-oxidizing drying gas into the FOUP cuc is set so as not to wind up dust existing in the FOUP cuc. In the first embodiment, when the volume in the FOUP cuc is about 30 l, the non-oxidizing drying gas It can be exemplified that the gas flow rate is about 1 SLM (Standard Liter per Minute) to 20 SLM. Here, FIG. 19 shows the relationship between the amount of N ₂ gas flowing into the FOUP cuc and the O ₂ concentration in the FOUP cuc when the non-oxidizing drying gas is N ₂ gas. 4 shows the case where the flow rate of N ₂ gas flowing into the tank is four types of 20 SLM, 10 SLM, 5 SLM, and 0.6 SLM. As shown in FIG. 19, the O ₂ concentration in the FOUP cuc decreases as the amount of N ₂ gas flowing into the FOUP cuc increases. FIG. 20 shows the relationship between the amount of N ₂ gas flowing into the FOUPcuc and the dew point of the atmosphere inside the FOUPcuc when the non-oxidizing drying gas is N ₂ gas, and flows into the FOUPcuc. It shows a case where the flow rate of N ₂ gas is 4 types of 10 SLM, 5 SLM, 3 SLM, and 0.5 SLM. As shown in FIG. 20, the dew point of the atmosphere in the FOUPcuc decreases as the amount of N ₂ gas flowing into the FOUPcuc increases. That is, the moisture in the atmosphere in the FOUPcuc decreases as the amount of N ₂ gas flowing into the FOUPcuc increases.

2. Outline of process flow in this embodiment (mainly FIGS. 21 and 22)
In this section, the outline of the process flow in the present embodiment in the wafer line described in the preceding section 1 will be described in relation to the background problem.

  FIG. 21 is a process block flow showing the main part of the manufacturing method of the semiconductor integrated circuit device according to the present embodiment (the fourth layer wiring M4 will be described as an example, see FIG. 25). FIG. 22 is a device cross-sectional follow corresponding to this. Here, a via first process that does not use a hard mask will be described as an example.

  Based on FIGS. 21 and 22, an outline of a process flow in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described. As shown in FIG. 22, the third layer wiring is composed of a copper wiring 2 or the like embedded in a wiring groove provided in the third layer interlayer insulating film 1, and an insulating barrier film (insulating property) is formed thereon. An SiCN film 3 (non-silicon oxide silicon-containing inorganic insulating film) is formed as a copper diffusion barrier film. On this SiCN film 3, a silicon oxide film 4 as a fourth interlayer insulating film is formed by CVD or the like. Here, in the via first method, the via 5 is opened by dry etching (via etching) in an etching atmosphere such as fluorocarbon gas or argon gas using the photoresist film 21 or the like as a mask. Here, the via resist pattern 21 is removed. Via fill agent 10 is applied to fill the via. Etch back unnecessary via fill 10. Thereafter, a new photoresist 22 is applied and patterned. Next, as shown in FIG. 22, with the new photoresist film 22 or the like as a mask, the trench 6 (wiring groove) is dry etched (trench etching) in an etching atmosphere such as fluorocarbon gas or argon gas. Is opened. Here, the photoresist 22 and the via fill agent 10 are removed.

  Next, as shown in FIG. 22, in order to selectively remove the SiCN film 3 at the bottom of the via, under a condition that a sufficient selection ratio is obtained with respect to the silicon oxide film (the silicon oxide film is slightly etched). Dry etching (liner etching) is performed in an etching atmosphere such as fluorocarbon gas or argon gas (insulating copper diffusion barrier film etching step 91 in FIG. 21). Here, this liner etching is performed in the processing chamber 111 of the dry etching apparatus 101 as shown in FIG.

  Next, nitrogen plasma processing is performed on the wafer WFR to be processed in the processing chamber 111 in a non-oxidizing gas atmosphere in which the atmosphere is changed and nitrogen is a main component (nitrogen plasma processing 92 in FIG. 21). ). This treatment is not essential, but it has the effect of reducing the polymer in addition to stabilizing the surface state of the via inner surface after etching.

  Thereafter, as shown in FIG. 21, the processing target wafer WFR is returned to the hoop cuc. Then, the hoop cuc stands by at the stocker BS at an appropriate position. At that time, the wafer WFR in the hoop cuc is stored in a purge gas (non-oxidizing dry gas) containing nitrogen gas as a main component (non-oxidizing dry gas atmosphere storage step 93 in FIG. 21).

  As shown in FIG. 21, after storing the nitrogen, the hoop cuc moves to the polymer removal cleaning device 102 and is connected thereto. That is, after the wafer transfer container is separated from the liner etching apparatus (including the mini-environment, the same applies hereinafter), before the wafer transfer container is connected to the polymer removal apparatus, the non-oxidizing dry gas atmosphere Provide a storage period in the middle (or in a non-oxidizing gas atmosphere). The atmosphere is preferably a fluid atmosphere. That is, it is important that the atmosphere is continuously or intermittently replaced (this is generally referred to as “purging”). Further, the wafer transfer container may be replaced with another one on the way. That is, lot reorganization may be performed.

  Next, as shown in FIG. 22, removal of the polymer deposited in the via 5 at the time of etching is performed by wet processing using, for example, an ammonium fluoride chemical solution (polymer removal cleaning step 94 in FIG. 21). This polymer removal process is performed in the wet treatment chamber 112 of the polymer removal washing apparatus 102 as shown in FIG.

  Thereafter, as shown in FIG. 22, a barrier metal is formed in the formed via 5 and trench 6 by sputtering or CVD (copper diffusion barrier metal film forming step 95 in FIG. 21), and if necessary, copper is formed on the barrier metal. A seed layer is formed by, for example, sputtering (barrier / seed film formation).

  Subsequently, the via 5 and the trench 6 are filled with copper by copper plating and annealing (copper plating and annealing). Thereafter, unnecessary metal members are removed by metal CMP (copper CMP), whereby the fourth-layer wiring of the embedded wiring structure 47 is completed.

3. Non-oxidizing dry gas storage and via bottom copper loss failure in this embodiment (mainly from FIGS. 28 to 33)
In this section, the relationship between the process of the present embodiment and avoidance of the cause of via bottom copper loss will be described.

  FIG. 28 shows the wafer yield and the positional relationship of the wafer WFR in the hoop cuc when the removal of the polymer is completed without storing nitrogen (the slot number is 1 at the bottom. Here, one lot consists of 12 sheets). It is a data plot figure showing an example). As can be seen here, it can be seen that the yield decreases as the slot goes up, except for the top slot. Therefore, this mode failure is called slot dependency failure.

  FIG. 29 is a data plot diagram showing slot dependency failure and waiting time dependency before polymer removal. From this, it can be seen that when the standby time exceeds 2 hours, the defect rate rises rapidly.

  FIG. 30 is a model of a failure mechanism that is established based on these data. As shown in FIG. 30A, the polymer 11 is thickly deposited in the via immediately after the liner etching. Here, when stored in the atmosphere (although in the hoop), oxidizing species such as moisture and oxygen in the air are taken into the polymer 11. At this time, the fluorine remaining on the wafer WFR acts as a catalyst to promote the oxidation of copper to produce a copper oxide 15 as shown in FIG. It is considered that the copper oxide 15 is dissolved when the polymer is removed as shown in FIG. 30 (c).

  This becomes clearer from FIGS. 32 and 33. FIG. 32 is a side cross-sectional view showing a combined state of the liner / dry etching apparatus 101 and the hoop cuc. Here, the wafer number matches the slot number. Liner etching usually begins with slot number 1 and ends with slot number 12. Accordingly, the lower layer wafers WFR1, WFR2, and WFR3 (with a smaller slot number) are left in the post-processing hoop cuc for a relatively long time. In the meantime, it is considered that a considerable amount of the fluorine component remaining on the wafer WFR is eliminated by the downflow (or its branch flow) in the local clean room (mini-environment) ME. On the other hand, the wafer WFR11 (upper intermediate position wafer) of the upper layer other than the uppermost layer (the upper intermediate position wafer) is returned to the hoop cuc after the liner etching, and immediately separated from the local clean room ME and waits in the hoop cuc. It will be. Therefore, it is confined in the hoop cuc before being sufficiently cleaned by the downflow in the local clean room ME. As for the uppermost wafer WFR12, since the device surface generally faces upward, the remaining fluorine component easily dissipates due to the large space above. That is, as shown in FIG. 33, in the lower and uppermost wafers WFR1, WFR2, WFR3, and WFR12, when they are trapped in the hoop, there is almost no residual fluorine component, or they easily diffuse in the hoop cuc. . On the other hand, the upper wafer WFR11 other than the uppermost layer has a considerable residual fluorine component and has a narrow wafer interval (interval between WFRn and WFRn + 1 in FIG. 33), so that sufficient diffusion into the air cannot be expected. . Therefore, it can be estimated that defects frequently occur in these upper intermediate position wafers.

  On the other hand, FIG. 31 is a data plot diagram corresponding to FIG. 28 when nitrogen storage according to the present embodiment is applied. From this, it is understood that the failure mode is almost disappeared by applying nitrogen storage.

From these facts, the following prescription becomes clear. Of course, all of the following combinations that can be combined may be implemented, or only a part may be implemented.
(1) The waiting time in the outside air in the wafer transfer container between the liner removal and the removal of the polymer is set to be as short as possible within 2 hours, and stored while purging in a non-oxidizing dry gas atmosphere as much as possible ( Store in flowing non-oxidizing dry gas atmosphere). This prevents copper oxidation during storage (see section 1). Here, “non-oxidizing” means that the content of mainly oxygen, moisture, etc. is so small that the oxidation reaction does not substantially proceed.
(2) The liner, etching gas should minimize the accumulation of organic polymer. That is, increase the gas composition with less hydrogen and more fluorine (see Section 4). This reduces the amount of polymer that causes oxidation.
(3) Reduce the amount of inorganic polymer (copper oxide, etc.) by suppressing copper oxidation during liner etching as much as possible. That is, the amount of oxygen added is reduced as much as possible or is set to “0” (see section 4). Nitrogen or the like is added to form a nitride film on the copper surface to prevent oxidation (see section 4). Since this nitride film is very thin, there is no problem in terms of electrical characteristics.
(4) Immediately after liner etching, a nitride film is formed on the copper surface by nitrogen plasma treatment or the like to prevent subsequent oxidation during storage (see section 5).

4). Explanation of various liner / etching treatment atmospheres in this embodiment (mainly FIG. 22)
Various detailed conditions of the liner etching described in the section 2 (FIG. 22 and the like) can be selected as appropriate from the following examples. Hereinafter, a case where the liner film 3 is a SiCN film will be described as an example, and a plurality of examples will be described. Either method can reduce the amount of polymer compared to using difluoromethane and oxygenated chemistry. Of course, it can also be processed using a gas system such as CH ₂ F ₂ / O ₂ / Ar that has been proven in the past. Further, although the following processing time depends on the film thickness, it is generally considered to be about 30 to 90 seconds. Here, although the fluoro-carbon system is exemplified as the etching gas here, the use of other fluorine-containing etching gases is not excluded.

(1) Oxygenation chemistry Detailed conditions are as follows. For example,
Etching device: parallel plate type for 300φ wafer, processing by placing the wafer on the lower electrode;
High frequency of upper electrode: 60MHz (power 1500W);
High frequency of the lower electrode: 2 MHz (power 225 W);
Processing pressure: 3.3 Pa;
Wafer temperature: 20 degrees Celsius;
Gas flow rate: CHF ₃ / O ₂ / Ar = 20/12/800 sccm.

  This condition was based on oxygen-added chemistry with stable etching characteristics, and the etching gas was changed from di-fluoro-methane to tri-fluoro-methane, thereby increasing the etching gas fluorine and reducing the amount of organic polymer. Is. In this case, the oxygen composition is preferably about 1 to 5% in flow rate ratio. It is not excluded to use other than this range depending on the size of other parameters.

(2) Tri-fluoro-methane chemistry Detailed conditions are as follows. For example,
Etching device: parallel plate type for 300φ wafer, processing by placing the wafer on the lower electrode;
High frequency of upper electrode: 60MHz (power 200W);
High frequency of the lower electrode: 2 MHz (power 150 W);
Processing pressure: 10.7 Pa;
Wafer temperature: 15 degrees Celsius;
Gas flow rate: CF ₄ / CHF ₃ / N ₂ = 110/20/300 sccm.

  This condition changes the etching gas from di-fluoro-methane to tri-fluoro-methane and substantially eliminates oxygen (preferably approximately “0”, at most less than 0.5% by flow ratio). At the same time, the argon gas, which is a dilution gas, is replaced with nitrogen gas. The nitrogen composition is preferably 30% or more in terms of flow ratio, but may be 20% or more depending on other conditions. The upper limit of the flow rate ratio of nitrogen may be close to 100% depending on the combination of etching and is usually considered to be about 90% to 95%. Note that a part of argon may be replaced with nitrogen. Further, it does not exclude additive gases that do not substantially generate other oxidizing species. Needless to say, a non-oxidizing additive gas may be added. The same applies to the following (3).

  The effect of this nitrogen is considered to be not only the stabilization of etching by adjusting the pressure or dilution, but also the stabilization of the surface of copper and vias by nitrogen radicals.

(3) Carbon tetrafluoride chemistry Detailed conditions are as follows. For example,
Etching device: parallel plate type for 300φ wafer, processing by placing the wafer on the lower electrode;
High frequency of upper electrode: 60 MHz (power 300 W);
High frequency of the lower electrode: 2 MHz (power 300 W);
Processing pressure: 4 Pa;
Wafer temperature: 15 degrees Celsius;
Gas flow rate: CF ₄ / N ₂ = 175/100 sccm.

  This condition is almost the same as (2) above, but organic polymer deposition can be further reduced by eliminating trifluoromethane. It is considered that this can reduce copper corrosion when left after the liner etching.

(4) Summary of this section Since the etching conditions of (2) and (3) can be considered to be able to perform the same processing as the nitrogen plasma processing of section 5 simultaneously, in these processes, additional nitrogen is used. There is a high possibility that the plasma treatment can be omitted. Even under the etching condition (1), the problem is highly likely to be avoided if nitrogen storage is thoroughly carried out.

5). Description of nitrogen plasma treatment in the present embodiment (mainly FIGS. 21 and 22)
Details of the nitrogen plasma treatment 92 described in Section 2 with reference to FIG. 21 will be described. This process is desirably performed continuously in the same processing chamber 111 (FIG. 21) as the liner dry etching 91, but it is needless to say that the process is not limited thereto. When processing continuously in the same processing chamber, the effect of shortening the processing time is great.

Detailed conditions are as follows. For example,
Etching device: parallel plate type for 300φ wafer, processing by placing the wafer on the lower electrode;
High frequency of upper electrode: 60MHz (power 2500W);
High frequency of lower electrode: 2MHz (power 0W);
Processing pressure: 5.3 Pa;
Wafer temperature: 15 degrees Celsius;
Gas flow rate: N ₂ = 400 sccm.

  The atmosphere preferably contains nitrogen as a main constituent and is non-oxidizing. The effect of nitrogen is considered to be due to a very thin copper nitride film serving as an oxidation mask due to nitridation of the copper surface by nitrogen radicals.

  In general, the processing time is considered to be about 10 to 20 seconds. Of course, the difference in various parameters does not preclude other processing times.

6). Explanation of various damascene process flows in this embodiment (mainly FIGS. 23 and 24)
Various examples of the damascene process flow described in Section 2 with reference to FIG. 22 will be described. Since each wiring layer uses the same manufacturing method, the fourth layer will be described by taking the fourth layer as an example, as described above.

(1) Process using an intermediate stopper (refer mainly to FIG. 23 and FIGS. 26 and 27 for the detailed structure)
FIG. 23 shows an example of a dual damascene process using a hard mask and an intermediate stopper film. Details of each film will be described in detail in Section 7. As shown in FIG. 23, the third-layer wiring is completed by depositing the SiCN film 3 by the plasma CVD method. An interlayer insulating film 14 is formed on this SiCN film 3 by plasma CVD. Thereafter, the interlayer insulating film 14 is flattened by a CMP process. A SiCN film as an intermediate stopper film 8 is formed thereon by a plasma CVD method. Further, the in-layer insulating film 24 is formed by a plasma CVD method. A SiN mask layer 9 is formed thereon by plasma CVD. The SiN mask layer 9 is patterned to make a trench hard mask in advance. Next, using the photoresist film 21 as a mask, the via 5 is opened by dry etching (via etching) in an etching atmosphere such as fluorocarbon gas, argon gas and oxygen gas. Here, the via resist pattern 21 is removed. Next, the trench 6 is opened by dry etching (trench etching) in an etching atmosphere such as fluorocarbon gas, argon gas, and oxygen gas using the hard mask 9 that has been previously prepared. Is done.

  Here, the liner film 3 is removed by dry etching (liner etching) using the etching gas containing fluorocarbon described in Section 4. At the same time, the hard mask 9 is also removed. If necessary, the nitrogen plasma treatment described in Section 5 is subsequently performed.

  Thereafter, a barrier metal film is formed by sputtering (or CVD). On top of that, a copper seed layer is formed by sputtering (or CVD) if necessary. Thereafter, copper plating is performed by electroplating or the like, and after an copper annealing process or the like, unnecessary copper is removed and the copper wiring 7 is placed in the trenches and vias (parts of the fourth and third layers). The copper buried wiring structure 47 is completed once.

(2) Process Using Via Fill FIG. 24 is an example of a dual damascene process that uses a hard mask but does not use an intermediate stopper film. As shown in FIG. 24, the third-layer wiring is completed by depositing the SiCN film 3 by the plasma CVD method. A plasma TEOS film 14 as an interlayer insulating film is formed on the SiCN film 3. Here, the interlayer insulating film 14 is flattened by a CMP process. Thereafter, an FSG film as an in-layer insulating film is deposited by plasma CVD. Further thereon, a hard mask antireflection film SiON film 9 is deposited by plasma CVD. The SiON film 9 is patterned to form a hard mask for via etching. For example, the via 5 is opened by dry etching (via etching) in an etching atmosphere such as fluorocarbon gas, argon gas, and oxygen gas. Here, the via fill agent 10 is applied to fill the via. Etch back unnecessary via fill 10. The SiON film 9 is patterned again to form a trench hard mask. Using this trench hard mask, the trench 6 is opened by dry etching (trench etching) in an etching atmosphere of, for example, fluorocarbon gas, argon gas and oxygen gas.

    Here, the liner film 3 is removed by dry etching (liner etching) using the etching gas containing fluorocarbon described in Section 4. At the same time, the hard mask 9 is also removed. If necessary, the nitrogen plasma treatment described in Section 5 is subsequently performed.

  Thereafter, a barrier metal film is formed by sputtering (or CVD). On top of that, a copper seed layer is formed by sputtering (or CVD) if necessary. Thereafter, copper plating is performed by electroplating or the like, and after an copper annealing process or the like, unnecessary copper is removed and the copper wiring 7 is placed in the trenches and vias (parts of the fourth and third layers). The copper buried wiring structure 47 is completed once.

7). Explanation of device structure by manufacturing process of this embodiment (mainly FIGS. 25 to 27)
FIG. 25 is a schematic cross-sectional view showing an outline of a device structure manufactured by the manufacturing process of the present embodiment. The substrate / device region 31 mainly includes a silicon substrate region 35, a contact tungsten plug region 36, and a first-layer copper wiring M1. The element isolation is an STI (Shallow Trench Isolation) type, and an insulating gate type MOSFET (composing a CMOS FET integrated circuit) is formed in the substrate / device region 31.

  On top of that, there is a fine pitch dual damascene wiring region 32, which is mainly composed of the second-layer copper wiring M2 to the sixth-layer copper wiring M6. Further, a double pitch damascene wiring region 33 is formed thereon, and is mainly composed of a double pitch single damascene wiring M7 and a double pitch dual damascene wiring M8. These first-layer copper wiring M1 to eighth-layer copper wiring M8 (copper embedded wiring structure of each layer) constitute the entire copper embedded wiring structure 47.

  Furthermore, there is a final passivation region 34, which is mainly composed of an upper tungsten plug region 37 and an aluminum pad region 38. The structure of the aluminum pad region 38 is, for example, Ti / TiN / Ti / Al or Al alloy / TiN (thickness nm: 10/50/10/2000/75) from the top. The insulating film constituting the final passivation region 34 is, for example, polyimide film / plasma / silicon nitride film / TEOS silicon oxide film (thickness nm: 4000/600/200) from the top.

  Next, details of the copper buried wiring structure of each layer corresponding to the process of FIG. 23 will be described. The details of the double pitch copper embedded wiring structure will be described with reference to FIG. 26, taking the eighth layer copper wiring M8 as an example. As shown in FIG. 26, the seventh-layer copper buried wiring structure has the same material as the intermediate stopper film 13 (generally the liner film 3 (eg, 75 nm thick)) on the FSG film (eg, 300 nm thick) as the interlayer insulating film 14. (For example, a thickness of 50 nm) is formed by a CVD method. On top of that, there is an FSG film (for example, thickness 325 nm) as the in-layer insulating film 1a, and a TEOS film (for example, thickness 75nm) as the cap layer 1b is formed on the upper layer for matching with the CMP process. ing. Further, a SiCN film as the liner film 3 is formed by a plasma CVD method. On the liner film 3, an FSG film (for example, a thickness of 300 nm) as an interlayer insulating film 14a having an eighth-layer buried wiring structure is formed by a plasma CVD method. A TEOS film (for example, a thickness of 150 nm) as an intermediate cap layer 14b is formed thereon by a plasma CVD method. An SiCN film (for example, a thickness of 50 nm) as an intermediate stopper film 8 is formed thereon by the plasma CVD method as in the seventh layer. On the intermediate stopper film 8, an FSG film (for example, a thickness of 325 nm) is formed as an in-layer insulating film 24a by a plasma CVD method. Further, like the seventh layer, a TEOS film (for example, a thickness of 75 nm) is formed as a cap layer 24b by the plasma CVD method. Copper wirings 7 are embedded through barrier metal films 12 in vias and wiring grooves formed in the insulating films constituting these eighth-layer embedded wiring structures.

  Next, the fine pitch copper embedded wiring structure will be described in detail with reference to FIG. 27, using the fourth layer copper wiring M4 as an example. As shown in FIG. 27, the third-layer copper buried wiring structure has the same material as the intermediate stopper film 13 (generally the liner film 3 (eg, 75 nm thick)) on the FSG film (eg, 300 nm thick) as the interlayer insulating film 14. (For example, a thickness of 50 nm) is formed by a CVD method. On top of that, there is an FSG film (for example, thickness 325 nm) as the in-layer insulating film 1a, and a TEOS film (for example, thickness 75nm) as the cap layer 1b is formed on the upper layer for matching with the CMP process. ing. Further, a SiCN film as the liner film 3 is formed by a plasma CVD method. On the liner film 3, an FSG film (for example, a thickness of 300 nm) as an interlayer insulating film 14a having a fourth-layer buried wiring structure is formed by a plasma CVD method. A TEOS film (for example, a thickness of 150 nm) as an intermediate cap layer 14b is formed thereon by a plasma CVD method. An SiCN film (for example, a thickness of 50 nm) as an intermediate stopper film 8 is formed thereon by the plasma CVD method as in the third layer. On the intermediate stopper film 8, an FSG film (for example, a thickness of 325 nm) is formed as an in-layer insulating film 24a by a plasma CVD method. Further, similarly to the third layer, a TEOS film (for example, a thickness of 75 nm) as a cap layer 24b is formed by the plasma CVD method. Copper wirings 7 are embedded through barrier metal films 12 in vias and wiring grooves formed in the insulating films constituting these fourth-layer embedded wiring structures.

8). Summary As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the in-bay conveyance is performed by RGV or OHT has been described, but AGV may be performed.

  Further, in the above-described embodiment, the wafer storage and transfer using the FOUP has been described. However, a sealed container such as a SMIF pod may be used instead of the FOUP, and even in this case, during storage in the bay station. Pours non-oxidizing dry gas into a sealed container.

  In the above-described embodiment, an example using FSG as the low dielectric constant interlayer insulating film has been mainly described, but it goes without saying that other silica-based low-k insulating films may be used.

1 is an overall plan view showing a wafer transfer system of a semiconductor production line applied in a method for producing a semiconductor integrated circuit device according to an embodiment of the present invention. It is a perspective view which shows an example of the external appearance structure of FOUP used by one embodiment of this invention. It is sectional drawing of FOUP arrange | positioned on the load port of the semiconductor manufacturing apparatus used by one embodiment of this invention. It is a top view which shows an example of the bottom face of FOUP used by one embodiment of this invention. It is the schematic of the FOUP automatic conveyance system using OHT which is one embodiment of this invention. It is explanatory drawing which shows the positioning method of FOUP on the load port of the semiconductor manufacturing apparatus used by one embodiment of this invention. It is explanatory drawing which shows the positioning method of FOUP on the load port of the semiconductor manufacturing apparatus used by one embodiment of this invention. It is a perspective view which shows an example of the inner side structure of the door of FOUP used by one embodiment of this invention. It is sectional drawing which shows an example of the positional relationship of the semiconductor wafer and wafer teeth in FOUP used by one embodiment of this invention. It is explanatory drawing which shows the coupling | bonding state of FOUP and a semiconductor manufacturing apparatus on the load port of the semiconductor manufacturing apparatus used by one embodiment of this invention. It is explanatory drawing which shows the storage means of FOUP in the bay station (stocker) in the manufacturing process of the semiconductor integrated circuit device which is one embodiment of this invention. It is sectional drawing in the middle of the storage in the bay station (stocker) of FOUP used by one embodiment of this invention. It is a top (bottom) figure during storage in the bay station (stocker) of FOUP used by one embodiment of the present invention. It is explanatory drawing which shows the attachment method of the pipe to the breathing filter provided in FOUP used by one embodiment of this invention. It is explanatory drawing which shows the attachment method of the pipe to the breathing filter provided in FOUP used by one embodiment of this invention. It is explanatory drawing which shows the attachment method of the pipe to the breathing filter provided in FOUP used by one embodiment of this invention. It is sectional drawing in the middle of the storage in the bay station (stocker) of FOUP used by one embodiment of this invention. It is a top (bottom) figure during storage in the bay station (stocker) of FOUP used by one embodiment of the present invention. Is an explanatory view showing the relationship between the concentration of O ₂ in the flow rate and the FOUP N ₂ gas into the FOUP in the manufacturing process of a is a semiconductor integrated circuit device an embodiment of the present invention. It is an explanatory view showing the relationship between the dew point of the N ₂ gas flow rate and the FOUP into the FOUP in the manufacturing process of an embodiment a semiconductor integrated circuit device in the form of the present invention. It is a process block flow diagram for explaining a main part of a manufacturing method of a semiconductor integrated circuit device which is an embodiment of the present invention. FIG. 3 is a device schematic cross-sectional flow diagram for explaining a main part of the method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention. It is a device cross section flowchart (process with an intermediate stopper) for demonstrating the principal part of the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. 1 is a device cross-sectional flow diagram (a process without an intermediate stopper) for explaining a main part of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is a device longitudinal cross-sectional view illustrating a cross-sectional structure of an entire device by a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 5 is a detailed partial cross-sectional view showing details of a double pitch portion in the entire device cross-sectional structure by the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention; It is a detailed fragmentary sectional view which shows the detail of the fine pitch part in the whole device sectional structure by the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a data plot diagram showing the yield of defective wafers and the positional relationship in the hoop. It is a data plot figure which shows the relationship between the rate of the lot containing a defect generation | occurrence | production wafer, and polymer removal waiting time. It is process estimation sectional drawing explaining the mechanism of defect generation | occurrence | production. FIG. 6 is a data plot diagram showing the yield of wafers processed by the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention and the positional relationship in the hoop. It is a schematic sectional side view which shows the coupling | bonding state of the manufacturing apparatus and hoop in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is an estimated schematic cross-sectional view of a wafer when a hoop is accommodated for explaining a mechanism of defective slot dependency.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 Insulating copper diffusion barrier film 5 Via 6 Wiring groove 12 Copper diffusion barrier metal film 47 Copper embedding wiring structure 101 Dry etching apparatus 102 Wet processing apparatus 111 Etching process chamber WFR Wafer

Claims (20)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surfaces of the wiring grooves and vias. In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the step (b) includes the following sub-steps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.   In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the wafer transfer container is a sealed type.   In the method of manufacturing a semiconductor integrated circuit device according to the item 3, the wafer transfer container is a hoop.   In the method of manufacturing a semiconductor integrated circuit device according to the item 4, the storage of the step (c) is performed in a standby area.   In the method for manufacturing a semiconductor integrated circuit device according to the item 4, the storage of the step (c) is performed in a stocker.   In the method of manufacturing a semiconductor integrated circuit device according to the item 6, the storage in the step (c) is performed by supplying the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container.   In the method of manufacturing a semiconductor integrated circuit device according to the item 6, the storage in the step (c) is performed by supplying the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the two breathing holes.   In the method for manufacturing a semiconductor integrated circuit device according to the item 8, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.   9. The method for manufacturing a semiconductor integrated circuit device according to the item 8, wherein the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) Insulating copper which is formed in an insulating film on the first main surface of the wafer in the etching process chamber of the dry etching apparatus and which exists on the bottom surface of the via in the copper embedded wiring structure having a wiring groove and a via. Removing the diffusion barrier film by dry etching;
(B) a step of unloading the wafer from the dry etching apparatus after the step (a);
(C) storing the unloaded wafer in a non-oxidizing dry gas atmosphere;
(D) carrying the stored wafer into a wet processing apparatus;
(E) performing a cleaning process for removing the polymer formed during the dry etching on the first main surface side of the loaded wafer in the wet processing apparatus;
(F) A step of unloading the wafer from the wet processing apparatus after the step (e);
(G) After the step (f), a step of forming a copper diffusion barrier metal film on the surface of the insulating film and the inner surface of the wiring groove and via;
Here, the step (a) includes the following substeps:
(A1) performing a dry etching process in an etching atmosphere containing a fluorocarbon-based etching gas in the etching process chamber;
(A2) A step of performing plasma treatment in a non-oxidizing atmosphere containing nitrogen as one of main components in the etching chamber after the step (a1).   12. The manufacturing method of a semiconductor integrated circuit device according to the item 11, wherein the etching atmosphere does not substantially contain a component that generates an oxidizing reactive species.   12. The method for manufacturing a semiconductor integrated circuit device according to the item 11, wherein the etching atmosphere contains trifluoromethane. 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the step (b) includes the following substeps:
(B1) transferring the wafer from the dry etching apparatus to the wafer transfer container in a state where the dry etching apparatus and the wafer transfer container are connected;
(B2) A step of separating the dry etching apparatus and the wafer transfer container.   15. The method for manufacturing a semiconductor integrated circuit device according to item 14, wherein the wafer transfer container is a sealed type.   16. The method for manufacturing a semiconductor integrated circuit device according to the item 15, wherein the wafer transfer container is a hoop.   In the method for manufacturing a semiconductor integrated circuit device according to the item 16, the storage of the step (c) is performed in a stocker.   18. The manufacturing method of a semiconductor integrated circuit device according to the item 17, wherein the storage in the step (c) is performed by supplying the non-oxidizing dry gas atmosphere from the first breathing hole of the wafer transfer container, This is performed by discharging the non-oxidizing dry gas atmosphere from the two breathing holes.   In the method for manufacturing a semiconductor integrated circuit device according to the item 18, the non-oxidizing dry gas atmosphere contains an inert gas as a main component.   In the method for manufacturing a semiconductor integrated circuit device according to the item 18, the non-oxidizing dry gas atmosphere contains nitrogen gas as a main component.

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