JP2011033557A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the measurement accuracy of an electrical test for confirming the electrical characteristics of an electronic component, in a high and low temperature environment. <P>SOLUTION: An electrical tester 20 for placing a QFP (a semiconductor device) 1 in a test temperature environment, and confirming the electrical characteristics includes a test head 21, a socket 22 for mounting the QFP 1, a test board (a wiring board) 23 having a socket mounting area 23c on a front surface 23a, and a temperature-controlled room 24 for maintaining a temperature in an internal space 24a at a test temperature. The test board 23 is enclosed by a partition 25, formed on the test head 21 and fixed to the test head 21 via a hollow space 25a, provided with an inlet path and an outlet path so as to make the back surface 23b face the upper surface 21a of the test head 21. The partition 25 is disposed farther outside of a position at which it is overlapped with the socket mounting area 23c of the test board 23. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to an electrical test process for confirming that electrical characteristics of an assembled semiconductor device satisfy a required specification in a high temperature environment or a low temperature environment.

  The semiconductor device manufacturing process includes an electrical test process for confirming that the assembled semiconductor device satisfies the required specifications in a high temperature environment or a low temperature environment. As the electrical test process, a test apparatus (tester) having a test head to which a performance board on which electronic parts for measuring electrical characteristics of the semiconductor device are mounted is mounted, and a temperature-controlled room for housing the semiconductor device are prepared. In addition, there is a technique for conducting an electrical test by electrically connecting a semiconductor device and a performance board in a temperature-controlled room via, for example, a cable (for example, see Patent Document 1).

JP 2000-147055 A

  In recent years, with stricter requirements for the quality of electronic components such as semiconductor devices, there is an increasing demand for electrical testing of electronic components in a high / low temperature environment. In such a test apparatus that changes the temperature environment and performs an electrical test, the test apparatus on which various circuits for performing the electrical test are formed is damaged due to the test environment temperature, or the measurement accuracy decreases. In order to prevent this, it is necessary to insulate between the temperature-controlled room and the test equipment.

  In particular, during low-temperature environment testing, the exterior of the temperature-controlled room is higher than the dew point temperature of the surrounding atmosphere to prevent adverse effects on the electrical test due to the generation of water droplets (leakage and short-circuiting) and damage caused by dripping water droplets on the test equipment. Therefore, it is necessary to suppress the generation of water droplets due to the condensation of water vapor exceeding the amount of saturated water vapor, so that heat insulation needs to be further strengthened.

  Thus, from the viewpoint of insulating between the temperature-controlled room and the test apparatus, as described in Patent Document 1, the distance between the semiconductor device arranged in the temperature-controlled room and the test apparatus (performance board) is increased. Therefore, it is effective to reduce the thermal gradient by increasing the heat propagation distance from the temperature-controlled room to the test apparatus.

  Also, from the viewpoint of preventing water droplets from dropping onto the test equipment (performance board or test head), the space between the semiconductor equipment and the test equipment (performance board) is filled with dry air to prevent or suppress condensation. Can do.

  However, as a result of examining the electrical test of the semiconductor device (electronic component) in the high / low temperature environment, the present inventor has found the following new problem.

  That is, with the recent increase in speed and functionality of semiconductor devices, it is necessary to improve the measurement accuracy of the electrical test. However, as in Patent Document 1, if the distance between the temperature-controlled room in which the semiconductor device (electronic component) is housed and the test device (performance board or test head) that detects a test current such as a signal current is increased, Since the transmission path (conductive path) distance between the semiconductor device and the test apparatus becomes longer, the impedance of the transmission path through which the test current flows is proportionally increased. As described above, an increase in the impedance component of the transmission path through which the test current flows causes noise in the electrical test, resulting in a decrease in measurement accuracy.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for improving the measurement accuracy of an electrical test for confirming the electrical characteristics of an electronic component in a high / low temperature environment.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
Preparing a semiconductor device having a plurality of first terminals;
Placing the semiconductor device in a heated or cooled test temperature environment and performing an electrical test to confirm the electrical characteristics of the semiconductor device, and
The electrical test apparatus used in the electrical test process is
A test head having a first surface and formed with a control circuit for controlling the operation of the electrical test;
A first region in which the semiconductor device is disposed; a second terminal electrically connected to the first terminal of the semiconductor device; and a second terminal electrically connected to the second terminal and electrically connected to the test head. A socket having three terminals;
A front surface, a back surface located on the opposite side of the front surface, and a socket mounting region disposed on the front surface for mounting the socket, the back surface facing the first surface of the test head, A wiring board surrounded by a partition wall formed on the test head and fixed on the test head via a hollow space having an air supply path and an exhaust path;
A temperature-controlled room having an opening sealed by closely contacting a temperature-controlled room adapter arranged around the socket mounting area of the wiring board and maintaining the temperature of the internal space at the test temperature. And
The step of conducting the electrical test includes
Electrically connecting the first terminal of the semiconductor device to the wiring board and the test head via the socket;
With the semiconductor device exposed to the internal space side of the temperature-controlled room, the opening of the temperature-controlled room is sealed, and the temperature inside the temperature-controlled room is maintained at the test temperature by heating means or cooling means. Process,
Energizing the semiconductor device and measuring electrical characteristics of the semiconductor device, and
The partition wall is disposed outside a position overlapping the socket mounting region of the wiring board.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, it is possible to improve the measurement accuracy of an electrical test for confirming the electrical characteristics of an electronic component in a high / low temperature environment.

It is a top view which shows the outline | summary of the internal structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. In the manufacturing method of the semiconductor device of Embodiment 1 of this invention, it is a principal part enlarged plan view which shows the state which mounted the semiconductor chip on the tab of a lead frame. FIG. 4 is an enlarged plan view of a main part showing a state where wire bonding is performed between pads and leads of the semiconductor chip shown in FIG. 3. It is a principal part enlarged plan view which shows the state which resin-sealed the semiconductor chip and wire which were shown in FIG. It is explanatory drawing which shows typically the outline | summary of the electrical test apparatus which performs the electrical test process of Embodiment 1 of this invention. It is a principal part expanded sectional view which expands and shows the test board periphery of the electrical test apparatus shown in FIG. It is a principal part enlarged plan view which shows the upper surface side of the test head shown in FIG. It is a principal part enlarged plan view which shows the back surface side of the test board | substrate shown in FIG. It is a principal part enlarged plan view which shows the surface side of the test board | substrate shown in FIG. It is a principal part enlarged plan view which shows the state which attached the socket and the constant temperature adapter to the test board | substrate shown in FIG. It is a top view which shows the state which fixed the semiconductor device to the socket shown in FIG. It is a principal part expanded sectional view along the AA line shown in FIG. It is a principal part expanded sectional view which expands and shows the test board periphery of the electrical test apparatus of Embodiment 2 of this invention. It is a principal part enlarged plan view which shows the upper surface side of the test head of the electrical test apparatus shown in FIG. It is a principal part expanded sectional view which expands and shows the test board periphery of the electrical test apparatus of Embodiment 3 of this invention. It is a principal part enlarged plan view which shows the upper surface side of the test head of the electrical test apparatus of Embodiment 4 of this invention.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
<Structure overview of semiconductor device>
FIG. 1 is a plan view showing an outline of the internal structure of the semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. In FIG. 1, in order to show a planar arrangement inside the semiconductor device, it is shown in a state where the sealing resin is transmitted.

  A QFP 1 of the present embodiment shown in FIGS. 1 and 2 is a semiconductor package in which a semiconductor chip 2 is embedded in a sealing resin (sealing body) 6. Here, an external projecting from the sealing resin 6 is used. A QFP (Quad Flat Package) 1 in which a plurality of outer leads 5b as terminals are formed in a gull wing shape will be described as an example.

  The QFP (semiconductor device) 1 includes a semiconductor chip 2 having a main surface 2a, a back surface 2b located on the opposite side of the main surface 2a, and a plurality of pads (terminals) 2c formed on the main surface 2a. . A plurality of semiconductor elements such as transistors and diodes are formed on the main surface 2a of the semiconductor chip 2, and these semiconductor elements are electrically connected to a plurality of pads 2c formed on the main surface 2a. A plurality of semiconductor elements configured on the main surface 2a of the semiconductor chip 2 are electrically connected via a wiring (not shown) formed on the main surface 2a to form an electric circuit. In the present embodiment, for example, a so-called high-frequency circuit that operates at a high frequency of 1 MHz or more is formed.

  In addition, the QFP 1 is electrically connected via a tab (chip mounting region, die pad) 3 for mounting the semiconductor chip 2, a plurality of pads 2 c of the semiconductor chip 2, and a plurality of wires (conductive members) 4. The lead 5 and the sealing resin (sealing body) 6 for sealing the semiconductor chip 2 and the plurality of wires 4 are provided. The semiconductor chip 2 is mounted on the tab 3, and the plurality of pads 2 c of the semiconductor chip 2 are electrically connected to the plurality of leads 5, which are external terminals, via the wires 4. Further, the semiconductor chip 2 and the plurality of wires 4 are resin-sealed with a sealing resin 6, and each of the plurality of leads 5 has one end portion (inner lead 5 a) sealed inside the sealing resin 6, The other end (outer lead 5 b) is disposed outside the sealing resin 6. The outer lead 5b is an external terminal of the QFP1.

  With the recent increase in speed and functionality of electronic devices, semiconductor devices such as the QFP 1 exemplified in Embodiment 1 are used for various purposes. For this reason, the environment in which the semiconductor device is operated is diversified. For example, a semiconductor device that operates normally in a high temperature environment or a low temperature environment is required.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the QFP 1 will be described focusing on the process of performing an electrical test performed to provide a semiconductor device that operates normally in the high temperature environment or the low temperature environment.

  The manufacturing method of the semiconductor device of this embodiment includes a step of preparing a semiconductor device having a plurality of terminals (leads), and the prepared semiconductor device is heated to a temperature higher than room temperature (for example, 25 ° C.) or And a process of conducting an electrical test for confirming the electrical characteristics of the semiconductor device (hereinafter simply referred to as an electrical test process).

  The process for preparing the semiconductor device is not limited to the following, but the process for manufacturing the QFP 1 shown in FIG. 3 to 5 are enlarged plan views of main parts showing steps for preparing the semiconductor device according to the present embodiment. FIG. 3 shows a state in which a semiconductor chip is mounted on a tab of a lead frame, and FIG. FIG. 5 shows a state in which the semiconductor chip and the wire shown in FIG. 4 are sealed with resin.

  In the step of preparing the semiconductor device, the QFP 1 shown in FIGS. 1 and 2 is assembled as follows. First, as shown in FIG. 3, a lead frame 10 and a semiconductor chip 2 which are substrates are prepared, and the semiconductor chip 2 is mounted on the tab 3 of the lead frame 10 (die bonding step). In FIG. 3, the lead frame 10 has a plurality of product formation regions 10a, and each product formation region 10a is integrally formed. In each product forming region 10a, a tab 3, a lead 5, a suspension lead 7, and a tie bar 8 are formed, and these are integrally formed. Specifically, the tab 3 is supported by the suspension lead 7. Further, the plurality of leads 5 are connected via a tie bar 8 and are integrally formed. In this step, the semiconductor chip 2 is fixed on the tab 3 with an adhesive such as a resin paste, for example, with the back surface of the semiconductor chip 2 facing the top surface of the tab 3.

  Next, as shown in FIG. 4, the plurality of pads 2c formed on the main surface 2a of the semiconductor chip 2 and the plurality of leads 5 are electrically connected to each other through the wires 4 (wire bonding step). ).

  Next, as shown in FIG. 5, the semiconductor chip 2 and the plurality of wires 4 mounted in each product formation region 10a are resin-sealed with a sealing resin 6 (sealing process). In this step, the portion inside the tie bar 8 of the lead 5 is sealed with the sealing resin 6, and the portion outside the tie bar 8 is exposed from the sealing resin 6.

  Next, the lead frame 10 is subjected to, for example, solder plating, and an exterior plating layer made of solder is formed in a region exposed from the sealing resin 6 shown in FIG. 5 (plating process).

  Next, the lead frame 10 is cut and separated into individual product formation regions 10a shown in FIG. 5 (individualization step). In this step, the region of the suspension lead 7 exposed from the sealing resin 6 and the tie bar 8 are cut, and the integrally formed leads 5 are individually divided as shown in FIG. In this step, the outer lead 5b is bent as shown in FIG. 2 to obtain QFP1.

  Next, the electrical test process will be described. Note that as a high temperature test performed after the semiconductor device is assembled, there is a so-called accelerated test called burn-in. In this burn-in, a simple electrical test such as a continuity test may be performed. However, this burn-in is distinguished from the electrical test process of the present embodiment. That is, burn-in is a process for detecting and removing an initial failure of a semiconductor device by accelerating it with temperature and voltage, and aims to increase the power of detection in the final inspection of an initial failure mode failure. For this reason, in burn-in, generally, a voltage higher than the voltage expected to be used in an environment of about 125 ° C. is applied to the semiconductor device for several hours to 10 hours.

  On the other hand, the electrical test process of the present embodiment includes a functional test aimed at confirming whether or not required electrical characteristics can be obtained in a temperature environment required by the specifications of the semiconductor device. Therefore, it is necessary to improve measurement accuracy in the electrical test process of this embodiment as compared with a simple electrical inspection performed in burn-in.

  FIG. 6 is an explanatory view schematically showing an outline of an electrical test apparatus that performs the electrical test process of the present embodiment, and FIG. 7 is an enlarged cross-sectional view of a main part showing the test board periphery of the electrical test apparatus shown in FIG. FIG. 8 is an essential part enlarged plan view showing the upper surface side of the test head shown in FIG. 7, and FIG. 9 is an essential part enlarged plan view showing the back side of the test substrate shown in FIG. 10 is an enlarged plan view of a main part showing the surface side of the test board shown in FIG. 7, and FIG. 11 is an enlarged plan view of the main part showing a state where a socket and a temperature-controlled room adapter are attached to the test board shown in FIG. It is. 12 is a plan view showing a state in which the semiconductor device is fixed to the socket shown in FIG. 10, and FIG. 13 is an enlarged cross-sectional view of a main part along the line AA shown in FIG. In order to facilitate understanding of the planar positional relationship between the socket mounting area and the hollow space surrounded by the partition walls, the planar position of the partition walls 25 is indicated by dotted lines in FIGS. 10 and 11.

  The electrical test apparatus 20 used in the electrical test process of the present embodiment is fixed on the test head 21 on which a control circuit for controlling the operation of the electrical test is formed, a socket 22 for fixing the QFP 1, and the test head 21. It has a test board (wiring board, performance board) 23 and a temperature-controlled room 24 that keeps the temperature of the internal space 24a at the test temperature.

  As shown in FIG. 7, the test head 21 has an upper surface 21a that is a surface on which the test substrate 23 is mounted, and a partition wall 25 surrounding a part of the upper surface 21a is disposed on the upper surface 21a. 23 is fixed on the partition wall 25. The fixing means for fixing the test board 23 is not particularly limited, but in the present embodiment, the bolt 29a extending from the test head 21 side to the test board 23 shown in FIG. An example is shown in which it is fixed by inserting it into a through hole and fastening it with a nut 29b. Further, as shown in FIG. 8, a plurality of beams 29 c are arranged around the partition wall 25 to reinforce the support strength of the test substrate 23. Thus, the test substrate 23 is firmly fixed on the partition wall 25, and the upper surface of the partition wall 25 and the back surface 23b of the test substrate 23 are in close contact with each other. From the viewpoint of improving the adhesion between the test substrate 23 and the partition wall 25, an elastic body such as a resin can be interposed between the partition wall 25 and the back surface 23 b of the test substrate 23. The test substrate 23 is electrically connected to a circuit formed on the test head 21 via a connector terminal (terminal) 28 disposed on the upper surface 21 a of the test head 21. The area surrounded by the partition walls 25 is a hollow space 25 a defined by the upper surface 21 a of the test head 21, the partition walls 25 and the back surface 23 b of the test substrate 23. Details of the region where the partition wall 25 is formed and the hollow space 25a surrounded by the partition wall 25 will be described later.

  The test board 23 is a wiring board having a front surface 23a, a back surface 23b located on the opposite side of the front surface 23a, and a socket mounting region 23c for mounting the socket 22 disposed on the front surface 23a. A constant temperature adapter 26 is arranged on the surface 23a so as to surround the socket mounting area 23c. A wiring pattern composed of a plurality of wirings 23d is formed on the front surface 23a and the back surface 23b, respectively. These wirings 23d are electrically connected via a transmission line such as a through hole penetrating from the front surface 23a to the back surface 23b of the test substrate 23. Connected. In addition, a plurality of electronic components 27 such as capacitors and coils are mounted on the test board 23, and electrically through a plurality of terminals 23e and wirings 23d that are electrically connected to the socket 22 mounted on the surface 23a side. It is connected. In the present embodiment, the plurality of electronic components 27 are mounted on the back surface 23b. Further, the test substrate 23 is fixed on the test head 21 via a hollow space 25a surrounded by a partition wall 25 formed on the test head 21 so that the back surface 23b faces the upper surface 21a of the test head 21. .

  The socket 22 is disposed on the surface side of the socket 22 and includes a fixing portion (first region) 22a that fixes and holds the QFP 1, a terminal 22b that is electrically connected to the plurality of leads 5 of the QFP 1, and a terminal 22b. The terminal 22c is electrically connected and electrically connected to the test head 21 via the test board 23. The means for fixing the QFP 1 is not particularly limited. For example, the QFP 1 can be fixed by pressing the upper surface side of the QFP 1 in the direction of the fixing portion 22a with a pressing jig (not shown). The fixing portion 22a is recessed with respect to the upper surface of the socket 22, and the side wall of the recessed portion functions as a guide (positioning guide, guide guide) for adjusting the position of the QFP 1 to a predetermined position.

  Further, in the present embodiment, QFP 1 to be inspected is a semiconductor device in which the lead 5 as an external terminal is led out around the sealing resin 6, so that the plurality of terminals 22 b of the socket 22 are connected to the lead 5, respectively. In addition, they are arranged side by side on the fixing portion 22a according to the arrangement of the plurality of leads 5. In the present embodiment, as the terminals 22b and 22c, so-called pogo pins or contact terminals called pogo contacts that perform electrical connection by pressing a contact pin made of a conductive material against an object to be connected with a spring are used. .

  Further, the socket 22 needs to be frequently attached / detached at least according to a change in the type of the semiconductor device to be measured. Therefore, in the present embodiment, from the viewpoint of facilitating attachment / detachment of the socket 22, a plurality of positioning through holes 23f (see FIGS. 9, 10, and 13) penetrating the test board 23 in the thickness direction are formed. The socket 22 is mounted by inserting and fastening positioning pins 22d (see FIGS. 12 and 13) into the through holes 23f. In addition, in FIG. 13, the structural example which plugs the through-hole 23f with the cap 23g is shown.

  Moreover, the temperature-controlled room 24 has the opening part 24b sealed by making the temperature-controlled room adapter 26 contact | adhere to the lower surface side, and the temperature-controlled room adapter 26 is attached to the lower surface side (for example, the temperature-controlled room 24 with the socket 22 mounted). When close contact with the lower wall of the temperature-controlled room 24 as shown in FIG. 6, the QFP 1 fixed to the socket 22 is exposed to the sealed internal space 24 a of the temperature-controlled room 24. The temperature-controlled room 24 includes a heating means (for example, a heater) or / and a cooling means (for example, a cold air supply / exhaust device) that keeps the internal space 24a at a test temperature, and the internal space 24a has a test higher or lower than normal temperature. It is a mechanism that maintains the temperature. For this reason, the QFP 1 exposed to the internal space 24a can be subjected to an electrical test at the test temperature.

  In the electrical test process of the present embodiment, first, the plurality of leads 5 of the QFP 1 are electrically connected to the test substrate 23 and the test head 21 via the socket 22. In this step, for example, the QFP 1 is mounted on the fixing portion 22a of the socket 22 in advance and is mounted on the socket mounting area 23c to be electrically connected. Alternatively, the QFP 1 can be mounted on the fixing portion 22a of the socket 22 after the socket 22 is mounted on the socket mounting area 23c. Here, when the QFP 1 is mounted on the fixing portion 22a of the socket 22 in advance and mounted in the socket mounting area 23c, it is necessary to attach and detach the socket 22 from the socket mounting area 23c every time the QFP 1 to be measured is replaced. . Therefore, as in the present embodiment, the configuration in which the socket 22 is mounted by inserting and fastening the positioning pins 22d (see FIG. 13) into the through holes 23f (see FIGS. 9 and 10) is It is preferable from the viewpoint of facilitating attachment / detachment and improving the efficiency of the electrical test process.

  Next, with the QFP 1 exposed to the internal space 24a side of the temperature-controlled room 24, the opening 24b of the temperature-controlled room 24 is closed, and the temperature inside the temperature-controlled room 24 is set as the test temperature by the heating means or the cooling means.

  Next, the QFP 1 is energized with the inside of the temperature-controlled room 24 at the test temperature, and the electrical characteristics of the QFP 1 are measured. Examples of the measurement items include an AC timing test and an analog accuracy test. The test temperature varies depending on the specifications of the QFP 1, but for example, the electrical test is performed in an environment of −50 ° C. when the temperature is low and 150 ° C. when the temperature is high.

  Here, when the test is performed in a low temperature or high temperature environment, if no measures are taken, the electrical test apparatus 20 may be damaged due to the test environment temperature or the measurement accuracy may be reduced. For example, when a test is performed in a high-temperature environment, the electronic components 27 mounted on the test board 23 and the circuit of the test head 21 are damaged by heat conduction through a metal material that electrically connects the QFP 1 and the test head 21. There is a case. In addition, the circuit characteristics for testing formed on the test substrate 23 and the test head 21 change due to high temperature, which causes a decrease in measurement accuracy. On the other hand, when the test is performed in a low temperature environment, since the temperature difference between the inside and outside of the temperature-controlled room 24 becomes large, dew condensation occurs in the vicinity of the temperature-controlled room 24, and when a short circuit of a test circuit or a water drop falls on the test head 21, This causes damage to the electrical test apparatus 20.

  From the viewpoint of preventing the electrical test apparatus 20 from being damaged by this heat transfer and reducing the measurement accuracy, the distance between the temperature-controlled room 24 and the test board 23 is increased, and the heat propagation distance from the temperature-controlled room 24 to the test board 23 is increased. Therefore, it is preferable to reduce the thermal gradient.

  However, when the distance from the temperature-controlled room 24 to the test substrate 23 is increased, not only the heat propagation distance but also the transmission distance of the test current such as the signal current becomes longer. As a result, the impedance from the QFP 1 to the test board 23 increases. In the electrical test of the present embodiment, the impedance of the signal current transmission path should be adjusted to be as low as possible and to be a predetermined value (for example, 50Ω) from the viewpoint of signal current transmission and reflection or noise resistance. Is preferred. By suppressing the impedance to be low, variation in impedance in the signal current transmission path can be suppressed, so that measurement accuracy can be improved. Moreover, since the influence of the reflected wave on the transmission path can be reduced by keeping the impedance low, the measurement accuracy can be improved. That is, in the electrical test process of this embodiment, measurement accuracy can be improved by reducing the cause of noise.

  Thus, from the viewpoint of improving measurement accuracy, it is preferable to shorten the transmission distance between the QFP 1 and the test board 23. In particular, in an electrical test of a semiconductor device in which a high-frequency circuit is formed, such as QFP1, the processing speed in the electrical test increases as the operating frequency increases. Therefore, it is necessary to improve measurement accuracy.

  Therefore, in this embodiment, by directly mounting the socket 22 on which the QFP 1 is mounted on the test board 23, the transmission distance between the QFP 1 and the test board 23 is shortened, and the measurement accuracy is improved. For example, as described in Patent Document 1, measurement accuracy can be greatly improved as compared with an electrical test apparatus in which a semiconductor device to be inspected and a performance board are arranged separately.

  When the distance between the QFP 1 and the test board 23 is brought closer as in the electrical test apparatus 20 of the present embodiment, the distance between the temperature-controlled room 24 and the test board 23 is also brought closer. Therefore, in the present embodiment, damage to the electrical test apparatus 20 caused by the test temperature and a decrease in measurement accuracy are prevented by the following.

  In other words, in the present embodiment, the test substrate 23 is connected to the test head via the hollow space 25 a defined by the partition wall 25 formed on the test head 21 so that the back surface 23 b faces the upper surface 21 a of the test head 21. 21 is fixed. The hollow space 25a is disposed at a position overlapping the socket mounting region 23c disposed in the surface 23a (in the thickness direction of the test substrate 23), and the air supply nozzle 25b serving as the air supply path and the exhaust nozzle 25c serving as the exhaust path. It has.

  The electrical test apparatus 20 prevents damage to the electrical test apparatus 20 caused by the test temperature and a decrease in measurement accuracy by convection of gas into the hollow space 25a via the supply nozzle 25b and the exhaust nozzle 25c. be able to.

  For example, when the inside of the temperature-controlled room 24 is heated and an electrical test is performed in a high temperature environment higher than the normal temperature, a gas having a temperature lower than the test temperature (for example, 25 ° C.) or lower than the normal temperature in the hollow space 25a ( By convection of the cooling gas), heat exchange can be performed and the test substrate 23 can be cooled from the back surface 23b side. The gas heated by the heat exchange is discharged from the exhaust nozzle 25c to the outside of the hollow space 25a, and the hollow space 25a is filled with the cooling gas supplied from the air supply nozzle 25b. When performing an electrical test in such a high temperature environment, by cooling the test substrate 23, it is possible to prevent or suppress an increase in the temperature of the test circuit. A decrease can be prevented.

  Further, for example, when the inside of the temperature-controlled room 24 is cooled and an electrical test is performed in a low temperature environment lower than normal temperature, the dew point in the hollow space 25a is lower than the test temperature (for example, -60 ° C. when the test temperature is −50 ° C.). ) Convection of gas (dry gas). Thereby, in the area | region facing the hollow space 25a of the test board | substrate 23, generation | occurrence | production of dew condensation can be prevented. Therefore, it is possible to prevent a short circuit of a test circuit and damage of the electrical test apparatus 20 due to a water drop falling on the test head 21. In the case of convection of the dry gas, it is preferable that the dew point temperature is about 10 ° C. lower than the test temperature in consideration of the safety factor.

  By the way, according to the study of the present inventor, when the electrical test is performed in the low temperature environment using the electrical test apparatus 20, the temperature of the region overlapping the socket mounting region 23c among the back surface 23b of the test substrate 23 is the lowest. I found out. This is because, from the viewpoint of shortening the transmission distance between the QFP 1 mounted on the socket 22 and the test board 23, a heat insulating material having a sufficient thickness cannot be disposed in the socket mounting region 23c. When the through hole 23f for fastening the socket 22 is formed in the socket mounting area 23c as in the present embodiment, the test temperature heat (hot or cold) is tested via the through hole 23f. There is a concern of being transmitted to the back surface 23b side of the substrate 23. On the other hand, in the part other than the socket mounting area 23c, for example, by disposing a heat insulating material on the outer wall of the temperature-controlled room 24, heat transfer to the outside can be prevented or greatly suppressed. The inventor of the present application has found this phenomenon based on the knowledge that in the electrical test under the low temperature environment, condensation is likely to occur particularly in the area overlapping the socket mounting area 23c on the back surface 23b of the test substrate 23. Although the case of the electrical test in the above has been described, the same can be said for the electrical test in a high temperature environment.

  That is, from the above findings found by the inventor of the present application, the test board 23 is most susceptible to the influence of the test temperature (temperature increase due to heat transfer or occurrence of condensation) that overlaps the socket mounting area 23c. It turned out that. For this reason, by taking measures against high temperatures or measures against dew condensation in this region, it is possible to prevent or suppress damage to the electrical test apparatus 20 caused by the test temperature and a decrease in measurement accuracy. In addition, when the countermeasure against high temperature or the countermeasure against condensation is taken on the back surface 23b side of the test substrate 23 as described above, the space required for the countermeasure against the high temperature or the countermeasure against condensation can be greatly reduced. As a result, the transmission distance between the QFP 1 and the test board 23 can be shortened, so that the measurement accuracy can be improved.

  Further, from the viewpoint of efficiently cooling the area overlapping the socket mounting area 23c or preventing condensation on the back surface 23b of the test substrate 23, the air supply nozzle 25b is arranged on the upper surface 21a of the test head 21 (socket mounting area). The region overlaps the region 23c). The air supply nozzle 25b is arranged so that the opening portion faces the region (the region overlapping the socket mounting region 23c), and the gas (cooling gas, dry gas) supplied from the air supply nozzle 25b is the same as that of the test substrate 23. It is supplied toward the area overlapping the socket mounting area 23c on the back surface 23b. As a result, it is possible to efficiently cool the periphery of the region most susceptible to the test temperature or prevent condensation.

  In addition, as described above, the electronic component 27 such as a capacitor and a coil is mounted on the test board 23. The electronic component 27 is a transmission path (conductive path) electrically connected to the QFP 1. It is a component for removing or attenuating noise in a transmission path through which a signal current flows. The noise in the electrical test process includes, for example, noise entering from the power supply line and noise generated inside the electrical test apparatus 20. From the viewpoint of removing or attenuating these noises, the electronic component 27 and the QFP 1 It is preferable to arrange them close to each other. Therefore, in the present embodiment, the transmission distance between the electronic component 27 and the QFP 1 is reduced by mounting the electronic component 27 on the test board 23. Therefore, it is possible to efficiently remove the influence of noise in the electrical test process and improve the measurement accuracy. In the present embodiment, as an example of the electronic component 27, a pin insertion type electronic component in which a lead (terminal) is inserted into a through hole and fixed with a conductive bonding material such as solder from the opposite side of the mounting surface is used. . For this reason, in order to prevent interference between the lead of the electronic component 27 and the socket 22 or the temperature-controlled room adapter 26, the electronic component 27 is mounted beside the temperature-controlled room adapter 26 (on the back surface 23b side in the present embodiment). .

  Further, from the viewpoint of preventing the influence of the test temperature on the electronic component 27 (malfunction due to temperature rise, short circuit due to condensation, etc.), the electronic component 27 is mounted in the hollow space 25a on the back surface 23b side of the test substrate 23. Is preferred. In other words, it is preferable to arrange the partition wall 25 outside the electronic component 27. This is because mounting the electronic component 27 in the hollow space 25a in which the cooling gas or the dry gas stays can suppress the temperature rise of the electronic component 27 or the generation of water droplets.

Similarly, in the present embodiment, the connector terminal 28 is disposed in the hollow space 25a from the viewpoint of preventing the influence of the test temperature on the connector terminal 28 (malfunction due to temperature rise, short circuit due to condensation, etc.). In other words, the partition wall 25 is disposed outside the connector terminal 28. Accordingly, the connector terminal 28 can be cooled or dew condensation can be suppressed, so that the distance between the test board 23 and the test head 21 can be shortened. As a result, the transmission distance between the test substrate 23 and the circuit formed on the test head 21 can be shortened, so that impedance can be reduced and measurement accuracy can be improved. In this embodiment, the socket 22 is directly mounted on the test board 23, and the electronic component 27 for removing or attenuating noise in the transmission path through which the signal current flows is mounted on the test board 23, thereby greatly increasing the measurement accuracy. It becomes possible to improve. But in addition to this,
By reducing the transmission distance from the test board 23 to the test head 21, the measurement accuracy can be further improved.

  After the electrical test is completed, the non-defective product and the defective product are selected, and the non-defective product confirmed to satisfy the required specifications is transported to the next process such as a packaging process and then shipped.

(Embodiment 2)
In the first embodiment, an electronic component 27 for removing or attenuating noise and a connector terminal 28 for electrically connecting the test board 23 and the test head 21 are arranged in a hollow space 25a surrounded by a partition wall 25. did. In the second embodiment, as a modification of the first embodiment, an embodiment in which the electronic component 27 and the connector terminal 28 are arranged outside the hollow space 25a will be described. FIG. 14 is an enlarged cross-sectional view of a main part showing an enlargement of the periphery of the test board of the electrical test apparatus according to the second embodiment. FIG. 15 is an enlarged plan view of the main part showing the upper surface side of the test head of the electrical test apparatus shown in FIG.

  The difference between the electrical test apparatus 30 shown in FIG. 14 and the electrical test apparatus 20 described in the first embodiment is the position of the partition wall 25 and the range of the hollow space 25a. That is, in the electrical test apparatus 30 according to the second embodiment, the partition wall 25 is disposed on the inner side of the electronic component 27 and the connector terminal 28. In other words, the electronic component 27 and the connector terminal 28 are disposed outside the hollow space 25 a surrounded by the partition wall 25.

  As described in the first embodiment, according to the examination by the inventors of the present application, the temperature rises or falls due to the influence of the test temperature, particularly in the region overlapping the socket mounting region 23c, and the surrounding region. Is relatively insensitive to test temperatures. Therefore, if at least the partition wall 25 is disposed outside the region overlapping the socket mounting region 23c, the influence of the test temperature (temperature increase due to heat transfer or occurrence of condensation) can be suppressed. Moreover, by reducing the range (volume) of the hollow space 25a as in the electrical test apparatus 30, the flow of gas (cooling gas, dry gas) in the hollow space 25a can be easily controlled. For example, since the retention of gas in the hollow space 25a can be prevented, the temperature increase in the hollow space 25a can be more reliably suppressed when performing an electrical test in a high temperature environment. As a result, high temperature countermeasures or dew condensation countermeasures can be reliably performed in a region that is particularly important from the viewpoint of preventing the electrical test apparatus from being destroyed or improving measurement accuracy (that is, a region overlapping the socket mounting region 23c).

  Further, if the range surrounded by the partition walls 25 is reduced, the airtightness of the hollow space 25a surrounded by the partition walls 25 can be improved in relation to the processing accuracy. For this reason, it is possible to prevent heat or cold from leaking from the gap between the partition wall 25 and the test substrate 23 to the outside of the hollow space 25a.

  In the electrical test apparatus 30, in order to prevent interference between the exhaust nozzle 25c and the connector terminal 28, the exhaust nozzle 25c is disposed between the adjacent beams 29c as shown in FIG. Yes. Further, from the viewpoint of preventing interference with the connector terminal 28, a method of forming a through hole (exhaust hole) in the partition wall 25 instead of the nozzle can be adopted as the exhaust means.

(Embodiment 3)
In the first embodiment, as an electronic component 27 for removing or attenuating noise, a pin insertion type electronic device in which a lead (terminal) is inserted into a through hole and fixed with a conductive bonding material such as solder from the opposite side of the mounting surface. Embodiments using parts have been described. For this reason, in the electrical test apparatus 20, the electronic component 27 is mounted beside the temperature-controlled adapter 26 in order to prevent interference between the lead of the electronic component 27 and the socket 22 or the temperature-controlled adapter 26.

  In the third embodiment, an embodiment using a so-called surface mount type electronic component 27 in which the terminals of the electronic component 27 are mounted on the surface of a land (terminal) formed on the test substrate 23 will be described. . FIG. 16 is an enlarged cross-sectional view of a main part showing an enlargement of the periphery of the test board of the electrical test apparatus according to the third embodiment.

  The difference between the electrical test apparatus 35 shown in FIG. 16 and the electrical test apparatus 20 described in the first embodiment is the planar position where the electronic component 27 is mounted on the back surface 23 b of the test substrate 23. That is, in the electrical test apparatus 35 according to the third embodiment, the electronic component 27 is mounted in a region overlapping the socket mounting region 23 c on the back surface 23 b of the test board 23. When the electronic component 27 is mounted in a region overlapping the socket mounting region 23c, the transmission distance of the transmission path that electrically connects the QFP 1 and the electronic component 27 is compared with the electrical test apparatus 20 described in the first embodiment. Can be further shortened. As described in the first embodiment, the electronic component 27 is a component (noise filter component) for removing or attenuating noise in a transmission path through which a signal current flows. Therefore, by reducing the transmission distance from the noise filter component to QFP 1 as the measurement target, it is possible to more effectively remove or attenuate noise, and improve measurement accuracy.

  Further, when the electronic component 27 is mounted in a region overlapping with the socket mounting region 23c, the range of the hollow space 25a surrounded by the partition wall 25 can be reduced as compared with the electrical test apparatus 20 described in the first embodiment. . For this reason, as described in the second embodiment, the flow of gas (cooling gas, dry gas) in the hollow space 25a can be easily controlled. Further, the airtightness of the hollow space 25a surrounded by the partition walls 25 can be improved in relation to the processing accuracy.

  Here, in the third embodiment, a land (terminal) 23h is formed on the back surface 23b of the test substrate 23, and the electronic component 27 is placed on the land 23h via solder (conductive connection material) called cream solder, for example. The terminals are joined. Such a mounting method is called a surface mounting method or a surface mounting method, and an electronic component mounted by the surface mounting method is called a surface mounting type electronic component. The land 23h and the wiring 23d formed on the surface of the test substrate 23 are electrically connected via an interlayer conductive path such as a through hole (not shown).

  When the pin insertion type electronic component 27 shown in FIG. 7 described in the first embodiment is used, the tip of the lead (terminal) of the electronic component 27 protrudes to the surface 23a side of the test board 23, so that the socket mounting region 23c and In order to mount in the overlapping region, it is necessary to take measures to prevent interference between the socket 22 and the lead (terminal) of the electronic component 27 on the surface 23a of the test board 23. On the other hand, in the case of a surface mount type electronic component, the terminals of the electronic component 27 can be mounted without protruding to the surface 23a side of the test substrate 23, and therefore can be easily mounted in an area overlapping the socket mounting area 23c. preferable.

  In the third embodiment, the region overlapping the socket mounting region 23c on which the electronic component 27 is mounted is a region where the temperature is most likely to be high or low due to the influence of the test temperature as described above. Therefore, from the viewpoint of preventing the measurement accuracy from being lowered due to the temperature change of the electronic component 27 or the short circuit of the wiring due to condensation, it is necessary to ensure that the atmosphere of the electronic component 27 is a cooling gas or dry gas atmosphere. In other words, as described in the first embodiment, the air supply nozzle 25b is formed on the upper surface 21a of the test head 21 at a position overlapping the area overlapping the socket mounting area 23c, and the opening of the air supply nozzle 25b is formed in the area. It is particularly suitable to apply to the third embodiment from the viewpoint of suppressing the influence of the test temperature on the electronic component 27 mounted in the area overlapping with the socket mounting area 23c.

(Embodiment 4)
In the first embodiment, the embodiment in which the exhaust path is formed at one place of the partition wall 25 as the exhaust path has been described. In the fourth embodiment, an embodiment in which exhaust paths are formed at a plurality of locations of the partition wall 25 will be described. FIG. 17 is an enlarged plan view of a main part showing the upper surface side of the test head of the electrical test apparatus according to the fourth embodiment.

The difference between the electrical test apparatus 37 shown in FIG. 17 and the electrical test apparatus 20 described in the first embodiment is the number of exhaust nozzles 25 c that are exhaust paths formed in the partition wall 25. That is,
In the electrical test apparatus 37, a plurality (four in FIG. 17) of exhaust nozzles 25c are formed in the partition wall 25.

  Thus, by forming a plurality of exhaust passages in the hollow space 25a surrounded by the partition wall 25, the direction in which the gas (cooling gas, dry gas) supplied from the air supply passage (supply nozzle 25b) convects is improved. It becomes easy to control. For example, the retention of gas can be suppressed by adjusting the position and the diameter of the exhaust nozzle 25c according to the arrangement of each member arranged in the hollow space 25a. As a result, high temperature countermeasures and dew condensation countermeasures can be reliably performed in the area overlapping the socket mounting area, which is the area where the temperature is most likely to be high or low due to the test temperature.

  Although the invention made by the inventors of the present application has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in Embodiments 1 to 4, the QFP 1 has been described as an example of a semiconductor device to be measured in an electrical test, but the type and shape of the semiconductor device are not limited to this. For example, it is applied to a semiconductor device (semiconductor package) such as a so-called BGA (Ball Grid Allay) or LGA (Land Grid Allay) in which a semiconductor device is mounted on the surface of a wiring board and a plurality of external terminals are formed on the back side. You can also

  In the first to fourth embodiments, the example in which the nozzle is provided as an example of the air supply path and the exhaust path has been described. However, a method of forming a through hole (air supply hole or exhaust hole) instead of the nozzle is employed. You can also

  The present invention is applicable to a semiconductor device used in a high temperature environment or a low temperature environment.

1 QFP (semiconductor device)
2 Semiconductor chip 2a Main surface 2b Back surface 2c Pad 3 Tab 4 Wire 5 Lead 5a Inner lead 5b Outer lead 6 Sealing resin,
7 Suspension lead 8 Tie bar 10 Lead frame 10a Product formation area 20, 30, 35, 37 Electrical test device 21 Test head 21a Upper surface 22 Socket 22a Fixing part (first area)
22b, 22c Terminal 22d Positioning pin 23 Test board (performance board, wiring board)
23a Front surface 23b Back surface 23c Socket mounting area 23d Wiring 23e Terminal 23f Through hole 23g Cap 23h Land 24 Temperature-controlled room 24a Internal space 24b Opening 25 Partition 25a Hollow space 25b Air supply nozzle 25c Exhaust nozzle 26 Temperature-controlled room adapter,
27 Electronic component 28 Connector terminal 29a Bolt 29b Nut 29c Beam

Claims (15)

Preparing a semiconductor device having a plurality of first terminals;
Placing the semiconductor device in a heated or cooled test temperature environment and performing an electrical test to confirm the electrical characteristics of the semiconductor device, and
The electrical test apparatus used in the electrical test process is
A test head having a first surface and formed with a control circuit for controlling the operation of the electrical test;
A first region in which the semiconductor device is disposed; a second terminal electrically connected to the first terminal of the semiconductor device; and a second terminal electrically connected to the second terminal and electrically connected to the test head. A socket having three terminals;
A front surface, a back surface located on the opposite side of the front surface, and a socket mounting region disposed on the front surface for mounting the socket, the back surface facing the first surface of the test head, A wiring board surrounded by a partition wall formed on the test head and fixed on the test head via a hollow space having an air supply path and an exhaust path;
A temperature-controlled room having an opening sealed by closely contacting a temperature-controlled room adapter arranged around the socket mounting area of the wiring board and maintaining the temperature of the internal space at the test temperature. And
The step of conducting the electrical test includes
Electrically connecting the first terminal of the semiconductor device to the wiring board and the test head via the socket;
With the semiconductor device exposed to the internal space side of the temperature-controlled room, the opening of the temperature-controlled room is sealed, and the temperature inside the temperature-controlled room is kept at the test temperature by heating means or cooling means. Process,
Energizing the semiconductor device and measuring electrical characteristics of the semiconductor device, and
The method of manufacturing a semiconductor device, wherein the partition wall is disposed outside a position overlapping the socket mounting region of the wiring board. In claim 1,
An electronic component for removing or attenuating noise in a conductive path through which a signal current flows among conductive paths electrically connected to the semiconductor device is mounted on the wiring board. Manufacturing method. In claim 2,
At the end of the air supply path on the hollow space side, an air supply nozzle having an opening and formed on the first surface of the test head at a position overlapping the socket mounting area is disposed,
The method of manufacturing a semiconductor device, wherein the opening of the air supply nozzle is arranged to face the socket mounting region. In claim 3,
The step of conducting the electrical test includes
An electrical test performed in a low temperature environment in which the inside of the temperature-controlled room is cooled by a cooling means,
A method of manufacturing a semiconductor device, comprising: checking electrical characteristics of the semiconductor device in a state where a gas having a dew point lower than the test temperature is supplied from the air supply path to the hollow space. In claim 4,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted inside the partition. In claim 5,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted in an area overlapping the socket mounting area on the back surface of the wiring board. In claim 4,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted outside the partition wall. In claim 4,
The wiring board is electrically connected to a circuit formed on the test head via a connector terminal disposed on the first surface,
The method of manufacturing a semiconductor device, wherein the connector terminal is disposed inside the partition wall. In claim 4,
The wiring board is electrically connected to a circuit formed on the test head via a connector terminal disposed on the first surface,
The method of manufacturing a semiconductor device, wherein the connector terminal is disposed outside the partition wall. In claim 3,
The step of conducting the electrical test includes
An electrical test performed in a high temperature environment where the inside of the temperature-controlled room is heated by a heating means,
A method of manufacturing a semiconductor device, comprising: confirming electrical characteristics of the semiconductor device in a state where a gas having a temperature lower than the test temperature is supplied from the air supply path to the hollow space. In claim 10,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted inside the partition. In claim 11,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted in an area overlapping the socket mounting area on the back surface of the wiring board. In claim 10,
The method of manufacturing a semiconductor device, wherein the electronic component is mounted outside the partition wall. In claim 10,
The wiring board is electrically connected to a circuit formed on the test head via a connector terminal disposed on the first surface,
The method of manufacturing a semiconductor device, wherein the connector terminal is disposed inside the partition wall. In claim 10,
The wiring board is electrically connected to a circuit formed on the test head via a connector terminal disposed on the first surface,
The method of manufacturing a semiconductor device, wherein the connector terminal is disposed outside the partition wall.

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